Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-2 and 4-27 are pending. Bolded claim language below regards newly amended subject matter with a corresponding new rejection citation. Newly amended subject matter that is not bolded does not comprise a new rejection citation (utilizes previous interpretation that is unchanged in view of the new language) or is a newly added claim.
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/08/2025 has been entered.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 7-9, 11, 13, 15-20, 22-23, 25, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Patent Application Publication 2021/0327362), herein after referred to as Park, in view of Chen et al. (US Patent Application Publication 2024/0265873), herein after referred to as Chen.
Regarding independent claim 1, Park discloses a display apparatus (Figure 1 reference display 10.), comprising:
a display panel (Figures 1-2 reference display panel 100.) including a plurality of subpixels (Figure 3 reference pixels PX.) in a display area (Figures 2-3 reference display area DA);
a gate driving circuit (Figures 1-3 reference scan driving circuit 111.) disposed along a first direction (Figures 1-2 reference direction Y) in a first area (NDA) of the display panel (Figures 1-3 reference NDA+DA.);
a gate clock line (Figure 2 reference scan timing lines SCL1/SCL2 described in paragraphs [0099]-[0100] to include scan clock lines to which scan clock signals are transmitted.) disposed along the first direction (Y) only in the first area (NDA) (Figure 2 reference SCL1/SCL2 with a portion disposed in only the Y direction and a second portion at an angle between the x and y directions. Further, SCL1/SCL2 are only disposed in the first area NDA outside of the display area DA.), and is configured to supply a gate clock to the gate driving circuit (Paragraphs [0099]-[0100] describes SCL1/SCL2 to include scan clock lines to which scan clock signals are transmitted. Figure 2 depicts SCL1/SCL2 to supply signals to 111.); and
a pseudo gate clock line (Figures 1-3 reference LTL1 described in paragraph [0197] to comprise clock lines CL1 and CL2 along with gate on voltage line VHJL and gate off voltage line VGLL for load matching circuit 130 (depicted in figure 8). Paragraph [0118] describes circuit 130 to output control signal LCL to TFT LMT which outputs gate signal GWL (figure 4). Therefore, citation of LTL1 in figures 1-3 is a reference to CL1, CL2, VGHL, and VGLL. Further, CL1 and CL2 are considered gate clocks since they operate the end goal of gate signal GWL.) (either of CL1 or CL2 not interpreted as the claimed gate clock line) disposed along the first direction (Y) in the first area (NDA), and disposed along a second direction (X) in a second area (NDA2) of the display panel (NDA+DA) where the gate driving circuit is not disposed (Figures 2-3 reference LTL1 disposed in areas where gate driving circuit 111 is not disposed in.), and electrically disconnected to the gate driving circuit (Figures 1-3 reference LTL1 output from DPA to load matching driving circuit and electrically disconnected from gate driving circuit 111.), [ ].
Park does not specifically disclose wherein the pseudo gate clock line is configured to receive a pseudo gate clock that is opposite in phase from the gate clock.
Chen discloses wherein the pseudo gate clock line is configured to receive a pseudo gate clock that is opposite in phase from the gate clock (Figures 1 and 4A reference second clock NCB_O and third clock NCB to be opposite phases as also described in paragraphs [0064] and [0209].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s shift register STAk’s controlled by clock signals with the known technique of the clock signals being different/opposite phases yielding the predictable results of controlling the operation of the shift register as disclosed by Chen (paragraph [0064]).
Regarding claim 2, Park discloses the display apparatus of claim 1, wherein the pseudo gate clock line is disposed outside the gate clock line (Figure 8 reference pseudo gate clock CL1 disposed further out than the gate clock SCL1/SCL2.).
Regarding claim 4, Park discloses the display apparatus of claim 1, wherein a width of the pseudo gate clock line (CL1) is a same as a width of the gate clock line (SCL1/SCL2) in the first area (NDA) (Figures 3 and 8 depicts the line width of CL1/CL2 and SCL1/SCL2 to be the same.).
Regarding claim 7, Park discloses the display apparatus of claim 1, wherein the gate clock line includes an emission clock line (Figure 2 reference adjacent to SCL1/SCL2 lines ETL1/ETL2 described in paragraph [0101] to include emission start lines, emission clock lines, gate on voltage line and gate off voltage line. Paragraph [0306] describes the ETL1 lines to be substantially the same as LTL1. The use of emission clock lines (plural) and the specific description of ETL1 emission clock signal lines to be substantially the same as LTL1 clock signal lines describes two emission clock signals operated substantially similar to figure 8. Therefore, figure 8 will be referenced with ECL1 and ECL2 regarding the disclosed emission clock signal lines represented by CL1 and CL2.) and a scan clock line (CL2), and
wherein the pseudo gate clock line (CL1/CL2) includes:
a pseudo emission clock line (ECL1) (Paragraph [0101] describes more than one emission clock signal.) disposed at a side of the emission clock line (ECL2) (Figure 2 reference ETL1 lines disposed adjacent.); and
a pseudo scan clock line (CL1) disposed at a side of the scan clock line (Figure 2 reference LTL1 disposed adjacent. Figure 8 reference CL2 and CL1 disposed adjacent.).
Regarding claim 8, Park discloses the display apparatus of claim 7, wherein the pseudo emission clock line (Figure 8 CL1 representing location of ECL1 as disclosed in paragraph [0306].) is disposed outside the pseudo scan clock line (Figure 8 CL2 representing the location of ECL2 disposed inside ECL1.).
Regarding claim 9, Park discloses the display apparatus of claim 7, wherein a width of the pseudo emission clock line (ECL1) is a same as a width of the emission clock line (ECL2) in the first area (NDA) (Figures 3 and 8 depicts the line width of CL2 and CL1 (representing ECL2 and ECL1 as disclosed in paragraph [0306]) to be the same.).
Regarding claim 11, Park discloses the display apparatus of claim 7, wherein a width of the pseudo scan clock line (CL1) is a same as a width of the scan clock line (CL2) in the first area (NDA) (Figures 3 and 8 depicts the line width of CL2 and CL1 to be the same.).
Regarding claim 13, Park discloses the display apparatus of claim 7, wherein the gate driving circuit includes a scan driving circuit (Figure 18 111+211),
wherein the scan driving circuit includes:
a first scan driving circuit (111) configured to supply a first scan signal (Figure 3 reference GWL as depicted in figure 4 to be a scan signal applied to the gates of ST2 and ST3.) to a first line subpixel (PX of LMT1); and
a second scan driving circuit (211) configured to supply a second scan signal (GIL as depicted in figure 4 to be a scan signal applied to the gates of ST1) to the first line subpixel (PX of LMT1), and
wherein the pseudo scan clock line includes a 2-1 scan clock line and a 2-2 scan clock line disposed between the first scan driving circuit and the second scan driving circuit (Figure 2 reference SCL1 described in paragraph [0099] to comprise scan clock lines. Further, paragraph [0245] describes circuit 211 to also include timing/clock lines.).
Regarding claim 15, Park discloses the display apparatus of claim 1, further comprising:
a transistor in the display area (Figures 3-4 reference display area DA with pixel PX comprising transistors ST1-ST6+DT.);
a light emitting element over the transistor (LEL); and
an encapsulation layer over the light emitting element (Figure 6 reference encapsulation layer TFEL disposed over the light emitting layer EML.).
Regarding claim 16, Park discloses the display apparatus of claim 15, wherein a semiconductor layer of the transistor includes an oxide semiconductor layer (paragraph [0254]) or a low-temperature polysilicon semiconductor layer (paragraph [0160]).
Regarding claim 17, Park discloses the display apparatus of claim 15 further comprising a touch part on the encapsulation layer (Figure 6 reference touch electrode SENL disposed over TFEL.).
Regarding claim 18, Park discloses the display apparatus of claim 15, wherein the light emitting element (Figure 6 EML) includes a first emission part (172) and a second emission part (172 of a different pixel) disposed between a first electrode (171) and a second electrode (TFE1), and
wherein the first emission part includes an emission layer configured to emit a same color as the second emission part (Paragraph [0178] describes 172 to emit a predetermined color.).
Regarding independent claim 19, Park discloses a display panel (Figures 1-2 reference display panel 100.), comprising:
a display area (Figures 2-3 reference display area DA.) including a plurality of subpixels (Figure 3 reference pixels PX.);
a gate driving circuit (Figures 1-3 reference scan driving circuit 111.) disposed along a first direction (Figures 1-2 reference direction Y) in a first area of a non-display area outside of the display area (Figures 1-3 reference NDA.);
a first gate clock line (Figure 2 reference scan timing lines SCL1/SCL2 described in paragraphs [0099]-[0100] to include scan clock lines to which scan clock signals are transmitted.) disposed along the first direction (Y) only in the first area (NDA) (Figure 2 reference SCL1/SCL2 with a portion disposed in only the Y direction and a second portion at an angle between the x and y directions. Further, SCL1/SCL2 are only disposed in the first area NDA outside of the display area DA.), and is configured to supply a gate clock to the gate driving circuit (Paragraphs [0099]-[0100] describes SCL1/SCL2 to include scan clock lines to which scan clock signals are transmitted. Figure 2 depicts SCL1/SCL2 to supply signals to 111.); and
a pseudo gate clock line (Figures 1-3 reference LTL1 described in paragraph [0197] to comprise clock lines CL1 and CL2 along with gate on voltage line VHJL and gate off voltage line VGLL for load matching circuit 130 (depicted in figure 8). Paragraph [0118] describes circuit 130 to output control signal LCL to TFT LMT which outputs gate signal GWL (figure 4). Therefore, citation of LTL1 in figures 1-3 is a reference to CL1, CL2, VGHL, and VGLL. Further, CL1 and CL2 are considered gate clocks since they operate the end goal of gate signal GWL.) (either of CL1 or CL2 not interpreted as the claimed gate clock line) disposed along the first direction (Y) in the first area (NDA), and disposed along a second direction (X) in a second area (NDA2) of the non-display panel (NDA) where the gate driving circuit is not disposed (Figures 2-3 reference LTL1 disposed in areas where gate driving circuit 111 is not disposed in.), and electrically disconnected to the gate driving circuit (Figures 1-3 reference LTL1 output from DPA to load matching driving circuit and electrically disconnected from gate driving circuit 111.), [ ].
Park does not specifically disclose wherein the pseudo gate clock line is configured to receive a pseudo gate clock that is opposite in phase from the gate clock.
Chen discloses wherein the pseudo gate clock line is configured to receive a pseudo gate clock that is opposite in phase from the gate clock (Figures 1 and 4A reference second clock NCB_O and third clock NCB to be opposite phases as also described in paragraphs [0064] and [0209].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s shift register STAk’s controlled by clock signals with the known technique of the clock signals being different/opposite phases yielding the predictable results of controlling the operation of the shift register as disclosed by Chen (paragraph [0064]).
Regarding claim 20, Park discloses the display panel of claim 19, wherein a width of the pseudo gate clock line (CL1/CL2) is a same as a width of the first gate clock line (SCL1/SCL2) in the first area (NDA) (Figures 3 and 8 depicts the line width of CL2 and CL1 to be the same.).
Regarding claim 22, Park discloses the display panel of claim 19, wherein the first gate clock line includes an emission clock line (Figure 2 reference adjacent to SCL1/SCL2 lines ETL1/ETL2 described in paragraph [0101] to include emission start lines, emission clock lines, gate on voltage line and gate off voltage line. Paragraph [0306] describes the ETL1 lines to be substantially the same as LTL1. The use of emission clock lines (plural) and the specific description of ETL1 emission clock signal lines to be substantially the same as LTL1 clock signal lines describes two emission clock signals operated substantially similar to figure 8. Therefore, figure 8 will be referenced with ECL1 and ECL2 regarding the disclosed emission clock signal lines represented by CL1 and CL2.) and a scan clock line (CL2), and
wherein the pseudo gate clock line (CL1/CL2) includes:
a pseudo emission clock line (ECL1) (Paragraph [0101] describes more than one emission clock signal.) disposed at a side of the emission clock line (ECL2) (Figure 2 reference ETL1 lines disposed adjacent.); and
a pseudo scan clock line (CL1) disposed at a side of the scan clock line (Figure 2 reference LTL1 disposed adjacent. Figure 8 reference CL2 and CL1 disposed adjacent.).
Regarding claim 23, Park discloses the display panel of claim 22, wherein the second emission clock line (Figure 8 CL1 representing location of ECL1 as disclosed in paragraph [0306].) is disposed outside the pseudo scan clock line (Figure 8 CL2 representing the location of ECL2 disposed inside ECL1.).
Regarding claim 25, Park discloses the display panel of claim 22, wherein a width of the pseudo scan clock line (CL1) is a same as a width of the scan clock line (CL2) in the first area (NDA) (Figures 3 and 8 depicts the line width of CL2 and CL1 to be the same.).
Regarding claim 27, Park discloses the display panel of claim 19, wherein the gate driving circuit includes a scan driving circuit (Figure 18 111+211),
wherein the scan driving circuit includes:
a first scan driving circuit (111) configured to supply a first scan signal (Figure 3 reference GWL as depicted in figure 4 to be a scan signal applied to the gates of ST2 and ST3.) to a first line subpixel (PX of LMT1); and
a second scan driving circuit (211) configured to supply a second scan signal (GIL as depicted in figure 4 to be a scan signal applied to the gates of ST1) to the first line subpixel (PX of LMT1), and
wherein the pseudo scan clock line includes a 2-1 scan clock line and a 2-2 scan clock line disposed between the first scan driving circuit and the second scan driving circuit (Figure 2 reference SCL1 described in paragraph [0099] to comprise scan clock lines. Further, paragraph [0245] describes circuit 211 to also include timing/clock lines.).
5. Claim(s) 5-6, 10, 12, 21, 24, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park-Chen in view of Kim et al. (US Patent Application Publication 2021/0142737), herein after referred to as Kim.
Regarding claim 5, Park discloses the display apparatus of claim 1, wherein a width of the pseudo gate clock line (CL1/CL2) is the same as a width of the gate clock line (SCL1/SCL2) in the second area (NDA2) (Figures 3 and 8 depicts the line width of CL1/CL2 and SCL1/SCL2 to be the same.).
Park does not specifically disclose the width of the second gate clock line is different from a width of the gate clock line in the second area.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values in a trench portion of the display (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s pseudo gate clock line CL1/CL2 and the gate clock line SCL1/SCL2 input to a load matching driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
Regarding claim 6, Park discloses the display apparatus of claim 1, wherein a width of the pseudo gate clock line (CL1/CL2) is the same as a width of the gate clock line (SCL1/SCL2) in the second area (NDA2) (Figures 3 and 8 depicts the line width of CL1/CL2 and SCL1/SCL2 to be the same.).
Park does not specifically disclose the width of the second gate clock line is thicker than a width of the gate clock line in the second area.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) in correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s pseudo gate clock line CL1/CL2 and the gate clock line SCL1/SCL2 input to a load matching driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
Regarding claim 10, Park discloses the display apparatus of claim 7, wherein a width of the pseudo emission clock line (ECL1) is a same as a width of the emission clock line (ECL2) in the first area (Figures 3 and 8 depicts the line width of CL2 and CL1 (representing ECL2 and ECL1 as disclosed in paragraph [0306]) to be the same.).
Park does not specifically discloses wherein a width of the pseudo emission clock line in the second area is different from a width of the emission clock line.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) in correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s emission clock line ECL1 and the emission clock line ECL2 input to an emission driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
Regarding claim 12, Park discloses the display apparatus of claim 1, wherein a width of the pseudo scan clock line (CL1) is the same as a width of the scan clock line (CL1) (Figures 3 and 8 depicts the line width of CL2 and CL1 to be the same.).
Park does not specifically disclose the width of the second scan clock line is different from a width of the scan clock line.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values in a trench portion of the display (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s second scan clock line CL1 and the scan clock line CL2 input to a load matching driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
Regarding claim 21, Park discloses the display apparatus of claim 1, wherein a width of the pseudo gate clock line (CL1/CL2) is the same as a width of the first gate clock line (SCL1/SCL2) (Figures 3 and 8 depicts the line width of CL1/CL2 and SCL1/SCL2 to be the same.).
Park does not specifically disclose the width of the pseudo gate clock line is different from a width of the first gate clock line in the second area.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values in a trench portion of the display (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s pseudo gate clock line CL1/CL2 and the first gate clock line SCL1/SCL2 input to a load matching driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
Regarding claim 24, Park discloses the display panel of claim 22, wherein a width of the pseudo emission clock line (ECL1) in the second area (NDA2) is the same as a width of the emission clock line (ECL2) (Figures 3 and 8 depicts the line width of CL2 and CL1 (representing ECL2 and ECL1 as disclosed in paragraph [0306]) to be the same.).
Park does not specifically discloses wherein a width of the pseudo emission clock line in the second area is different from a width of the emission clock line.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) in correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s emission clock line ECL1 and the emission clock line ECL2 input to an emission driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
Regarding claim 26, Park discloses the display panel of claim 22, wherein a width of the pseudo scan clock line (CL1) in the second area (NDA2) is the same as a width of the scan clock line (CL1) (Figures 3 and 8 depicts the line width of CL2 and CL1 to be the same.).
Park does not specifically disclose the width of the second scan clock line is different from a width of the scan clock line.
Kim discloses the width of a line to be different from an adjacent line for forming uniform resistance values and adjusted load values in a trench portion of the display (Figure 4 reference CSLa and CSLc as descried in paragraph [0156].) correspondence to the length of the wire (Longer is thicker Paragraph [0156] and figure 10 reference wa-wc.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s second scan clock line CL1 and the scan clock line CL2 input to a load matching driving circuit with the known technique of respectively comprising a different/thicker line width than the shorter inner line yielding the predictable results of a uniform line resistance and additional means of adjusting the load value as disclosed by Kim (paragraph [0156]).
6. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park-Chen in view of Segawa et al. (US Patent Application Publication 2008/0158453), herein after referred to as Segawa.
Regarding claim 14, Park discloses the display apparatus of claim 7.
Park does not specifically disclose wherein the pseudo emission clock line and the pseudo scan clock line each have a closed loop shape.
Segawa discloses wherein a line may have a closed loop shape for suppressing static electricity (Figure 4 reference 170 and paragraphs [0050]-[0053].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Park’s pseudo emission clock line and pseudo scan clock line with the known technique of each having a closed loop shape yielding the predictable results of suppressing static electricity as disclosed by Segawa (paragraphs [0050]-[0053]).
Response to Arguments
7. Applicant's arguments filed 12/8/2025 have been fully considered but they are not persuasive. Applicant argues, page 12 of the filed remarks, LTL of Park is a line for applying a load timing signal, gate-on voltage, and gate-off voltage to the light emitting driving circuit. In contrast, the pseudo gate clock line of the present application is electrically disconnected to the gate driving circuit.
Emphasis is made on “the” gate driving circuit. The office action above cites figures 1-3 scan driving circuit 111 as the claimed “the gate driving circuit”. While Park comprises more than one gate driving circuit, LTL is connected to load matching driving circuit 130 and is not connected to (electrically disconnected from) “the” gate driving circuit 111.
It is noted that while LTL has a different from applicant’s PSCL lines as recited in their specification, the independent claims do not recite the function or arrangement of the pseudo gate clock line outside of the negative claim limitation. It is not until claim 14 wherein the suppressing of noise function is described. The combination including Segawa discloses a dummy wiring 168 disposed in a loop around the display area. Applicant notes that Segawa discloses the dummy wiring to be connected to ground potential in paragraph [0047]. But said paragraph additionally state to set the potential relative to ground to suppress the rise of noise in ground electric potential. Park-Chen discloses said wires to comprise particular potentials. If applicant comprises particular potential ranges and/or relationship of opposite phases in view of noise, such should be claimed. However, in the current state of any potential so long as its opposite in phase to the gate potential is found disclosed by the combination of arts as disclosed above.
This action is non-final.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E LEIBY whose telephone number is (571)270-3142. The examiner can normally be reached 11-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER E LEIBY/ Primary Examiner, Art Unit 2621