DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 3-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11,430,164. Although the conflicting claims are not identical, they are not patentably distinct from each other because the patented claims recite each limitation or an obvious variant of the limitations of the current claims.
The following table illustrates a mapping of the conflicting claims:
Current Application
1
3
4-9
10
11-12
13
14-16
17
18
19
Patent
1
1
2-7
10
8-9
11
13
14
15
16
The following table illustrates a sample mapping of the limitations of claim 1 of the current application when compared against the pertinent limitations of claim 1 of the patent. The remaining claims can be mapped in a similar manner.
Current Application
U.S. Patent 11,430,164
1. A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising:
1. A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, comprising:
rendering logic arranged to render the tiles using the tile control lists identifying graphics data items present in the tile and texture data; and
the tile control list for a tile identifying graphics data items that are present in the tile … rendering logic arranged to render the tiles using the tile control lists generated by the tiling unit and texture data
per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on resources that are used when processing the tile in the rendering logic [note that the scope of “resources” in the current claim is broader than “only textures” in the patented claim; “resources” can include “only textures,” “textures and other resources,” etc.]
per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based only on a set of textures that will be accessed when processing the tile in the rendering logic
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,039,643. Although the conflicting claims are not identical, they are not patentably distinct from each other because the patented claims recite each limitation or an obvious variant of the limitations of the current claims.
The following table illustrates a mapping of the conflicting claims:
Current Application
1-8
9
10
11-12
13
14-20
Patent
1-8
10
13
11-12
9
14-20
The following table illustrates a sample mapping of the limitations of claim 1 of the current application when compared against the pertinent limitations of claim 1 of the patent. The remaining claims can be mapped in a similar manner.
Current Application
U.S. Patent 12,039,643
1. A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising:
1. A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising:
rendering logic arranged to render the tiles using the tile control lists identifying graphics data items present in the tile and texture data; and
the tile control list for a tile identifying graphics data items that are present in the tile … rendering logic arranged to render the tiles using the tile control lists generated by the tiling unit and texture data
per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on resources that are used when processing the tile in the rendering logic.
per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on resources that are used when processing the tile in the rendering logic
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitations use a generic placeholder “system” that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: a layout processing system and an integrated circuit generation system in claim 20.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites “the tile control lists” in line 3, which lacks proper antecedent basis. Since one is not able to tell what this recitation references, the scope of the claim is unclear.
Claim 1 recites “the tile” in line 4. The claim previously only recites a plurality of tiles, not any singular tile. Since one is not able to tell which singular tile this recitation references, the scope of the claim is unclear.
Claim 12 recites “the one or more least likely to be used textures” in line 2, which lacks proper antecedent basis. Since one is not able to tell what this recitation references, the scope of the claim is unclear.
Claim 19 recites “the tile control lists” in line 6, which lacks proper antecedent basis. Since one is not able to tell what this recitation references, the scope of the claim is unclear.
The remaining claims depend on one of the rejected claims but fail to cure the cited deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10, 13-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fernandez et al. (US 2016/0027144; hereinafter “Fernandez”).
Regarding claim 1, Fernandez discloses A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles (“a graphics processor to sort primitives into tiles including a current tile of pixels for a current frame,” para. 51), the graphics processing unit comprising: rendering logic arranged to render the tiles using the tile control lists identifying graphics data items present in the tile and texture data (“The tiling engine receives geometry, state information, shader information, and texture addresses,” para. 22; “all primitives, such as triangles that are to be rendered, are sorted into the tiles … in a primitive list per tile … When all sorting is done, each tile can be rasterized,” para. 12); and per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on resources that are used when processing the tile in the rendering logic (“a compact representation, such as a hash, is accumulated per tile when the primitive list per tile is created. The compact representation may be based on all geometry, input data, and the relevant states, including all primitives, uniforms, textures, shaders, blending modes, etc.,” para. 14; note that “primitives, uniforms, textures, shaders, blending modes, etc.” are considered to be “resources that are used when processing the tile”).
Regarding claim 2, Fernandez discloses wherein the per-tile hash value is generated based on a shader program used when processing the tile in the rendering logic (“a compact representation, such as a hash … may be based on all geometry, input data, and the relevant states, including all primitives, uniforms, textures, shaders, blending modes, etc.,” para. 14).
Regarding claim 3, Fernandez discloses wherein the rendering logic comprises scheduling logic and processing logic and wherein the scheduling logic is arranged to select a next tile to be scheduled for processing by the processing logic based on a comparison of two or more per-tile hash values (“the next tile identifier to fetch is obtained. For that tile, the current hash or filter is obtained and the ones from the previous frame are obtained in block 52 [of Fig. 2]. A check at 54 determines whether the current and previous hash or filters match. If so, at 56, tile fetching is skipped,” para. 27).
Regarding claim 10, Fernandez discloses wherein the rendering logic comprises a plurality of processing cores (“multi-core processor,” para. 35) and a cache for storing the texture data for use in rendering tiles (“The tiling engine 10 [of Fig. 1] receives geometry, state information, shader information, and texture addresses … This combined data is stored in the tile cache 22,” para. 22), wherein the cache is accessible to each of the plurality of processing cores (e.g. Fig. 1 illustrates the tile cache 22 and unified cache 24 accessible to the processors).
Regarding claim 13, Fernandez discloses wherein the comparison of two per-tile hash values comprises a bit-wise comparison to identify a number of matching bits in the two per-tile hash values (“When the triangle list is created, several hash functions are applied to the information to compare. The results of these hash functions are used to index both bloom filters. For the one related to the current frame, all bits indexed are set. On the other hand, for the bloom filter of the previous frame, the bits indexed are read and a check determines whether all of them are one,” para. 20).
Regarding claim 14, Fernandez discloses wherein each per tile hash value is a Bloom filter (“bloom filter algorithm,” para. 20).
Regarding claim 15, Fernandez discloses wherein the per-tile hash generation logic is arranged to generate, for each tile, a per-tile hash value by: for each texture that will be accessed when processing the tile in the rendering logic, identifying a bit position in the Bloom filter; and setting bits in the Bloom filter at each identified bit position to a default value (“A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures,” para. 10; “The bloom filter algorithm works like the one with hashes, in one embodiment. When the triangle list is created, several hash functions are applied to the information to compare. The results of these hash functions are used to index both bloom filters. For the one related to the current frame, all bits indexed are set,” para. 20).
Regarding claim 16, Fernandez discloses wherein the per-tile hash generation logic is arranged to generate, for each tile, a per-tile hash value by: for each texture that will be accessed when processing the tile in the rendering logic, using each of a plurality of hash functions to identify a bit position in the Bloom filter; and setting bits in the Bloom filter at each identified bit position to a default value (“A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures,” para. 10; “The bloom filter algorithm works like the one with hashes, in one embodiment. When the triangle list is created, several hash functions are applied to the information to compare. The results of these hash functions are used to index both bloom filters. For the one related to the current frame, all bits indexed are set,” para. 20).
Regarding claim 17, Fernandez discloses wherein the per-tile hash generation logic is included in a tiling unit (hash computation unit 13 of Fig. 1 is included in tiling engine 10).
Regarding claim 19, it is rejected using the same citations and rationales described in the rejection of claim 1, with the additional limitation of storing the per-tile hash value for a tile for use by the rendering logic (“A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile,” Fernandez, para. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over a combination of Fernandez and Shim et al. (US 2016/0078667; hereinafter “Shim”).
Regarding claim 4, Fernandez does not disclose identify a candidate set of tiles and to select a next tile to be scheduled for processing by the processing logic based on a comparison of a per-tile hash value of a currently scheduled tile and the per-tile hash value of at least one of the tiles in the candidate set.
In the same art of tile-based rendering, Shim teaches identify a candidate set of tiles (“a plurality of second tiles that are rendered after the first tile,” para. 88) and to select a next tile to be scheduled for processing by the processing logic based on a comparison of a per-tile … value of a currently scheduled tile and the per-tile … value of at least one of the tiles in the candidate set (“determines a rendering order of the plurality of tiles according to a similarity of texture information by comparing texture information between the first tile and the second tiles … the rendering order may be determined so that a third tile that uses in rendering the same texture data as texture data of the first tile the most is rendered after the first tile,” paras. 90-91).
Before the effective filing date of the claimed invention, it would have been obvious to one having ordinary skill in the art to combine the teachings of Shim with the per-tile hash value comparisons of Fernandez. The motivation would have been to “more efficiently use resources” (Shim, abstract). Specifically, Fernandez compares per-tile hash values in order to determine a tile to render next (e.g. by skipping certain tiles), and Shim teaches comparing per-tile values in order to determine a tile to render next from a set of candidate tiles. When the teachings of Fernandez and Shim are combined, the combination renders obvious using the per-tile hash value comparisons of Fernandez to compare a current tile to a set of candidate tiles as in Shim in order to determine an efficient rendering order of tiles.
Regarding claim 5, the combination of Fernandez and Shim renders obvious wherein the currently scheduled tile is either: (i) a current tile being processed, or (ii) a most recently scheduled tile (“select at least one tile that is rendered after the first tile,” Shim, para. 22; see claim 4 for motivation to combine).
Regarding claim 6, the combination of Fernandez and Shim renders obvious identify a candidate set of tiles based, at least in part, on a spatial order scheme (“consider a rendering order of the plurality of tiles, to select the second tile. The controller may also select at least one second tile, from among tiles that are adjacent to the selected first tile in the rendering image,” Shim, para. 109; see claim 4 for motivation to combine).
Regarding claim 7, the combination of Fernandez and Shim renders obvious wherein the candidate set comprises a next N tiles according to the spatial order scheme, wherein N is an integer; or wherein the candidate set comprises a first tile from each of a next N groups of tiles according to the spatial order scheme, wherein N is an integer (“select only one second tile, or a plurality of second tiles, for example, 2 or 4 second tiles,” Shim, para. 61; see claim 4 for motivation to combine).
Regarding claim 8, the combination of Fernandez and Shim renders obvious wherein the candidate set comprises one or more tiles adjacent to the current tile being processed (“consider a rendering order of the plurality of tiles, to select the second tile. The controller may also select at least one second tile, from among tiles that are adjacent to the selected first tile in the rendering image,” Shim, para. 109; see claim 4 for motivation to combine).
Regarding claim 9, Fernandez discloses a cache controller configured to select an item of texture data to be evicted from a cache (“The tiling engine receives geometry, state information, shader information, and texture addresses … This combined data is stored in the tile cache,” para. 22; storage/eviction procedures are inherent in any computer memory).
Fernandez does not disclose evicting textures from a cache based on analysis of two or more per-tile hash values.
In the same art of tile-based rendering, Shim teaches a cache controller (“The memory 720 stores a plurality of pieces of texture data including texture data that is used to render the first tile. The memory 720 may obtain the plurality of pieces of texture data from the graphics memory 122,” para. 110; NOTE: while memory 720 of Fig. 7 is not explicitly labeled as “cache,” it is located proximate to a processor/controller and it stores data from a more distant memory such as graphics memory 122 of Fig. 1, therefore it fits the definition of a cache) configured to select an item of texture data to be evicted from a cache based on analysis of two or more per-tile … values (“the controller 710 may compare the texture information of the first tile with texture information of each of the second tiles … The data changer 730 selects at least one piece of texture data from among a plurality of pieces of texture data of the first tile that are previously stored in the memory 720 according to a frequency of use … The data changer 730 may determine at least one piece of texture data to be changed,” paras. 108-112).
Before the effective filing date of the claimed invention, it would have been obvious to one having ordinary skill in the art to combine the teachings of Shim with the per-tile hash value comparisons of Fernandez. The motivation would have been to “more efficiently use resources” (Shim, abstract). Specifically, Fernandez compares per-tile hash values, and Shim teaches comparing per-tile values in order to determine a texture to evict from a texture cache. When the teachings of Fernandez and Shim are combined, the combination renders obvious using the per-tile hash value comparisons of Fernandez to compare a current tile to a set of candidate tiles as in Shim in order to determine which textures to evict from a texture cache.
Regarding claim 11, the combination of Fernandez and Shim renders obvious identify one or more textures that are least likely to be used based on the analysis of two or more per-tile … values and to select an item of texture data to be evicted from the cache corresponding to a least likely to be used texture (“The data changer 730 [of Fig. 7] selects at least one piece of texture data from among a plurality of pieces of texture data of the first tile that are previously stored in the memory 720 according to a frequency of use for rendering of the second tile, according to a result of the comparison,” Shim, para. 111; see claim 9 for motivation to combine), wherein the per-tile values are per-tile hash values (“hash values per tiles are generated just for comparison purposes,” Fernandez, para. 17).
Regarding claim 12, the combination of Fernandez and Shim renders obvious wherein the cache controller is arranged to identify the one or more least likely to be used textures based on the analysis of per-tile … values for at least one tile being processed by the rendering logic (“The data changer 730 [of Fig. 7] selects at least one piece of texture data from among a plurality of pieces of texture data of the first tile that are previously stored in the memory 720 according to a frequency of use for rendering of the second tile, according to a result of the comparison,” Shim, para. 111; see claim 9 for motivation to combine), wherein the per-tile values are per-tile hash values (“hash values per tiles are generated just for comparison purposes,” Fernandez, para. 17).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Fernandez in view of Kakarlapudi et al. (US 2017/0330372; hereinafter “Kakarlapudi”).
Regarding claim 18, Fernandez does not disclose wherein the graphics processing unit is arranged to store the per-tile hash value for a tile within a tile control list for the tile.
In the same art of tile-based rendering, Kakarlapudi teaches wherein the graphics processing unit is arranged to store the per-tile … value for a tile within a tile control list for the tile (“a primitive list reader configured to read a primitive list associated with a tile to be rendered … the primitive lists could include appropriate information, e.g. metadata,” para. 258).
Before the effective filing date of the claimed invention, it would have been obvious to one having ordinary skill in the art to apply the teachings of Kakarlapudi to the per-tile hash values of Fernandez. Fernandez teaches storing per-tile hash values, which can be considered a form of metadata related to a tile. Kakarlapudi teaches storing per-tile metadata, i.e. a value for a tile, within a control list for the tile. The combination would render obvious storing the per-tile hash value of Fernandez as metadata in the tile control list. The motivation would have been to increase efficiency by placing appropriate data together in memory.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fernandez in view of Official Notice.
Regarding claim 20, Fernandez does not disclose An integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a graphics processing unit as set forth in claim 1; a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the graphics processing unit; and an integrated circuit generation system configured to manufacture the graphics processing unit according to the circuit layout description.
The Examiner takes Official Notice that both the concepts and the advantages of An integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a graphics processing unit … a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the graphics processing unit; and an integrated circuit generation system configured to manufacture the graphics processing unit according to the circuit layout description were well known and expected in the art before the effective filing date of the claimed invention, and it would have been obvious before the effective filing date of the claimed invention to apply integrated circuit description, layout, and manufacturing in Fernandez in order to efficiently manufacture the circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan McCulley whose telephone number is (571)270-3754. The examiner can normally be reached Monday through Friday, 8:00am - 4:30pm.
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/RYAN MCCULLEY/Primary Examiner, Art Unit 2611