Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 06/10/2024. Claims 1-19 are pending on this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 and 4-17 are rejected under 35 U.S.C. 103 as being unpatentable over Charkraborty et al. Pub. No. 2023/0054999 in view of Wang et al. U.S. patent No. 7,375,670.
Regarding claim 1. Fig. 6 of Charkraborty et al. discloses a wideband signal generator (paragraph 0001), comprising: one or more digital-to-analog converters (411, 412…613 DACs), each of the one or more DACs (each of 411, 412…613 DACs) having one or more pipes (pipes of 411, 412…613 DACs) and a sample rate (fs (D1)…fs(DN); a multiplexer (multiplexer 620; paragraph 0049) to receive analog outputs (analog outputs of 411, 412…613 DACs) from at least two pipes (pipes of 411, 412…613 DACs) from the one or more DACs (one or more 411, 412…613 DACs) and multiplex (multiplexer 620) the analog outputs (analog outputs of 411, 412…613 DACs) into an output stream (output stream of multiplex 620 ; a bandpass filter (bandpass filter GEF 431-432; paragraph 0042) to receive the output stream (output stream of 620) and filter out frequency components in the output stream that are outside a target frequency band (higher frequency or lower frequency than the target bandpass frequency is filtered out by the bandpass filter GFE 431-432) and produce a radio frequency (RF) output signal (OUTPUT-1…OUTPUT-M; paragraph 0002) in the in the target frequency band (target frequency band of bandpass filter GFE 431-432); and one or more processors (Fig. 8 {814}) configured to execute code that causes the one or more processors (paragraph 0008 discloses “The program instructions are executable by a processor to cause the processor to perform operations”) to generate digital samples (BB(dN)) and transfer the digital samples (BB(dN)) to the one or more DACs (411, 412…613 DACs), the digital samples(BB(dN)) generated to produce analog outputs (analog outputs of 411, 412…613 DACs) that cause the RF output signal (OUTPUT-1…OUTPUT-M; paragraph 0002) to match the target RF frequency band (target frequency band of bandpass filter GFE 431-432).
However, Charkraborty et al. do not disclose the multiplexer (620) multiplexes zero into an output stream.
Fig. 2 of Wang et al. disclose a digital to analog converter (DAC 202) comprising first and second pipes (first and second pipes 202 to output stream analog output Vin1 and Vin2; see Fig. 3 for disclose first pipe 304 DAC and second pipe 304 DAC to outputs stream of analog outputs Vin1 and Vin2); and a multiplexer (selection 204) to receive analog outputs (Vin1, Vin2) from at least two pipes from the one or more DACs (202) and multiplex (208, 210) the analog outputs (Vin1, Vn2) and zero (zero of 208 and 210) into an output stream (Vo1, Vo2).
Charkraborty et al. and Wang et al. are common subject matter of multiplexing the analog outputs from digital-to-analog converter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the zero in multiplexer of Wang et al. into the multiplexer of Charkraborty et al. for the purpose of providing circuit loading of the DAC is effectively lowered and the layout area is decreased and providing selecting section is coupled to the R-string DAC section to provide dual output voltages according to the LSB bit and a panel polarity signal (Col. 2 lines 3-8 of Wang et al.).
Regarding claim 4. Charkraborty et al. and Wang et al. applied to claim 1 above, Fig. 6 of Charkraborty et al. further disclose wherein the one or more processors (605) are configured to transfer the digital samples (BB(dN)) directly to the one or more DACs (411, 412…613 DACs).
Regarding claim 5. Charkraborty et al. and Wang et al. applied to claim 1 above, Fig. 8 of Charkraborty et al. further comprising a memory (816).
Regarding claim 6. Charkraborty et al. and Wang et al. applied to claim 5 above, Fig.6 and Fig. 8 of Charkraborty et al. further discloses wherein the one or more processors (605, see Fig. 8 {814}) are configured to transfer the digital samples (BB(dN)) to the memory (812 in Fig. 8) , and the memory (812 in Fig. 8) transfers the digital samples (BB(dN)) to the one or more DACs (411, 412…613 DACs).
Regarding claim 7. Charkraborty et al. and Wang et al. applied to claim 1 above, Fig. 6 of Charkraborty et al. further discloses wherein the bandpass filter (431, 432) has a bandwidth greater than a target bandwidth of the RF output signal and narrower than the sample rate (Fig. 5 discloses the target RF output signal bandwidth is inside bandwidth 560, 570 of bandpass filter, and the bandwidth of bandpass 560 and 570 less than the sampling frequency 0-16 Ghz; also see Fig. 2 and Fig. 3 of Charkraborty et al.).
Regarding claim 8. Charkraborty et al. and Wang et al. applied to claim 1 above, Fig. 6 of Charkraborty et al. further discloses wherein the code (paragraph 0008 discloses “The program instructions are executable by a processor to cause the processor to perform operations”) that causes the one or more processors (605) to generate digital samples (BB(dN)) causes the one or more processors (650) to use a starting frequency (fs (D1)…fs(DN)) and a spectrum of the target frequency band (560 and 570 in Fig. 5).
Regarding claim 9. Charkraborty et al. and Wang et al. applied to claim 8 above, Fig. 6 of Charkraborty et al. further discloses wherein the one or more processors (650) are further configured to execute code (paragraph 0008) that causes the one or more processors (650) to set a pipe delay in the one or more DACs (paragraph 004) to be more than twice the target RF frequency band (Fig. 5 discloses more than twice of target frequency of RF signal inside the bandpass bandwidth 560, 570) and the sample rate (Frequency 0..16 Gzh of Fig. 5) to be greater than an instantaneous bandwidth target (target bandwidth of RF signal inside bandwidth of bandpass 560, 570) of the wideband signal generator (Fig. 6).
Regarding claim 10. Charkraborty et al. and Wang et al. applied to claim 8 above, Fig. 6 of Charkraborty et al. further discloses wherein the starting frequency (fs(D1)…fs(DN)) is between a multiple of the sample rate and a multiple of the sample rate minus the Nyquist frequency (see Fig. 3 for Nyquist multiples frequency Zones related to sampling frequency Fs).
Regarding claim 11. Fig. 6 of Charkraborty et al. further discloses wherein the starting frequency (fs(D1)…fs(DN)) is between the sample rate (fs) and a multiple of the sample rate plus the Nyquist frequency (see Fig. 3 for multiple Nyquist frequency Zones related to sampling frequency Fs).
Regarding claim 12. Fig. 6 of Charkraborty et al. discloses a method of generating a wideband signal (paragraph 0001), comprising: using at least two pipes from one or more digital-to-analog converters (pipes of 411, 412…613 DACs) , each of the one or more DACs (each of 411, 412…613 DACs ) having one or more pipes (pipes of 411, 412…613 DACs) and a sample rate (fs(D1)…fs(DN), to generate analog outputs (analog outputs of 411, 412…613 DACs); multiplexing (multiplexer 620) the analog outputs (analog outputs of 411, 412…613 DACs) from the at least two pipes (pipes of 411, 412…613 DACs) to produce an output stream (output stream of 620); filtering (bandpass filter GEF 431-432; paragraph 0042) the output stream (output stream of 620) to remove frequency components in the output stream outside a target frequency band (higher or lower frequency than the target bandpass frequency is filtered out by the bandpass filter GFE 431-432) and produce a radio frequency (RF) output signal (OUTPUT-1…OUTPUT-M; paragraph 0002) in the in the target frequency band (target frequency band of bandpass filter GFE 431-432); and generating digital samples (BB(dN)), the digital samples generated (BB(dN)) to cause the RF output signal (OUTPUT-1…OUTPUT-M; paragraph 0002) matches the target RF frequency band (target frequency band of bandpass filter GFE 431-432).
However, Charkraborty et al. do not disclose multiplexing zero into an output stream.
Fig. 2 of Wang et al. disclose a digital to analog converter (DAC 202) comprising first and second pipes (first and second pipes 202 to output stream analog output Vin1 and Vin2; see Fig. 3 for disclose first pipe 304 DAC and second pipe 304 DAC to outputs stream of analog outputs Vin1 and Vin2); and a multiplexer (selection 204) to receive analog outputs (Vin1, Vin2) from at least two pipes from the one or more DACs (202) and multiplex (208, 210) the analog outputs (Vin1, Vn2) and zero (zero of 208 and 210) into an output stream (Vo1, Vo2).
Charkraborty et al. and Wang et al. are common subject matter of multiplexing the analog outputs from digital-to-analog converter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the zero in multiplexer of Wang et al. into the multiplexer of Charkraborty et al. for the purpose of providing circuit loading of the DAC is effectively lowered and the layout area is decreased and providing selecting section is coupled to the R-string DAC section to provide dual output voltages according to the LSB bit and a panel polarity signal (Col. 2 lines 3-8 of Wang et al.).
Regarding claim 13. Charkraborty et al. and Wang et al. applied to claim 12 above, Fig. 6 of Charkraborty et al. further discloses wherein filtering (431, 432) the output stream (output stream of multiplexer 620) comprises filtering (431, 432) the output stream with a bandpass filter (bandpass filter GEF 431-432; paragraph 0042) having a bandwidth greater than a target bandwidth of the RF output signal and narrower than the sample rate (Fig. 5 discloses the target RF output signal bandwidth is inside bandwidth 560, 570 of bandpass filter, and the bandwidth of bandpass 560 and 570 less than the sampling frequency 0-16 Ghz; also see Fig. 2 and Fig. 3 of Charkraborty et al.).
Regarding claim 14. Charkraborty et al. and Wang et al. applied to claim 12 above, Fig. 6 of Charkraborty et al. further discloses generating the digital samples (BB(dN)) comprises using a starting frequency (fs) and a spectrum of the target frequency band to determine a spectrum of the digital samples (see Fig. 5) .
Regarding claim 15. Charkraborty et al. and Wang et al. applied to claim 14 above, Fig. 6 of Charkraborty et al. further disclose: setting a pipe delay in the one or more DACs (paragraph 004) to be more than twice the target RF frequency band (Fig. 5 discloses more than twice of target frequency of RF signal inside the bandpass bandwidth 560, 570) and the sample rate (fs) to be greater than an instantaneous bandwidth target (target bandwidth of RF signal inside bandwidth of bandpass 560, 570) of the wideband signal generator (Fig. 6).
Regarding claim 16. Charkraborty et al. and Wang et al. applied to claim 14 above, Fig. 6 of Charkraborty et al. further discloses wherein the starting frequency (fs) is between a multiple of the sample rate and a multiple of the sample rate minus the Nyquist frequency (see Fig. 3 for Nyquist frequency Zones related to sampling frequency Fs).
Regarding claim 17. Charkraborty et al. and Wang et al. applied to claim 14 above, Fig. 6 of Charkraborty et al. further discloses wherein the starting frequency (fs) is between the sample rate and a multiple of the sample rate plus the Nyquist frequency (see Fig. 3 for Nyquist frequency Zones related to sampling frequency Fs).
5. Claims 2-3 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Charkraborty et al. and Wang et al. applied to claims 1 and 12 above, in further view of Dempsey U.S. patent No. 9,407,278.
Regarding claims 2 and 18. Charkraborty et al. and Wang et al. applied to claims 1 and 12 above, respectively, do not disclose one DAC and the at least two pipes are from the one DAC.
Fig. 2 of Dempsey discloses digital-to-analog converter comprises: one or more DACs (115, 120, 116, 130) comprise one DAC (115, 120) and the at least two pipes (two pipes of 115 and 102 DACs) are from the one DAC (120, 130).
Charkraborty et al. and Dempsey are common subject matter of digital-to-analog converter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Dempsey into Charkraborty et al. for the purpose of providing DAC architecture comprises multiple stages where each stage is configured to convert a specific group of bits of a N-bit digital word; a first stage will convert a group of higher order bits of the N-bit digital word whereas a second stage will convert remaining lower order bits. In accordance with the present teaching the first and second stages may be provided as parallel paths between an input node of the DAC and an output node of the DAC. In effect this provides a dual output DAC (Col. 1 lines 55-63 of Dempsey).
Regarding claims 3 and 19. Charkraborty et al. and Wang et al. applied to claims 1 and 12 above, respectively, do not disclose at least two DACs, and the at least two pipes comprise at least one pipe from each of the at least two DACs.
Fig. 2 of Dempsey discloses digital-to-analog converter (100) comprises: at least two DACs (115, 116, 120, 130 DACs), and at least two pipes (two pipes of 115 and 116) comprise at least one pipe (pipe of 115 to 120 DACs and pipe of 116 to 130 DACs) from each of the at least two DACs (115, 116, 120, 130 DACs).
Charkraborty et al. and Dempsey are common subject matter of digital-to-analog converter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Dempsey into Charkraborty et al. for the purpose of providing DAC architecture comprises multiple stages where each stage is configured to convert a specific group of bits of a N-bit digital word; a first stage will convert a group of higher order bits of the N-bit digital word whereas a second stage will convert remaining lower order bits. In accordance with the present teaching the first and second stages may be provided as parallel paths between an input node of the DAC and an output node of the DAC. In effect this provides a dual output DAC (Col. 1 lines 55-63 of Dempsey).
Contact Information
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
12/03/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845