DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/2/2026 have been fully considered but they are not persuasive.
Applicant’s arguments are summarized as:
Prior art of record does not teach the “compute assembly” or “processing device” in the claims.
In support of argument ‘a’, applicant argues the claims limitations are for use in a data center, and therefore the elements are different from the computer system taught by the prior art. Applicant lists various details, for example in page 4 of arguments, that differentiates the compute assembly and processing devices from those taught in Robinson. However, it is noted that the features upon which applicant relies (i.e., the compute intensive functions, “large-scale AI/ML model training”, “HPC simulations”, etc…, and associated compute and memory requirements) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
For the claimed language, examiner notes that a laptop from Robinson can certainly read on “a computer assembly” and the laptop would implicitly include one or more CPUs that would read on the “processing device”. The collection of laptops can be used to store various data, which can collectively be referred to as a data center. Merely claiming a “data center” does not require every generic and well-known element of traditional data centers. Applicant’s own application is such an example where many traditional data center elements are not included.
The following rejections are made in light of the amended claims and above arguments.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Robinson et al (pub #US 20110007491 A1, hereinafter Robinson).
Regarding claim 1, Robinson discloses a compute assembly (power devices 330, 340 of figure 3; examples given in paragraph 80, and can be portable computers) of an data center (overall system shown in figure 3), the compute assembly being configured to mount to a base node (the collection of power manager 210s and corresponding power sources shown in figure 3) of the data center, the base node comprising an active carrier plane (power managers 210s, figure 3) mounted to a photovoltaic panel (solar panel 390 shown in figure 3), the compute assembly comprising: at least one processing device (implied in portable computers); at least one memory device (implied in portable computers); and a first connector that is configured to connect to a corresponding second connector of the active carrier plane (smart cables and corresponding jacks and plugs connecting various components to the power managers 210s, figure 3), paragraph 54), the compute assembly being configured to communicate data with the active carrier plane via the first and second connectors (connected via smart cables, using a data communication protocol; paragraph 54).
Examiner notes that the system taught by Robinson is “man-portable”, and therefore can be understood as a system without stationary infrastructure (paragraph 80).
Regarding claim 2, Robinson discloses the compute assembly of claim 1, wherein the compute assembly is configured to receive power from the active carrier plane via the first and second connectors (paragraph 80).
Regarding claim 3, Robinson discloses the compute assembly of claim 1, wherein: the compute assembly further comprises an enclosure comprising an enclosure base and an enclosure cover that is configured for attachment to the enclosure base (Robinson teaches a portable computer in paragraph 80; an outer casing that houses the various computer components is implied and well-known for portable computers); the at least one processing device, the at least one memory device, and the first connector are mounted within the enclosure (outer housing implied for portable computers); and the first connector comprises a first board-mounted connector (connector ends shown in figure 3; note for USB these would be the female receptors on the devices) that extends through an opening in the enclosure (as shown in figure 3, and as known traditionally for USB and other common device interfaces); the second connector comprises a second board-mounted connector (the other end of the connector shown in figure 3); and the first connector is configured to connect (through a cable shown in figure 3) to the second connector by physically mating the first board-mounted connector with the second board-mounted connector (by connecting the two ends as shown in figure 3), the physical mating of the first board-mounted connector with the second board-mounted connector mounting the compute assembly to the active carrier plane (as shown in figures 2 and 3).
Regarding claim 4, Robinson discloses the compute assembly of claim 3, wherein attachment of the enclosure cover to the enclosure base is configured to inhibit an intrusion of outside environmental elements into the enclosure (implied function of enclosures for electronic devices such of portable computers; note Robinson also suggests electrically sealed closures, paragraph 102).
Regarding claim 5, Robinson discloses the compute assembly of claim 1, wherein the at least one memory device comprises at least one volatile memory device and at least one non-volatile memory device (implied for portable computers, typically boot program are stored on a non-volatile memory such as ROM; and application data are stored in faster but volatile working memory such as RAM).
Regarding claim 6, Robinson discloses the compute assembly of claim 1, wherein the at least one processor, the at least one memory device, and the first connector are mounted on a printed circuit board (a motherboard of the portable computer is implied).
Regarding claim 7, Robinson discloses the compute assembly of claim 6, wherein the printed circuit board comprises a computer-on-module (COM, CPU on the motherboard is implicit).
Regarding claim 8, Robinson discloses the compute assembly of claim 6, wherein the printed circuit board comprises a field-programmable gate array, at least one function of the field-programmable gate array being configured to be modifiable while the compute assembly is mounted to the base node (FPGA, paragraph 102).
Regarding claim 9, Robinson discloses the compute assembly of claim 1, wherein the active carrier plane comprises a plurality of second connectors comprising the second connector, each second connector of the plurality of second connectors being configured to interchangeably connect to any of a plurality of different assemblies including the compute assembly (multiple connectors shown in figure 3, connecting to other parts of the system; note Robinson teaches this is unlimitedly scalable, paragraph 89).
Regarding claim 10, Robinson discloses the compute assembly of claim 1, wherein the connection of the first connector to the second connector is configured to mount the compute assembly to the base node (to connect other devices to the power managers and each other; paragraph 89).
Regarding claim 11, Robinson discloses the compute assembly of claim 10, wherein the connection of the first connector to the second connector is configured to mount the compute assembly to the active carrier plane (to connect other devices to the power managers and each other; paragraph 89).
Regarding claim 12, Robinson discloses the compute assembly of claim 1, wherein the compute assembly is configured to perform at least one data center compute operation (store and retrieve data are implicit functions of a portable computer).
Regarding claims 13-20, examiner notes these claims comprise of limitations substantially similar to those in claims 1-3, 6-8, and 10 and are rejected under the same grounds.
Further regarding claim 15, examiner notes that the claim recites “first half” and second “half” without clarifying the unit of measure (e.g. volume, weight, length, etc…). It is assumed that “half” here merely represents one of two ends of a connection between two devices.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181