Prosecution Insights
Last updated: August 17, 2026
Application No. 18/739,322

DATA COMMUNICATION METHOD AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Jun 11, 2024
Priority
Mar 21, 2023 — CN 202310280055.1 +3 more
Examiner
KE, PENG
Art Unit
Tech Center
Assignee
Hisense Group
OA Round
1 (Non-Final)
53%
Grant Probability
Moderate
1-2
OA Rounds
2y 7m
Est. Remaining
75%
With Interview

Examiner Intelligence

Grants 53% of resolved cases
53%
Career Allowance Rate
120 granted / 226 resolved
-6.9% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Typical timeline
4y 9m
Avg Prosecution
18 currently pending
Career history
247
Total Applications
across all art units

Statute-Specific Performance

§101
12.2%
-27.8% vs TC avg
§103
55.0%
+15.0% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 226 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detail Action Application 18/739,322 is filed with claims 1-20 on 06/11/2024. That is a Non-Final Action. Allowable Subject Matter Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Liu US Publication 2024/0153433 in view Cho et al. US Patent 10,269,329. 18/739,322 Liu US Publication 2024/0153433 in view Cho et al. US Patent 10,269,329 Claim 1 A data communication method for an electronic device, wherein the electronic device comprises at least one controller, the at least one controller is connected to at least one drive group, the drive group comprises a plurality of drive chips sequentially connected in series, and at least one drive chip of the plurality of drive chips has a different channel quantity from remainder drive chips; the method comprises: Liu fig. 1 and Fig. 11; p0170-p0178; for each drive group, acquiring drive data and channel quantities of the plurality of drive chips in the drive group; Liu teaches compress image data for each group; see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; It is noted that 18/739,322 specification stated that “where the drive data of the drive group can include a plurality of data segments corresponding one-to-one with the drive chips…” p0004 generating, based on the drive data and the channel quantities, drive data of the drive group; Liu see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; wherein the drive data of the drive group comprises a plurality of data segments corresponding one-to-one with the drive chips, and the drive data of the drive group comprises data compensation information related to the channel quantities of the respective drive chips; and Liu see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; Although Liu teaches drive data related to channel quantities, Liu Fig. 3 item 210 but Liu does not teach compensation information; Cho teaches using compensation information; Cho c8:50-c12:25; It would have been obvious at the time of the invention for a person ordinary skill in the art (POSITA) to include Cho’s teaching with method of Liu in order to provide for a display device capable of decreasing the bezel size of the display device by supplying the scanline enable signal in accordance with the serially-supplied chip selection data and address data. sending, to each drive group, corresponding drive data of the drive group, so that each drive chip in the drive group acquires its corresponding drive data based on the data compensation information. Liu see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; Cho teaches using compensation information; Cho c8:50-c12:25; Claim 2 The method according to claim 1, wherein the generating, based on the drive data and the channel quantities, the drive data of the drive group comprises: acquiring a channel quantity corresponding to a drive chip with a maximal channel quantity in the drive group as a first quantity; and Liu see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; Liu teaches higher requirements is put forward on a data transmission bandwidth between the processor and the controller in the display apparatus, as well as a data transmission bandwidth between the controller and the driver chip, leading to a relatively high cost of the display apparatus. For example, a large number of data channels (which may also be referred to as transmission interfaces) of the driver chip are required, and the cost of the driver chip is relatively high; p0082; p0158-p0159; generating, based on the first quantity and the drive data of the plurality of drive chips, the drive data of the drive group; Liu see Fig. 3, Fig. 16, item 401, p0097-p0106; p0082; p0158-p0159; p0200-p0207; wherein the drive data of the drive group comprises a plurality of data segments corresponding one-to-one with the plurality of drive chips, and each data segment comprises the first quantity of data. Liu see Fig. 3, Fig. 16, item 401, p0097-p0106; p0082; p0158-p0159; p0200-p0207; Clam 3 The method according to claim 2, wherein the data compensation information comprises second quantities of invalid data corresponding to the respective drive chips; for the respective drive chips, the second quantities are differences between the first quantity and the channel quantities of the drive chips; wherein the generating, based on the first quantity and the drive data of the plurality of drive chips, the drive data of the drive group comprises: for each drive chip, adding a second quantity of invalid data to drive data corresponding to the drive chip, to generate a data segment corresponding to the drive chip; and Liu teaches invalid data correspond to driver chip; p0172; Liu see Fig. 3, Fig. 16, item 401, p0097-p0106; p0082; p0158-p0159; p0200-p0207; Cho c8:50-c12:25; integrating data segments corresponding to the plurality of drive chips to obtain the drive data of the drive group; wherein a sequence of the data segments of the plurality of drive chips in the drive data of the drive group is consistent with a sequence of the plurality of drive chips in the drive group. Claim 4 The method according to claim 3, wherein the invalid data, in the data segment corresponding to the drive chip, is located after the drive data of the drive chip. Liu teaches sending invalid data to targeted chip. See Liu p0125-p0135; Claim 5 The method according to claim 1, wherein the generating, based on the drive data and the channel quantities, the drive data of the drive group comprises: generating, according to the drive data of the plurality of drive chips in the drive group, the drive data of the drive group; wherein a sequence of the drive data of the plurality of drive chips in the drive data of the drive group is consistent with a sequence of the plurality of drive chips in the drive group; the data compensation information comprises a reading bit related to the channel quantities of the respective drive chips. Liu see Fig. 3, Fig. 16, item 401, p0097-p0106; p0082; p0158-p0159; p0200-p0207; Cho c8:50-c12:25; Claim 6 The method according to claim 5, wherein the drive data of the drive group comprises a wave head, the reading bit is located at a bit succeeding the wave head. Cho teaches using compensation information within, scanline signal/wave head; Cho c8:50-c12:25; As per claims 7 and 15, they are rejected under the same rationale as claim 1. See rejection above. 18/739,322 Liu US Publication 2024/0153433 in view Cho et al. US Patent 10,269,329 Claim 8 The method according to claim 7, wherein the drive data of the drive group is generated by the at least one controller based on a first quantity and the drive data of the plurality of drive chips, the first quantity is a channel quantity corresponding to a drive chip with a maximal channel quantity in the drive group; the drive data of the drive group comprises a plurality of data segments corresponding one-to-one with the plurality of drive chips, each data segment comprises the first quantity of data; wherein the data compensation information comprises invalid data generated based on the channel quantities of the drive chips; wherein the acquiring, based on the data compensation information, the drive data corresponding to the drive chip from the drive data of the drive group comprises: acquiring a corresponding data segment from the drive data of the drive group in a serial order; acquiring the first quantity, and determining, based on the first quantity and the channel quantity of the drive chip, a quantity of invalid data; and determining, based on the quantity of the invalid data, the drive data of the drive chip from the data segment. Liu fig. 1 and Fig. 11; p0170-p0178; Liu see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; Liu teaches higher requirements is put forward on a data transmission bandwidth between the processor and the controller in the display apparatus, as well as a data transmission bandwidth between the controller and the driver chip, leading to a relatively high cost of the display apparatus. For example, a large number of data channels (which may also be referred to as transmission interfaces) of the driver chip are required, and the cost of the driver chip is relatively high; p0082; p0158-p0159; Liu teaches invalid data correspond to driver chip; p0172; Claim 9 The method according to claim 8, wherein the drive data of the drive group is formed by integrating, by the at least one controller, the data segments corresponding to the plurality of drive chips; wherein the data segment corresponding to the drive chip is generated by adding a second quantity of invalid data to the drive data corresponding to the drive chip, the second quantity is a difference between the first quantity and the channel quantity of the drive chip, a sequence of the data segments of the plurality of drive chips in the drive data of the drive group is consistent with a sequence of the plurality of drive chips in the drive group; the determining, based on the first quantity and the channel quantity of the drive chip, the quantity of the invalid data comprises: subtracting the channel quantity of the drive chip from the first quantity to obtain the second quantity for the invalid data. Liu fig. 1 and Fig. 11; p0170-p0178; Liu see Fig. 3, Fig. 16, item 401, p0097-p0106, p0200-p0207; Liu teaches higher requirements is put forward on a data transmission bandwidth between the processor and the controller in the display apparatus, as well as a data transmission bandwidth between the controller and the driver chip, leading to a relatively high cost of the display apparatus. For example, a large number of data channels (which may also be referred to as transmission interfaces) of the driver chip are required, and the cost of the driver chip is relatively high; p0082; p0158-p0159; Liu teaches invalid data correspond to driver chip; p0172; Claim 11 The method according to claim 8, wherein the invalid data, in the data segment corresponding to the drive chip, is located after the drive data of the drive chip. Liu teaches sending invalid data to targeted chip. See Liu p0125-p0135; Claim 12 The method according to claim 7, wherein the drive data of the drive group is generated by the at least one controller based on the drive data of the plurality of drive chips in the drive group; a sequence of the drive data of the plurality of drive chips in the drive data of the drive group is consistent with a sequence of the plurality of drive chips in the drive group; the drive data of the drive group comprises data compensation data, the data compensation information comprises a reading bit; wherein the acquiring, based on the data compensation information, the drive data corresponding to the drive chip from the drive data of the drive group comprises: starting from the reading bit, acquiring data in the channel quantity of the drive chip as the drive data of the drive chip; and shifting drive data corresponding to a next drive chip of the drive chip to the reading bit. Liu see Fig. 3, Fig. 16, item 401, p0097-p0106; p0082; p0158-p0159; p0200-p0207; Cho c8:50-c12:25; Claim 13 The method according to claim 12, wherein the shifting the drive data corresponding to the next drive chip of the drive chip to the reading bit comprises: deleting the drive data corresponding to the drive chip from the drive data of the drive group; and adding, at an end of the drive data of the drive group, padding data in the channel quantity of the drive chip, so that remaining data in the drive data of the drive group moves sequentially forward by positions in the channel quantity of the drive chip. Liu see Fig. 3, Fig. 16, item 401, p0097-p0106; p0082; p0158-p0159; p0200-p0207; Cho c8:50-c12:25; Claim 14 The method according to claim 12, wherein the drive data of the drive group comprises a wave head, the reading bit is located at a bit succeeding the wave head. Cho teaches using compensation information within, scanline signal/wave head; Cho c8:50-c12:25; Related Prior Art Here a list of controllers of chip group: Lee US Patent 11,562,696: A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines. Takahara US Publication 2007/0080905: It is difficult to obtain a good image display by using an organic EL display panel. An EL display apparatus includes EL elements 15 and driving transistors 11a placed like a matrix, a voltage gradation circuit 1271 for generating a program voltage signal, a current gradation circuit 164 for generating a program current signal, and a drive circuit means of applying a signal to the driving transistors 11a, having switches 151a and 151b for switching between the program voltage signal and the program current signal. Kim et al. US Publication 20070139354: A liquid crystal display (LCD) device includes a data converter for processing first and second data signals, a backlight unit emitting light having a luminance, and a liquid crystal panel supplied with the light. The LCD panel has a first and second region corresponding to the first and second data signals. The data converter differently processes gray levels of the first and second data signals a and the luminance is adjusted when the first and second regions have different brightness. The LCD driving method allows presentation of different image regions on a screen, such as moving image screens and static image screens without brightness degradation. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENG KE whose telephone number is (571)272-4062. The examiner can normally be reached M-F 6:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. PENG KE Primary Examiner Art Unit 2194 /PENG KE/Primary Examiner, Art Unit 2194
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Prosecution Timeline

Jun 11, 2024
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
53%
Grant Probability
75%
With Interview (+22.3%)
4y 9m (~2y 7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 226 resolved cases by this examiner. Grant probability derived from career allowance rate.

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