DETAILED ACTION
The RCE filed September 16, 2026 has been entered. Claims 1-20 are pending. Claims 3 and 13 have been cancelled. Claims 1 and 11 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5 and 11-12, 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 2021/0249057).
Regarding independent claims 1 and its method independent claim 11, Wu et al. disclose a pre-charge system comprising:
a pre-charge circuit (FIG. 1: 108), arranged to perform time-division pre-charge upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals, wherein the memory array comprises a plurality of memory cells each coupled to one of the plurality of bit-line groups (see FIG. 1 and accompanying disclosure); and
a timing controller circuit (110), arranged to generate and output the plurality of pre-charge timing control signals to the pre-charge circuit;
wherein the plurality of bit-line groups comprise a first bit-line group that corresponds to a same memory cell column, and during a period in which none of a read operation and a write operation is performed upon any memory cell coupled to the first bit-line group (see e.g., FIG. 9: 902, a first pre-charging circuit inhibiting charging during a read operation; and 904, a second pre-charging circuit inhibiting charging during the read operation; further, performing a pre-charge operation during periods other than read /write operations are inherent characteristic of memory operations), one pre-charging of a same bit-line included in the first bit-line group is divided into a plurality of phases that are sequentially enabled by the plurality of pre-charge timing control signals, where the plurality of pre-charge timing control signals comprise a first pre-charge timing control signal and a second pre-charge timing control signal (see FIGS. 2-3, FIG. 6 and FIG. 8, and accompanying disclosure), and the plurality of phases comprise:
a first phase (see FIG. 2 and FIG. 3: 310, at 312), enabled by the first pre-charge timing control signal, for pre-charging the same bit-line to a first voltage (see FIG. 3: BL/BLB at BLEQB1=”L” and BLEQB2=”H”); and
a second phase (see FIG. 2 and FIG. 3: 310, at 314), enabled by the second pre-charge timing control signal after the first phase is enabled by the first pre-charge timing control signal, for pre-charging the same bit-line to a second voltage (see FIG. 3: BL/BLB at BLEQB1=”L” and BLEQB2=”L”) different from the first voltage.
Regarding claims 2 and 12, which depends from claims 1 and 11, respectively.
Wu et al. disclose each of the plurality of memory cells is a static random access memory (SRAM) cell (FIG. 1).
Regarding claims 4 and 14, which depends from claims 1 and 11, respectively.
Wu et al. disclose the pre-charge circuit comprises: a plurality of pre-charge sub-circuits, coupled to the plurality of bit-line groups, respectively, wherein each of the plurality of pre-charge sub-circuits receives the plurality of pre-charge timing control signals, and comprises: an equalizer; and a pre-charge device; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the equalizer and the pre-charge device sequentially (see e.g., FIGS. 2, 6 and 8 and accompanying disclosure).
Regarding claims 5 and 15, Wu et al. teach the limitations of claims 1 and 11, respectively.
Wu et al. disclose teach the pre-charge circuit comprises: a plurality of pre-charge sub-circuits, coupled to the plurality of bit-line groups, respectively, wherein each of the plurality of pre-charge sub-circuits receives the plurality of pre-charge timing control signals, and comprises: a first pre-charge device; and a second pre-charge device, wherein pre-charge strength of the second pre-charge device is larger than pre-charge strength of the first pre-charge device; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the first pre-charge device and the second pre-charge device sequentially (see e.g., FIGS. 2, 6 and 8 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 and 16-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0249057) in view of Yang et al. (US 9,685,224).
Regarding claims 6-7 and 16-17, Wu et al. teach the limitations of claims 1 and 11, respectively.
Wu et al. do not explicitly disclose the timing controller circuit comprises: an adjustable delay circuit, arranged to adjust an interval between two of the plurality of pre-charge timing control signals; and the adjustable delay circuit operates in response to a user input.
However, the claimed limitation is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Yang et al. (US 9,685,224), e.g., col. 6, lines 35-40: … a delay circuit to delay activation of the pre charge circuits …; and col. 9, line 58: … receive a delay signal CKPB_DLY.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in pre-charging circuits because these conventional technology are well established in the art of the memory devices.
Regarding claims 8 and 18, Wu et al. teach the limitations of claims 1 and 11, respectively.
Wu et al. do not explicitly disclose the limitations of claims 8 and 18.
Yang et al. teach the deficiencies, i.e., the timing controller circuit comprises: a tracking circuit, arranged to adjust an interval between two of the plurality of pre-charge timing control signals by monitoring at least one parameter of the memory array (e.g., col. 6, lines 7-40, i.e., sequentially controlling pre-charge signals by adjusting RC delay (claimed monitoring at least one parameter of the memory array)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yang et al. to the teaching of Tachibana such that a memory, as taught by Tachibana, utilizes timing circuitry, as taught by Yang et al., for the purpose of controlling charging segment of memory arrays, thereby improving memory performance.
Yang et al.’ timing control circuit do not explicitly disclose a tracking circuit.
However, a tracking circuit tracks signals in a memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in tracking circuits because these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 19, Wu et al. and Yang et al. teach the limitations of claims 8 and 18, respectively.
Yang et al. further teach the at least one parameter of the memory array comprises a number of memory cells in a bit-line direction (e.g., FIG. 1., i.e., RC delay in bit-line direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Yang et al. for the same purpose of controlling charging segment of memory arrays, thereby improving memory performance.
Regarding claims 10 and 20, Wu et al. and Yang et al. teach the limitations of claims 8 and 18, respectively.
Yang et al. further teach the at least one parameter of the memory array comprises a number of memory cells in a word-line direction (e.g., FIG. 1., i.e., RC delay in word-line direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Yang et al. for the same purpose of controlling charging segment of memory arrays, thereby improving memory performance.
Response to Argument
The RCE filed 09/16/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
