DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending for examination.
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 18 of U.S. Patent No.12,045,674. Although the claims at issue are not identical, they are not patentably distinct from each other
Claim 1 of current application 18/739,583
Claim 1 of Patent Number 12,045,674
1. A neural processing device comprising a plurality of blocks, the neural processing device comprising: a first block including a first neural core that operates at a first operating frequency; a second block including a second neural core that is connected to the first block and operates at the first operating frequency; a third block including a third neural core that is connected to the second block and operates at the first operating frequency; and a data communication mode determiner that is connected to the first to third blocks, respectively, and controls data communication among the first to third blocks, and determines a mode of data communication among the first to third blocks, wherein, when a clock skew occurs in data communication between the second block and the third block, the data communication mode determiner controls the mode of data communication between the second block and the third block as an asynchronous data communication mode.
2. The neural processing device according to claim 1, wherein the data communication mode determiner is capable of controlling the first block to operate at an operating frequency different from the first operating frequency, is capable of controlling the second block to operate at an operating frequency different from the first operating frequency, and is capable of controlling the third block to operate at an operating frequency different from the first operating frequency.
3. The neural processing device according to claim 2, wherein the data communication mode determiner controls the first block to operate at a second operating frequency different from the first operating frequency, and controls the mode of data communication between the first block and the second block as the asynchronous data communication mode.
4. The neural processing device according to claim 3, wherein the data communication mode determiner further controls the second block to operate at the second operating frequency, and changes the mode of data communication between the first block and the second block to a synchronous data communication mode, wherein, after the mode of data communication between the first block and the second block is changed to the synchronous data communication mode, when a clock skew occurs in data communication between the first block and the second block, the data communication mode determiner further changes the mode of data communication between the first block and the second block to the asynchronous data communication mode.
5. The neural processing device according to claim 1, wherein, when a clock skew occurs in data communication between the first block and the second block, the data communication mode determiner controls the mode of data communication between the first block and the second block as the asynchronous data communication mode.
6. The neural processing device according to claim 1, further comprising a command processor that controls the data communication mode determiner.
7. The neural processing device according to claim 1, wherein, each of the first block and the second block further includes a memory.
8. A neural processor comprising a plurality of neural cores, the neural processor comprising: a first neural core that operates at a first operating frequency; a second neural core that is connected to the first neural core and operates at the first operating frequency; a first memory that is connected to the first neural core and operates at a second operating frequency different from the first operating frequency; a task manager that configures a data communication path among the first neural core, the second neural core, and the first memory; and a data communication mode determiner that is connected to the first neural core, the second neural core, and the first memory, respectively, and controls data communication among the first neural core, the second neural core, and the first memory, and determines a mode of data communication among the first neural core, the second neural core, and the first memory, wherein, when a clock skew occurs in data communication between the first neural core and the second neural core, the data communication mode determiner controls the mode of data communication between the first neural core and the second neural core as an asynchronous data communication mode.
9. The neural processor according to claim 8, wherein, in a maximum computation speed mode, the data communication mode determiner controls each of the first neural core and the second neural core to operate at a third operating frequency greater than the first operating frequency.
10. The neural processor according to claim 9, wherein, in the maximum computation speed mode, the data communication mode determiner controls the first memory to operate at the third operating frequency and controls the mode of data communication between the first neural core and the first memory as a synchronous data communication mode.
11. The neural processor according to claim 10, wherein, when a clock skew occurs in data communication between the first neural core operating at the third operating frequency and the first memory operating at the third operating frequency, the data communication mode determiner changes the mode of data communication between the first neural core and the first memory to the asynchronous data communication mode.
12. The neural processor according to claim 8, wherein, in a minimum power use mode, the data communication mode determiner controls each of the first neural core and the second neural core to operate at a fourth operating frequency smaller than the first operating frequency.
13. The neural processor according to claim 12, wherein, in the minimum power use mode, the data communication mode determiner controls the first memory to operate at the fourth operating frequency and controls the mode of data communication between the first neural core and the first memory as a synchronous data communication mode.
14. The neural processor according to claim 13, wherein, when a clock skew occurs in data communication between the first neural core operating at the fourth operating frequency and the first memory operating at the fourth operating frequency, the data communication mode determiner changes the mode of data communication between the first neural core and the first memory to the asynchronous data communication mode.
15. The neural processor according to claim 8, further comprising: a first data line connecting the first neural core and the second neural core in series and transmitting data in a first direction; a second data line connecting the first neural core and the second neural core in series and transmitting data in a second direction opposite to the first direction; and a second memory that is connected to the second neural core and operates at the first operating frequency, wherein the task manager controls the first data line and the second data line so as to configure a data path among the first neural core, the second neural core, the first memory, and the second memory, and the data communication mode determiner determines the mode of data communication between the second neural core and the second memory to be a synchronous data communication mode.
16. The neural processor according to claim 15, wherein, when a clock skew occurs in data communication between the second neural core and the second memory, the data communication mode determiner controls the mode of data communication between the second neural core and the second memory as the asynchronous data communication mode.
17. The neural processor according to claim 16, wherein the task manager controls the first data line and the second data line so as to configure a first data path in which data is provided in the first direction from the first memory to the first neural core and data is provided in the second direction from the first neural core to the first memory, and controls the first data line and the second data line so as to configure a second data path in which data is provided in the second direction from the second memory to the second neural core and data is provided in the first direction from the second neural core to the second memory.
18. A method for determining a data communication mode, the method being performed in a neural processing device including a first block including a first neural core, a second block including a second neural core, and a third block including a third neural core, which perform data communication and comprising: controlling the first block to operate at a first operating frequency; controlling the second block connected to the first block to operate at the first operating frequency; controlling the third block connected to the second block to operate at a second operating frequency different from the first operating frequency; and controlling a mode of data communication between the first block and the second block as an asynchronous data communication mode when a clock skew occurs in data communication between the first block and the second block.
19. The method according to claim 18, further comprising: controlling the first block to operate at the second operating frequency different from the first operating frequency; and controlling a mode of data communication between the first block and the third block to a synchronous data communication mode.
20. The method according to claim 19, further comprising: after the mode of data communication between the first block and the third block is controlled as the synchronous data communication mode, when a clock skew occurs in data communication between the first block and the third block, changing the mode of data communication between the first block and the third block to the asynchronous data communication mode.
1. A neural processing device comprising a neural processor comprising a plurality of neural cores, the neural processing device comprising: a first neural core that operates at a first operating frequency; a second neural core that is connected to the first neural core and operates at the first operating frequency; a third neural core that is connected to the second neural core and operates at the first operating frequency; and a data communication mode determiner that is connected to the first to third neural cores, respectively, and controls data communication among the first to third neural cores, and determines a mode of data communication among the first to third neural cores, wherein the data communication mode determiner determines a mode of data communication between the first neural core and the second neural core to be a synchronous data communication mode, and determines a mode of data communication between the second neural core and the third neural core to be a synchronous data communication mode, and when a clock skew occurs in data communication between the second neural core and the third neural core, the data communication mode determiner maintains the mode of data communication between the first neural core and the second neural core as the synchronous data communication mode, and changes the mode of data communication between the second neural core and the third neural core to an asynchronous data communication mode.
2. The neural processing device according to claim 1, wherein the data communication mode determiner is capable of controlling the first neural core to operate at an operating frequency different from the first operating frequency, is capable of controlling the second neural core to operate at an operating frequency different from the first operating frequency, and is capable of controlling the third neural core to operate at an operating frequency different from the first operating frequency.
3. The neural processing device according to claim 2, wherein the data communication mode determiner controls the first neural core to operate at a second operating frequency different from the first operating frequency, and changes the mode of data communication between the first neural core and the second neural core to the asynchronous data communication mode.
4. The neural processing device according to claim 3, wherein the data communication mode determiner further controls the second neural core to operate at the second operating frequency, and changes the mode of data communication between the first neural core and the second neural core to the synchronous data communication mode, wherein, after the mode of data communication between the first neural core and the second neural core is changed to the synchronous data communication mode, when a clock skew occurs in data communication between the first neural core and the second neural core, the data communication mode determiner further changes the mode of data communication between the first neural core and the second neural core to the asynchronous data communication mode.
5. The neural processing device according to claim 1, wherein, when a clock skew occurs in data communication between the first neural core and the second neural core, the data communication mode determiner changes the mode of data communication between the first neural core and the second neural core to the asynchronous data communication mode.
6. The neural processing device according to claim 1, further comprising a command processor that controls the data communication mode determiner.
7. The neural processing device according to claim 1, wherein, each of the first neural core and the second neural core is either a neural core or a memory.
8. A neural processor comprising a plurality of neural cores, the neural processor comprising: a first neural core that operates at a first operating frequency; a second neural core that is connected to the first neural core and operates at the first operating frequency; a first memory that is connected to the first neural core and operates at a second operating frequency different from the first operating frequency; a task manager that configures a data communication path among the first neural core, the second neural core, and the first memory; and a data communication mode determiner that is connected to the first neural core, the second neural core, and the first memory, respectively, and controls a data communication among the first neural core, the second neural core, and the first memory, and determines a mode of data communication among the first neural core, the second neural core, and the first memory, wherein the data communication mode determiner determines the mode of data communication between the first neural core and the second neural core to be the synchronous data communication mode, and determines the mode of data communication between the first neural core and the first memory to be the asynchronous data communication mode, wherein, in a maximum computation speed mode, the data communication mode determiner controls each of the first neural core and the second neural core to operate at a third operating frequency greater than the first operating frequency.
9. The neural processor according to claim 8, wherein, in the maximum computation speed mode, the data communication mode determiner controls the first memory to operate at the third operating frequency and changes the mode of data communication between the first neural core and the first memory to the synchronous data communication mode.
10. The neural processor according to claim 9, wherein, when a clock skew occurs in data communication between the first neural core operating at the third operating frequency and the first memory operating at the third operating frequency, the data communication mode determiner changes the mode of data communication between the first neural core and the first memory to the asynchronous data communication mode.
11. The neural processor according to claim 8, wherein, in a minimum power use mode, the data communication mode determiner controls each of the first neural core and the second neural core to operate at a fourth operating frequency smaller than the first operating frequency.
12. The neural processor according to claim 11, wherein, in the minimum power use mode, the data communication mode determiner controls the first memory to operate at the fourth operating frequency and changes the mode of data communication between the first neural core and the first memory to the synchronous data communication mode.
13. The neural processor according to claim 12, wherein, when a clock skew occurs in data communication between the first neural core operating at the fourth operating frequency and the first memory operating at the fourth operating frequency, the data communication mode determiner changes the mode of data communication between the first neural core and the first memory to the asynchronous data communication mode.
14. The neural processor according to claim 8, further comprising: a first data line connecting the first neural core and the second neural core in series and transmitting data in a first direction; a second data line connecting the first neural core and the second neural core in series and transmitting data in a second direction opposite to the first direction; and a second memory that is connected to the second neural core and operates at the first operating frequency, wherein the task manager controls the first data line and the second data line so as to configure a data path among the first neural core, the second neural core, the first memory, and the second memory, and the data communication mode determiner determines the mode of data communication between the second neural core and the second memory to be the synchronous data communication mode.
15. The neural processor according to claim 14, wherein, when a clock skew occurs in data communication between the second neural core and the second memory, the data communication mode determiner changes the mode of data communication between the second neural core and the second memory to the asynchronous data communication mode.
16. The neural processor according to claim 15, wherein the task manager controls the first data line and the second data line so as to configure a first data path in which data is provided in the first direction from the first memory to the first neural core and data is provided in the second direction from the first neural core to the first memory, and control the first data line and the second data line so as to configure a second data path in which data is provided in the second direction from the second memory to the second neural core and data is provided in the first direction from the second neural core to the second memory.
18. A method for determining a data communication mode, the method being performed in a neural processing device including first, second, and third neural core performing data communication and comprising: controlling the first neural core to operate at a first operating frequency; controlling the second neural core connected to the first neural core to operate at the first operating frequency; controlling the third neural core connected to the second neural core to operate at a second operating frequency different from the first operating frequency; determining a mode of data communication between the first neural core and the second neural core to be a synchronous data communication mode; and determining a mode of data communication between the second neural core and the third neural core to be an asynchronous data communication mode, when a clock skew occurs in data communication between the first neural core and the second neural core, changing the mode of data communication between the first neural core and the second neural core to the asynchronous data communication mode.
.674 teaches limitations of claims 1 – 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 3, 5 – 10, 12 – 13, and 18 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al., (US PUB 2020/0082263 hereinafter Song) in view of Ovsiannikov et al., (US PUB 2019/0187983 hereinafter Ovsiannikov).
As to claim 1, Song teaches a neural processing device (“Additionally, the computing system 1 in FIG. 1 may be a computer system that includes one or more computing devices that each include one or more processors. A processor for the computing system 1 is tangible and non-transitory. The term “non-transitory” specifically disavows fleeting characteristics such as characteristics of a carrier wave or signal or other forms that exist only transitorily in any place at any time. A processor is an article of manufacture and/or a machine component…” figure 1 and associated text, especially para. 0027) comprising a plurality of blocks (“…Additionally, any processor described herein may include multiple processors…” para. 0027. Note: multiple processors are multiple blocks in a processor), the neural processing device comprising:
a first block including a first neural core (“…include multiple processors…” para. 0027…” Note: would comprise first processor or block) that operates at a first operating frequency (“…a clock domain…” para. 0008);
a second block including a second neural core that is connected to the first block (“…include multiple processors…” para. 0027…” Note: would comprise second processor or block) [and operates at the first operating frequency];
a third block including a third neural core that is connected to the second block (“…include multiple processors…” para. 0027…” Note: would comprise third processor or block) [and operates at the first operating frequency]; and
a data communication mode determiner that is connected to the first to third blocks, respectively, and controls data communication among the first to third blocks, and determines a mode of data communication among the first to third blocks,
wherein, when a clock skew occurs in data communication between the second block and the third block (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge 1112 may be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a. Similarly, the bridge 1113 may be electrically connected to the first neural processing unit 100a and the third neural processing unit 100c operating in the clock domain different from the first neural processing unit 100a. The bridge 1114 may be electrically connected to the first neural processing unit 100a and the fourth neural processing unit 100d operating in the clock domain different from the first neural processing unit 100a.’ para. 0107), the data communication mode determiner controls the mode of data communication between the second block and the third block as an asynchronous data communication mode (“As a result, the bridges 1112, 1113 and 1114 are implemented as asynchronous bridges to enable the data transmission between different clock domains.” Para. 0108 and 0112).
Song does not but Ovsiannikov teaches first, second and third processing element or blocks (“…first processing element 120a. Similarly, the element-wise products of the second and third rows of the first multiplicand and the second and third rows of the second multiplicand are formed, one pair of elements at a time, by a second processing element 120b and a third processing element 120c, respectively….” Para. 0061) that operates at a first operating frequency (“…the entire neural processing system, is a synchronous digital circuit with a single clock domain. A stream of first operands is fed, one per clock cycle…” para. 0057. Note: entire system has 1 clock domain and therefore it operates at the first operating frequency/cycle).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Song by applying the teachings of Ovsiannikov because Ovsiannikov teaches the same field of the invention of neural processing system and Ovsiannikov provides a system with same clock domain so all processing element/blocks can be distributed and run in pipeline or synchronously (para. 0061).
As to claim 2, Song modified by Ovsiannikov teaches The neural processing device according to claim 1 block, Song teaches wherein the data communication mode determiner is capable of controlling the first block to operate at an operating frequency different from the first operating frequency, is capable of controlling the second block to operate at an operating frequency different from the first operating frequency, and is capable of controlling the third block to operate at an operating frequency different from the first operating frequency (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge 1112 may be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a. Similarly, the bridge 1113 may be electrically connected to the first neural processing unit 100a and the third neural processing unit 100c operating in the clock domain different from the first neural processing unit 100a. The bridge 1114 may be electrically connected to the first neural processing unit 100a and the fourth neural processing unit 100d operating in the clock domain different from the first neural processing unit 100a.’ para. 0107).
As to claim 3, Song modified by Ovsiannikov teaches The neural processing device according to claim 2, Song teaches wherein the data communication mode determiner controls the first block to operate at a second operating frequency different from the first operating frequency, and controls the mode of data communication between the first block and the second block as the asynchronous data communication mode (“Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other…” para. 0041 - 0042).
As to claim 5, Song modified by Ovsiannikov teaches the neural processing device according to claim 1, Song teaches wherein, when a clock skew occurs in data communication between the first block and the second block, the data communication mode determiner controls the mode of data communication between the first block and the second block as the asynchronous data communication (“Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other…” para. 0041 - 0042).
As to claim 6, Song modified by Ovsiannikov teaches The neural processing device according to claim 1, Song teaches further comprising a command processor that controls the data communication mode determiner (“…the processor 30 executes an application or controls the computing system 1…” para. 0037).
As to claim 7, Song modified by Ovsiannikov teaches The neural processing device according to claim 1, Song teaches wherein, each of the first block and the second block further includes a memory (“…A scratch memory is connected to a plurality of configurable processing elements…” para. 0005).
As to claim 8, Song teaches a neural processor comprising a plurality of neural cores (“…Additionally, any processor described herein may include multiple processors…” para. 0027. Note: multiple processors are multiple blocks/cores in a processor), the neural processor comprising:
a first neural core (“…include multiple processors…” para. 0027…” Note: would comprise first processor/block/core) that operates at a first operating frequency (“…the entire neural processing system, is a synchronous digital circuit with a single clock domain. A stream of first operands is fed, one per clock cycle…” para. 0057. Note: entire system has 1 clock and therefore it operates at the first operating frequency/cycle);
a second neural core that is connected to the first neural core (“…include multiple processors…” para. 0027…” Note: would comprise second processor or block) [and operates at the first operating frequency]
a first memory (element memory 40 of figure 1 and associated text) that is connected to the first neural core and operates at a second operating frequency different from the first operating frequency (“To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains…” para. 0041);
a task manager that configures a data communication path among the first neural core, the second neural core, and the first memory (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains…” para. 0107); and
a data communication mode determiner that is connected to the first neural core, the second neural core, and the first memory, respectively (“…” para. )., and controls data communication among the first neural core, the second neural core, and the first memory, and determines a mode of data communication among the first neural core, the second neural core, and the first memory (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge 1112 may be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a. Similarly, the bridge 1113 may be electrically connected to the first neural processing unit 100a and the third neural processing unit 100c operating in the clock domain different from the first neural processing unit 100a. The bridge 1114 may be electrically connected to the first neural processing unit 100a and the fourth neural processing unit 100d operating in the clock domain different from the first neural processing unit 100a.’ para. 0107);
wherein, when a clock skew occurs in data communication between the first neural core and the second neural core (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge unit 110 may be electrically connected to the first neural processing unit 100a and to the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a…” para. 0041), the data communication mode determiner controls the mode of data communication between the first neural core and the second neural core as an asynchronous data communication mode (“Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other” para. 0042).
Song does not but Ovsiannikov teaches first and second processing element or blocks (“…first processing element 120a. Similarly, the element-wise products of the second and third rows of the first multiplicand and the second and third rows of the second multiplicand are formed, one pair of elements at a time, by a second processing element 120b and a third processing element 120c, respectively….” Para. 0061) that operates at a first operating frequency (“…the entire neural processing system, is a synchronous digital circuit with a single clock domain. A stream of first operands is fed, one per clock cycle…” para. 0057. Note: entire system has 1 clock domain and therefore all it operates at the first operating frequency/cycle)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Song by applying the teachings of Ovsiannikov because Ovsiannikov teaches the same field of the invention of neural processing system and Ovsiannikov provides a system with one clock domain so all processing element/blocks can be distributed and run in pipeline or synchronously (para. 0061).
As to claim 9, Song modified by Ovsiannikov teaches The neural processor according to claim 8, Song teaches wherein, in a maximum computation speed mode, the data communication mode determiner controls each of the first neural core and the second neural core to operate at a third operating frequency greater than the first operating frequency (“…power management unit 50 enhances the practical ability to selectively control power to individual neural processing units among multiple neural processing units in a manner that lowers power consumption, increases power consumption, lowers processing speeds…” para. 0093. Note: can lower speed of a processing unit to a minimum to be third operating frequency).
As to claim 10, Song modified by Ovsiannikov teaches The neural processor according to claim 9, Song teaches wherein, in the maximum computation speed mode frequency (“…power management unit 50 enhances the practical ability to selectively control power to individual neural processing units among multiple neural processing units in a manner that lowers power consumption, increases power consumption, lowers processing speeds…” para. 0093. Note: can lower speed of a processing unit to a minimum to be third operating frequency).
Song and Ovsiannikov does not teach
the data communication mode determiner controls the first memory to operate at the third operating and controls the mode of data communication between the first neural core and the first memory as a synchronous data communication mode (“…entire neural processing system, is a synchronous digital circuit with a single clock domain …” para. 0057).
See motivation for claim 8 above.
As to claim 12, Song modified by Ovsiannikov teaches The neural processor according to claim 8, Song teaches wherein, in a minimum power use mode, the data communication mode determiner controls each of the first neural core and the second neural core to operate at a fourth operating frequency smaller than the first operating frequency (“…power management unit 50 enhances the practical ability to selectively control power to individual neural processing units among multiple neural processing units in a manner that lowers power consumption, increases power consumption, lowers processing speeds…” para. 0093. Note: can lower speed of a processing unit to a minimum to be fourth operating frequency).
As to claim 13, Song modified by Ovsiannikov teaches The neural processor according to claim 12, Song teaches wherein, in the minimum power use mode, the data communication mode determiner controls the first memory to operate at the fourth operating frequency (“…power management unit 50 enhances the practical ability to selectively control power to individual neural processing units among multiple neural processing units in a manner that lowers power consumption, increases power consumption, lowers processing speeds…” para. 0093. Note: can lower speed of a processing unit to a minimum to be fourth operating frequency).
Song does not but Ovsiannikov teaches controls the mode of data communication between the first neural core and the first memory as a synchronous data communication mode (“Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other.” Para. 0042. Note: asynchronous execution can be any different neural processing units including fourth one with different clock cycle).
See motivation for claim 8 above.
As to claim 18, Ovsiannikov teaches A method for determining a data communication mode, the method being performed in a neural processing device (“…Additionally, any processor described herein may include multiple processors…” para. 0027. Note: multiple processors are multiple blocks/cores in a processor) including a first block including a first neural core, a second block including a second neural core, and a third block including a third neural core (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge 1112 may be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a. Similarly, the bridge 1113 may be electrically connected to the first neural processing unit 100a and the third neural processing unit 100c operating in the clock domain different from the first neural processing unit 100a. The bridge 1114 may be electrically connected to the first neural processing unit 100a and the fourth neural processing unit 100d operating in the clock domain different from the first neural processing unit 100a.’ para. 0107), which perform data communication and comprising:
controlling the first block (“…include multiple processors…” para. 0027…” Note: would comprise first processor or block) to operate at a first operating frequency that operates at a first operating frequency (“…the entire neural processing system, is a synchronous digital circuit with a single clock domain. A stream of first operands is fed, one per clock cycle…” para. 0057. Note: entire system has 1 clock and therefore it operates at the first operating frequency/cycle);
Controlling the second block connected to the first block (“…include multiple processors…” para. 0027…” Note: would comprise second processor or block) [to operate at the first operating frequency];
controlling the third block connected to the second block (“…include multiple processors…” para. 0027…” Note: would comprise third processor or block) to operate at a second operating frequency different from the first operating frequency (“To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge unit 110 may be electrically connected to the first neural processing unit 100a and to the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a.” para. 0041); and
controlling a mode of data communication between the first block and the second block as an asynchronous data communication mode when a clock skew occurs in data communication between the first block and the second block (Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other.” para. 0042).
Song does not but Ovsiannikov teaches first and second processing element or blocks (“…first processing element 120a. Similarly, the element-wise products of the second and third rows of the first multiplicand and the second and third rows of the second multiplicand are formed….” Para. 0061) that operates at a first operating frequency (“…the entire neural processing system, is a synchronous digital circuit with a single clock domain. A stream of first operands is fed, one per clock cycle…” para. 0057. Note: entire system has 1 clock domain and therefore it operates at the first operating frequency/cycle).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Song by applying the teachings of Ovsiannikov because Ovsiannikov teaches the same field of the invention of neural processing system and Ovsiannikov provides a system with same clock domain so all processing element/blocks can be distributed and run parallel or synchronously (para. 0061).
As to claim 19, Song modified by Ovsiannikov teaches The method according to claim 18, Song teaches further comprising:
controlling the first block to operate at the second operating frequency different from the first operating frequency (“To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge unit 110 may be electrically connected to the first neural processing unit 100a and to the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a.” para. 0041); and
controlling a mode of data communication between the first block and the third block to a synchronous data communication mode (Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other.” para. 0042).
Allowable Subject Matter
Claims 4, 11, 14 – 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 4, Song modified by and Ovsiannikov teaches The neural processing device according to claim 3, Song teaches wherein the data communication mode determiner further controls the second block to operate at the second operating frequency (“…To this end, the first neural processing unit 100a and the second neural processing unit 100b may operate in mutually different clock domains. In this circumstance, the bridge unit 110 may be electrically connected to the first neural processing unit 100a and to the second neural processing unit 100b operating in the clock domain different from the first neural processing unit 100a….” para. 0041),
when a clock skew occurs in data communication between the first block and the second block, the data communication mode determiner further changes the mode of data communication between the first block and the second block to the asynchronous data communication mode (“Thus, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to allow data to transmit between the clock domains different from each other.” Para. 0042).
Song and Ovsiannikov do not teach the limitation of
changes the mode of data communication between the first block and the second block to a synchronous data communication mode, wherein, after the mode of data communication between the first block and the second block is changed to the synchronous data communication mode, when a clock skew occurs in data communication between the first block and the second block, the data communication mode determiner further changes the mode of data communication between the first block and the second block to the asynchronous data communication mode”, when taken in a context as a whole.
As to claim 11, The neural processor according to claim 10, Song and Ovsiannikov do not teach the limitation of wherein, when a clock skew occurs in data communication between the first neural core operating at the third operating frequency and the first memory operating at the third operating frequency, the data communication mode determiner changes the mode of data communication between the first neural core and the first memory to the asynchronous data communication mode, when taken in a context as a whole.
As to claim 14, Song modified by and Ovsiannikov teaches The neural processor according to claim 13, Song and Ovsiannikov do not teach the limitation of wherein, when a clock skew occurs in data communication between the first neural core operating at the fourth operating frequency and the first memory operating at the fourth operating frequency, the data communication mode determiner changes the mode of data communication between the first neural core and the first memory to the asynchronous data communication mode, when taken in a context as a whole.
As to claim 15, Song and Ovsiannikov do not teach The neural processor according to claim 8, further comprising:
a first data line connecting the first neural core and the second neural core in series and transmitting data in a first direction; a second data line connecting the first neural core and the second neural core in series and transmitting data in a second direction opposite to the first direction; and
a second memory that is connected to the second neural core and operates at the first operating frequency, wherein the task manager controls the first data line and the second data line so as to configure a data path among the first neural core, the second neural core, the first memory, and the second memory, and the data communication mode determiner determines the mode of data communication between the second neural core and the second memory to be a synchronous data communication mode, in a context as a whole.
As to claims 16, it is objected as to claim 15 it depends on.
As to claims 17, it is objected as to claim 16 it depends on.
As to claim 20, Song and Ovsiannikov teaches after the mode of data communication between the first block and the third block is controlled as the synchronous data communication mode, when a clock skew occurs in data communication between the first block and the third block, changing the mode of data communication between the first block and the third block to the asynchronous data communication mode, when taken in a context as a whole.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Kaibel, (US PUB 2008/0005635), discloses an integrated circuit having multiple processors and clock switch to run between synchronous and asynchronous processors (title, abstract and figures 1 – 5).
Parashar, (US PUB 2021/0232921), discloses method for managing heterogenous processors to execute in synchronous or asynchronous mode in a neural network (title, abstract and figures 1 – 19).
Kuo, (US PUB 2022/0036158), discloses a task skew management for neural processor circuit, wherein tasks are executed in asynchronous manner (title, abstract and figures 1 – 15).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached at 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
