CTNF 18/739,614 CTNF 80146 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7, 9-10 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regrading claim 7, Mimis, and fail to disclose teach or suggest the limitations that read, “wherein the supply voltage error compensation circuitry further comprises: a supply voltage detector configured to sense the power supply voltage received at the radio-frequency amplifier, wherein the supply voltage error compensation circuitry is configured to generate the error signal based on a difference between the sensed power supply voltage and the target supply voltage waveform”, in combination with all the limitations of the claims from which claim 7 depends and within the context of the claims. Regrading claim 9, Mimis, and fail to disclose teach or suggest the limitations that read, “wherein the supply voltage error compensation circuitry further comprises: a scaling and filtering block configured to receive the digital code and to generate a reference power supply signal by scaling and filtering the received digital code”, in combination with all the limitations of the claims from which claim 9 depends and within the context of the claims. Note : Claim 8 is required in conjunction with claim 9, since based on Fig. 9, both the outputs of the “scaling & filtering” and the “supply voltage estimator” are required to generate the error signal. Claim 10 depends from claim 9 and inherit all the limitations of the claim; therefore, it is objected to its dependency from claim 9. Note : Claim 10 is required in combination with at least claims 1, and 8-9, since claim 10 generates the error signal. Regrading claim 14, Mimis, and fail to disclose teach or suggest the limitations that read, “sensing the power supply voltage, wherein generating the error signal comprises generating the error signal by computing a difference between the sensed power supply voltage and the target power supply signal”, in combination with all the limitations of the claims from which claim 14 depends and within the context of the claims. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 8, 11-12 and 17-19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by US 20180123521 A1 (Mimis et al., hereinafter Mimis) . Regarding claim 1, Mimis discloses wireless circuitry (Fig. 11) comprising: a radio-frequency amplifier (Fig. 11, “radiofrequency power amplifier (RFPA) 120”) configured to receive a radio-frequency signal (Fig. 11 and par. [0034], “radiofrequency (RF) signal 118 “) generated from a baseband signal (Fig. 11, “baseband processing module 1100”) and to receive a power supply voltage (Fig. 11, “supply voltage 324”); a load modulation circuit (Fig. 11 and par. [0048], “The amplifier circuit 1100 uses a combination of supply modulation and dynamic load modulation…”) configured to generate a load control signal (Fig. 11, “load control signal 754”) from the baseband signal (Fig. 11, “baseband processing module 1100”; par. [0049], “The baseband processing module 1110 is coupled to an amplifier 750, which acts as a load controller, and a supply modulator 340”); and supply voltage error compensation circuitry (Fig. 11, circuitry in “baseband processing module 1110” or “baseband [1100]”) configured to generate an error signal that is applied to the load control signal to produce a compensated load control signal, wherein an adjustable load component of the radio-frequency amplifier is tuned by the compensated load control signal (Fig. 14, “which shows that each time the supply voltage changes, the load modulation is adapted or in other words an error signal is generated to change the load modulation OR the error signal determined by calibration”; par. [0053]. “The amplifier circuit shown in FIG. 11 operates with supply and load modulation at each output power level as indicated in FIG. 12. These combinations can be determined using calibration and characterization procedures”, which will determine an error and compensate by the addition or subtracting of an error signal to compensate for said error”). Regarding claim 11, Mimis discloses a method of operating wireless circuitry (Fig. 11 and par. [0076]) comprising: with a radio-frequency amplifier (Fig. 11, “radiofrequency power amplifier (RFPA) 120”), receiving a radio-frequency signal generated from a baseband signal (Fig. 11, “baseband processing module 1100” and par. [0034], “radiofrequency (RF) signal 118”) and receiving a power supply voltage (Fig. 11, “supply voltage 324”); with a load modulation circuit (Fig. 11 and par. [0048], “The amplifier circuit 1100 uses a combination of supply modulation and dynamic load modulation…”), generating a load control signal (Fig. 11, “load control signal 754”) from the baseband signal (Fig. 11, “baseband processing module 1100”; par. [0049], “The baseband processing module 1110 is coupled to an amplifier 750, which acts as a load controller, and a supply modulator 340”); with supply voltage error compensation circuitry (Fig. 11, circuitry in “baseband processing module 1110” or “baseband [1100]”), generating an error signal and combining the error signal with the load control signal to produce a compensated load control signal (Fig. 14, “which shows that each time the supply voltage changes, the load modulation is adapted or in other words an error signal is generated to change the load modulation OR the error signal determined by calibration”; par. [0053]. “The amplifier circuit shown in FIG. 11 operates with supply and load modulation at each output power level as indicated in FIG. 12. These combinations can be determined using calibration and characterization procedures”, which will determine an error and compensate by the addition or subtracting of an error signal to compensate for said error”); and tuning an adjustable load component of the radio-frequency amplifier with the compensated load control signal (Fig. 7 and par. [0047]). Regarding claim 17, Mimis discloses circuitry (Fig. 11) comprising: an amplifier (Fig. 11, “radiofrequency power amplifier (RFPA) 120”) having a data input (“RF in”), a first control input , and a second control input; a first control signal generator configured to output a first control signal to the first control input of the amplifier (Fig. 11, “baseband processing module 1100” and par. [0034], “radiofrequency (RF) signal 118”); a second control signal generator configured to output a second control signal (Fig. 11, “load control signal 754” generated by “load controller 750”); and error compensation circuitry (Fig. 11, circuitry in “baseband processing module 1110” or “baseband [1100]”) configured to sense or estimate the first control signal received at the first control input of the amplifier (“radiofrequency (RF) signal 118”), and generate an error signal for compensating the second control signal (Fig. 11, “load control signal 754), wherein the compensated second control signal is provided to the second control input of the amplifier (Fig. 14, “which shows that each time the supply voltage changes, the load modulation is adapted or in other words an error signal is generated to change the load modulation OR the error signal determined by calibration”; par. [0053]. “The amplifier circuit shown in FIG. 11 operates with supply and load modulation at each output power level as indicated in FIG. 12. These combinations can be determined using calibration and characterization procedures”, which will determine an error and compensate by the addition or subtracting of an error signal to compensate for said error”). Regarding claims 2, 12 and 18, Mimis discloses all the limitations of claims 1, 11 and 17, respectively. Mimis further discloses an adaptive power tracking control circuit configured to generate a digital code based on a target output power level; and a power management circuit configured to generate the power supply voltage for the radio-frequency amplifier based on the digital code (Fig. 11, “load controller 750”, where according to applicant’s invention both components are “a control signal generator”, par. [0042]). Regarding claim 8, Mimis discloses all the limitations of claims 2. Mimis further discloses wherein the supply voltage error compensation circuitry comprises: a supply voltage estimation block configured to receive the digital code and to generate an estimated power supply signal based on a digital model associated with the power management circuit (Fig. 11, “load controller 750” provides the function of a “power management system”. Where according to applicant’s invention both components are “a control signal generator”, par. [0042]). Regarding claim 19, Mimis discloses all the limitations of claims 18. Mimis further discloses wherein the amplifier further comprises an adjustable load that is tuned by the compensated second control signal (Fig. 11, “load control 754”) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Mimis in view of US 20190348956 A1 (Megretski et al., hereinafter Megretski) . Regarding claim 3, Mimis discloses all the limitations of claims 2. Although implied, given that Mimis’ invention deals with digital signals, Mimis does not specifically disclose wherein the digital code generated by the adaptive power tracking control circuit is piecewise constant. In related art concerning digital compensator for a non-linear system, Megretski discloses wherein the digital code generated by the adaptive power tracking control circuit is piecewise constant (par. [0084]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Megretski’s teachings wherein the digital code is piecewise constant with the amplifier disclosed by Mimis because one of ordinary skill in the art would have recognized that by doing so, the amplifier’s gain and drive level or drive signals are held constant over fixed periods of time, this discretization makes it easier for the amplifier to respond dynamically to changing load conditions . 07-21-aia AIA Claim s 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Mimis in view of US 20150288282 A1 (Robert H. Isham, hereinafter Isham) . Regarding claim 4, Mimis discloses all the limitations of claims 2. Mimis does not specifically disclose wherein the supply voltage error compensation circuitry comprises: a reference signal generator configured to receive the digital code and to generate a reference supply voltage waveform. In related art concerning digital voltage compensation for power supply integrated circuits, Isham discloses wherein the supply voltage error compensation circuitry comprises: a reference signal generator configured to receive the digital code and to generate a reference supply voltage waveform (Fig. 1, 104 and 106; pars. [0013]-[0014]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Isham’s teachings wherein the supply voltage error compensation circuitry comprises: a reference signal generator configured to receive the digital code and to generate a reference supply voltage waveform with the amplifier disclosed by Mimis because one of ordinary skill in the art would have recognized that by feeding a digital-to-analog converted reference voltage signal into the error compensation circuit, the signals can be customized to variable refence levels for specific load conditions that the PA can handle, among others. Regarding claim 5, Mimis and Isham disclose all the limitations of claims 4. Isham discloses wherein the reference signal generator comprises a supply reference digital-to-analog converter (DAC) configured to generate an analog reference supply voltage waveform (Fig. 1, 104 and 106; pars. [0013]-[0014])). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Isham’s teachings wherein the reference signal generator comprises a supply reference digital-to-analog converter (DAC) configured to generate an analog reference supply voltage waveform with the amplifier disclosed by Mimis because one of ordinary skill in the art would have recognized that by feeding a digital-to-analog converted reference voltage signal into the error compensation circuit, the signals can be customized to variable refence levels for specific load conditions that the PA can handle, among others . 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mimis in view of Isham, and further in view of US 20220149864 A1 (Prakash et al., hereinafter Prakash) . Regarding claim 6, Mimis and Isham disclose all the limitations of claims 4. Mimis and Isham do not specifically disclose wherein the supply voltage error compensation circuitry (Fig. 10, 15D) further comprises: a low-pass filter configured to receive the reference supply voltage waveform and to generate a corresponding target supply voltage waveform. In related art concerning gain error reduction in switched capacitor delta-sigma data converters, Prakash discloses wherein the supply voltage error compensation circuitry further comprises: a low-pass filter (92) configured to receive the reference supply voltage waveform (ratio of Vref_fp and Vref_rp voltage coming from ADC 92) and to generate a corresponding target supply voltage waveform (Fig. where the filtered signal is provided to multiplier 96). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Prakash’s teachings about a low-pass filter with the amplifier disclosed by Mimis because one of ordinary skill in the art would have recognized that the low-pass filter would remove unwanted variations in order to maintain a stable output voltage . 07-21-aia AIA Claim 13, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mimis in view of Prakash . Regarding claim 13, Mimis discloses all the limitations of claims 12. Prakash discloses generating a reference power supply signal based on the digital code (Fig. 10, ratio of Vref_fp and Vref_rp voltage); and generating a target power supply signal by filtering the reference power supply signal (signal filtered by low-noise filter 92). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Prakash’s teachings about generating a reference power supply signal based on the digital code and generating a target power supply signal by filtering the reference power supply signal with the amplifier disclosed by Mimis because one of ordinary skill in the art would have recognized that the low-pass filter would remove unwanted variations in order to maintain a stable output voltage. Regarding claim 15, Mimis and Prakash disclose all the limitations of claims 13. Prakash further discloses estimating the power supply voltage based on a digital model of the power management circuit, wherein generating the error signal comprises generating the error signal by computing a difference between the estimated power supply voltage and the target power supply signal (par. [0039], “determine an error between a voltage across the reference filter capacitor and the reference voltage” which reads on a difference between the voltages). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Prakash’s teachings about estimating the power supply voltage based on a digital model of the power management circuit, wherein generating the error signal comprises generating the error signal by computing a difference between the estimated power supply voltage and the target power supply with the amplifier disclosed by Mimis because one of ordinary skill in the art would have recognized that a difference between the estimated power supply voltage and the target power corresponds to the error. Regarding claim 20, Mimis discloses all the limitations of claims 18. wherein the error compensation circuitry comprises: a reference signal generator configured to generate a reference signal based on the digital code (Fig. 10, ratio of Vref_fp and Vref_rp voltage); and a filter configured to generate a target signal based on the reference signal (signal filtered by low-noise filter 92), wherein the error signal is computed based on a difference between the target signal and the sensed or estimated version of the first control signal (par. [0039], “determine an error between a voltage across the reference filter capacitor and the reference voltage” which reads on a difference between the voltages). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Prakash’s teachings about generating a reference power supply signal based on the digital code and generating a target power supply signal by filtering the reference power supply signal with the amplifier and calculating an error disclosed by Mimis because one of ordinary skill in the art would have recognized that the low-pass filter would remove unwanted variations in order to maintain a stable output voltage; and that a difference between the estimated power supply voltage and the target power corresponds to the error . 07-21-aia AIA Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Mimis in view of US 20230361731 A1 (Huang et al., hereinafter Huang) . Regarding claim 16, Mimis discloses all the limitations of claims 12. Mimis does not specifically disclose where with the power management circuit, driving the power supply voltage to a first fixed voltage level while transmitting a first symbol in the baseband signal; and with the power management circuit, driving the power supply voltage to a second fixed voltage level different than the first fixed voltage level while transmitting a second symbol in the baseband signal. In related art concerning power amplifier modulator, Huang discloses where with the power management circuit, driving the power supply voltage to a first fixed voltage level while transmitting a first symbol in the baseband signal; and with the power management circuit, driving the power supply voltage to a second fixed voltage level different than the first fixed voltage level while transmitting a second symbol in the baseband signal (par. [0015]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Huang’s teachings where with the power management circuit, driving the power supply voltage to a first fixed voltage level while transmitting a first symbol in the baseband signal; and with the power management circuit, driving the power supply voltage to a second fixed voltage level different than the first fixed voltage level while transmitting a second symbol in the baseband signal with the amplifier and calculating an error disclosed by Mimis because one of ordinary skill in the art would have recognized that 5G and LTE networks, OFDM technique is used to transmit information/data to different users using different symbols. Where different data/information requires different power based on particular services or data types . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230058434 A1 relates to class-D amplifier with deadtime distortion compensation. US 20230238886 A1 relates to constant on time converter control circuit and constant on time converter. US 20100001699 A1 relates to output voltage control circuit for modular power supplies. US 6526006 B1 relates to tracking error signal compensation circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Angelica Perez whose telephone number is 571-272-7885. The examiner can normally be reached on Monday-Friday from 8:00 a.m. to 4:00 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yuwen (Kevin) Pan can be reached at (571) 272-7855. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300 for regular communications and for After Final communications. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either the PAIR or Public PAIR. Status information for unpublished applications is available through the Private PAIR only. For more information about the pair system, see http://pair- direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll- free). Information regarding Patent Application Information Retrieval (PAIR) system can be found at 866-217-9197 (toll-free). Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the TC 2600's customer service number is 703-306-0377. /Angelica M. Perez/ Primary Patent Examiner AU 2649 Application/Control Number: 18/739,614 Page 2 Art Unit: 2649 Application/Control Number: 18/739,614 Page 3 Art Unit: 2649 Application/Control Number: 18/739,614 Page 4 Art Unit: 2649 Application/Control Number: 18/739,614 Page 5 Art Unit: 2649 Application/Control Number: 18/739,614 Page 6 Art Unit: 2649 Application/Control Number: 18/739,614 Page 7 Art Unit: 2649 Application/Control Number: 18/739,614 Page 8 Art Unit: 2649 Application/Control Number: 18/739,614 Page 9 Art Unit: 2649 Application/Control Number: 18/739,614 Page 10 Art Unit: 2649 Application/Control Number: 18/739,614 Page 11 Art Unit: 2649 Application/Control Number: 18/739,614 Page 12 Art Unit: 2649 Application/Control Number: 18/739,614 Page 13 Art Unit: 2649 Application/Control Number: 18/739,614 Page 14 Art Unit: 2649 Application/Control Number: 18/739,614 Page 15 Art Unit: 2649 Application/Control Number: 18/739,614 Page 16 Art Unit: 2649 Application/Control Number: 18/739,614 Page 17 Art Unit: 2649 Application/Control Number: 18/739,614 Page 18 Art Unit: 2649
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