Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 06/11/2024. Claims 1-15 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bunsen et al. Pub. No. 2023/0275593.
Fig. 1 of Bunsen et al. discloses SAR AD converter (paragraph 0038) with processing circuit 27 for error detection circuit for each bit of plurality comparators 48…40 and 61, 60P, 60N (paragraph 0061-0062); Coarse DAC circuits 32 and 31, Fine DAC circuit 51, coarse comparators circuit 33 and fine comparator circuit 52.
Fig. 2 of Bunsen et al. disclose detailed of processing circuit 27 in Fig. 1, the processing circuit 27 includes: error correction circuit 71, error bit detection circuit 72, error factor estimation circuit 72 and calibration signal Generation circuit 74 to generate off_cal, th_cal , DAC1_cal, DAC2_cal, and finephase_cal, based on most- significant-bits B1 [8:0], and least-significant-bits B2[1:0] from comparators 48…40, 61, 60P, 60N
Regarding claim 1 Fig. 1 of Bunsen et al. disclose SAR AD converter (1, paragraph 0038) with comparator error detection (27; paragraph 0061-0062) , comprising: a digital-to-analog converter (DACs 32, 31, 51), a plurality of comparators (48…40 and 61, 60P, 60N), and a successive-approximation register logic (paragraph 0038), configured to form a loop (loop of 30 and 50) for successive approximation (loop of comparators 48-40, 61 and 60) of a digital representation (Dout) of an analog input (Vin); and a comparator error detector (27; paragraphs 0176-00184 discloses comparison of error detector 72 between most signal bits B1 and least significant bits B2 to generate error flags ), coupled to the loop (loop of 30 and 50); wherein: digital control bits (B1[8:3], B1[8:2], B1[8:0]) controlling the digital-to-analog converter(32, 31, 51) include most significant bits (B1[8]….B1[0]) and least significant bits (B2[1], B2[0]), and the digital-to-analog converter (32, 31, 51) is configured to provide redundancy (paragraph 0167) approximation (1, paragraph 0038) at the lowest bit (B1[0]) of the most significant bits (B1[8:3], B1[8:2], B1[8:0]); the comparators (48…40 and 61, 60P, 60N ) include a plurality of most-significant-bit comparators (48…40) corresponding to the most significant bits (B1[8]….B1[0]); and the comparator error detector (27; see Fig. 2 for discloses error bit detection circuit 72 ) detects occurrence of a comparator error (paragraphs 0065-0068 ) based on the least significant bits (B2[1], B2[0]), and identifies a target comparator (paragraph 0055) causing the comparator error (error of comparators 48…40 and 61, 60P, 60N) based on the most significant bits (B1[8]….B1[0]).
Regarding claim 2. The successive-approximation register analog-to-digital converter as claimed in claim 1, Fig. 1 further discloses wherein: the most-significant-bit comparators (Coarse comparators 48…40) correspond to the most significant bits in a one-to-one relationship (B1[8]…B1[0]), and generate the most significant bits one by one (comparator 48…40 one by one generate B1[8]…B1[0]).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 3-4, 6, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bunsen et al. applied to claim 1 above in view of Oh et al. Pub. No. 2016/0126967.
Regarding claim 3. Fig. 1 and Fig. 2 of Bunsen et al. applied to claim 1 above further discloses wherein: the comparator error detector (27) to receive the least significant bits (B2[1:0]) , and transforms the least significant bits (B2[1:0]) into a least-significant-bit code (DTE) that corresponds to a normal range (paragraph 0065-0066 discloses DTE with error flag “0” is no error ); and when determining that the least-significant-bit code (DTE) is beyond the normal range (paragraph 0065-0066 discloses DTE with error flag “1” or “-1” for threshold error), the comparator error detector (27) confirms the occurrence of the comparator error (paragraph 0065-0066 discloses DTE with error flag “1” or “-1” for threshold error confirmation by error factor estimation circuit 73).
However, Bunsen et al. do not disclose the comparator error detector (27) is coupled to the successive-approximation register logic to receive the least significant bits.
Fig. 1 of Oh et al. disclose a SAR ADC (153; paragraph 0014) comprising: comparator 140, a SAR logic 153 couple to comparator 140; and error correction unit 151 couple to SAR logic 153.
Fig. 5 of Ho et al. discloses a detailed of error correction unit 151 comprising comparator error detection 530 that receive least significant bits 510 from the SAR 153 (paragraph 0069).
Bunsen et al. and Ho et al. are common subject matter of error detection for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Ho et al. into Bunsen et al. for the purpose of providing detection error of bits from SAR Logic to eliminate errors that arise when a value of capacitor is not accurate (paragraph 0012 of Ho et al.).
Regarding claim 4. Bunsen et al. and Ho et al. applied to claim 3, Fig. 3 of Bunsen et al. further discloses wherein: when determining (that the least-significant-bit code (DTE) is greater than an upper boundary of the normal range (paragraph 0065-0066 discloses DTE with error flag “1” or “-1” for threshold error), the comparator error detector (27) determines that the target comparator (48…40 and 61, 60P, 60N) introduces a negative offset (paragraph 0069 discloses positive offset caloffsetp and negative offset caloffsetn for comparator 60N and 60P).
Regarding claim 6. Bunsen et al. and Ho et al. applied to claim 3, Fig. 3 of Bunsen et al. further discloses wherein: wherein: when determining (72) that the least-significant-bit code is smaller than a lower boundary of the normal range (paragraph 0065-0066 discloses DTE with error flag “1” or “-1” for threshold error higher or lower boundary of desire voltage), the comparator error detector (72) determines that the target comparator (target of each comparator of comparators 48…40 and 61, 60P, 60N) ) introduces a positive offset (paragraph 0069 discloses positive offset caloffsetp and negative offset caloffsetn for comparator 60N and 60P).
Regarding claim 12. Bunsen et al. and Ho et al. applied to claim 3, Fig. 1-3 of Bunsen et al. further discloses wherein: the comparator error detector (27) determines an offset value (off_cal, th_cal) of the target comparator (48…40 and 61, 60P, 60N) based on a difference between the least-significant-bit code (B2{1:0]) and an upper boundary or a lower boundary of the normal range (paragraph 0046 disclose upper threshold voltage +Vref/2 or lower threshold voltage -Vref/2 for comparators).
7. Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Bunsen et al. and Oh et al. applied to claim 3 above, in further view of Scanlan Pub. No. 2012/0001781.
Bunsen et al. and Oh et al. applied to claim 3 above, Fig. 1 of Bunsen et al. further discloses wherein: the digital-to-analog converter is a capacitor digital-to-analog converter (5); M is a number (number of capacitors of 51); and in the capacitor digital-to-analog converter (51), an Mth capacitor (0.5cu) corresponding to the lowest bit (B1[0]) of the most significant bits (B1[8:0] and an (M-1) th capacitor (Variable capacitor of 51) corresponding to the highest bit (B2[1]) of the least significant bits (B2[1:0]).
However, Bunsen et al. and Oh et al. do not disclose the Mth capacitor (0.5 Cu) is the same size as an (M-1)th capacitor (Variable capacitor of 51) as claimed.
Fig. 13 of Scanlan discloses SAR ADC (paragraph 0044) comprising : digital-to-analog converter (switching capacitors; paragraph 0012) is a capacitor digital-to-analog converter (switching capacitors; paragraph 0012); M is a number (five capacitors ); and in the capacitor digital-to-analog converter ((switching capacitors; paragraph 0012), an Mth capacitor (fourth capacitor C) corresponding to the lowest bit (b4) of the most significant bits (b1) is the same size (C) as an (M-1)th capacitor (fifth capacitor C) corresponding to a highest bit (b3) of the least significant bits (b3, b4)
Bunsen et al. and Scanlan are common subject matter of switch- capacitors DAC for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Scanlan into Bunsen et al. for the purpose to compensate for gain error, addition of high-speed logic and large power overhead (paragraph 0010-0011 of Scanlan).
Regarding claim 9. Bunsen et al., Oh et al. and Scanlan applied to claim 8 above, Fig. 1 of Scanlan further discloses wherein: in the capacitor digital-to-analog converter (digital switching capacitors; paragraph 0012): a first capacitor (first C) corresponding to the lowest bit (b4) of the least significant bits (b3, b4) is the same size (same C) as a number capacitor (fifth Capacitor C) that has a fixed connection (fixed to Ground) ; from the first capacitor (fourth capacitor C) to the (M-1)th capacitor (third capacitor 2C) corresponding to the lowest bit (b4) of the least significant bits (b2, b3) to the highest bit (b3) of the least significant bits (b3, b4) , the capacitor size increases by a factor of two (C, 2C, 4C, 8C).
Regarding claim 10. Bunsen et al., Oh et al. and Scanlan applied to claim 9 above, Fig. 1 of Scanlan further discloses wherein: wherein: N is a number (number capacitors of 8C and 4C); and in the capacitor digital-to-analog converter (switching capacitors; paragraph 0012), from the Mth capacitor (first C) to the Nth capacitor (capacitors of 4C and 8C) corresponding to the lowest bit (b2) of the most significant bits (b1, b2) to the highest bit (b1) of the most significant bits (b1, b2), the capacitor size increases by a factor of two (C, 2C, 4C, 8C).
8. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Bunsen et al. and Oh et al. applied to claim 12 above, in further view of Matsui et al. U.S. patent No. 9,559,716.
Bunsen et al. and Oh et al. applied to claim 12 above do not disclose a compensation logic, coupled to the comparator error detector and the successive-approximation register logic, and configured to adjust the digital representation received from the successive-approximation register logic to compensate for the offset value of the target comparator that is obtained by the comparator error detector.
Fig. 3 of Matsui discloses SAR ADC comprising: a comparator 130, SAR Logic 140, and a digital correction controller (8, 9); Fig. 8 of Matsui discloses detailed of digital correction controller (8) in Fig. 3 comprising: comparator error detection (subtractor 82) coupling ADPRE to SAR logic 140 in Fig. 3; and a digital error correction 81 coupling to ADPRE to SAR logic 140 in Fig. 3, the digital error correction 81 configured to adjust (adjusted by ADERR) the digital representation (ADPRE) received from the successive-approximation register logic (140 in Fig. 3).
From above, described by Fig. 3 and Fig. 8 above, Matsui et al. discloses compensation logic (81) coupled to the comparator error detector (Subtractor 82 performing comparing function) and the successive-approximation register logic (140 in Fig. 3) , and configured to adjust (adjusted by ADERR) the digital representation (ADPRE) received from the successive-approximation register logic (140 in Fig. 3) to compensate for the offset value (error value ƐN…Ɛ0); of the target comparator (130 in Fig. 3) that is obtained by the comparator error detector (Subtractor 82).
Bunsen et al./Oh et al. and Matsui et al. are common subject matter of digital correction for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Matsui et al. into Bunsen et al./OH et al. for the purpose of improve a processing speed while achieving a high accuracy of AD conversion (Col. 2 lines 34-35 of Matsui et al.).
9. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bunsen et al. and Oh et al. applied to claim 3 above in further view of Lin et al. Pub. No. 2013/0285844.
Regarding claim 14. Bunsen et al. and Oh et al. applied to claim 3 above, Fig. 1 of Bunsen et al. further disclose plurality most-significant-bit comparators (comparators 48…40 and 61, 60P, 60N) but do not disclose each of the comparator is reset just one time in one approximation cycle.
Fig.1 of Walsh et al. discloses SAR ADC (paragraph 0016) comprising a comparator (110), the comparator (110) comparator is reset just one time in one approximation cycle (paragraph 0043 discloses “each bit cycle includes a comparator reset time and a comparator decision time”).
Bunsen et al./Oh et al. and Walsh et al. are common subject matter of comparator for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Walsh et al. into Bunsen et al./OH et al. for the purpose providing a reset control circuit configured to reset circuits in the comparator module to avoid a pulse output from the non-selected output signal at the same time with the selected output signal (paragraphs 0005-0006 of Walsh et al.).
Regarding claim 15. Regarding claim 14. Bunsen et al. and Oh et al. applied to claim 3 above, Fig. 1 of Bunsen et al. further disclose wherein: the comparators (60P or 60N) provide one single least-significant-bit comparator (60P, 60N) to correspond to all of the least significant bits (B2[1:0]); but de not discloses the least-significant-bit comparator (60P, 60N) is repeatedly reset in one approximation cycle.
Fig.1 of Walsh et al. discloses SAR ADC (paragraph 0016) comprising a comparator (110), the comparator (110) comparator is reset just one time in one approximation cycle (paragraph 0043 discloses “each bit cycle includes a comparator reset time and a comparator decision time”).
Bunsen et al./Oh et al. and Walsh et al. are common subject matter of comparator for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Walsh et al. into Bunsen et al./OH et al. for the purpose providing a reset control circuit configured to reset circuits in the comparator module to avoid a pulse output from the non-selected output signal at the same time with the selected output signal (paragraphs 0005-0006 of Walsh et al.).
Allowable Subject Matter
10. Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein: the lowest bit of the most significant bits is the Mth bit of the digital control bits, where M is a number; and K is a number greater than M; when determining that the Kth bit of the digital control bits is 0 and the (K-1)th bit to the Mth bit of the digital control bits are all 1s, the comparator error detector determines that a Kth most-significant-bit comparator corresponding to the Kth bit of the digital control bits is the target comparator with the negative offset; and it is further determined whether the (M+1)th bit and the Mth bit of the digital control bits is “10” when an overshoot LSB code occurs, and, if yes, the comparator error detector determines that the Mth most-significant-bit comparator corresponding to the Mth bit of the digital control bits is the target comparator with the negative offset.
11. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein: the lowest bit of the most significant bits is the Mth bit of the digital control bits, where M is a number; and K is a number greater than M; when determining that the Kth bit of the digital control bits is 1 and the (K-1)th bit to the Mth bit of the digital control bits are all 0s, the comparator error detector determines that a Kth most-significant-bit comparator corresponding to the Kth bit of the digital control bits is the target comparator with the positive offset; and it is further determined whether the (M+1)th bit and the Mth bit of the digital control bits is “01” when a undershoot LSB code occurs, and, if yes, the comparator error detector determines that the Mth most-significant-bit comparator corresponding to the Mth bit of the digital control bits is the target comparator with the positive offset.
12. Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: a lower boundary of the normal range is 2(M-2); and an upper boundary of the normal range is 2(M-1) + 2(M-2)-1.
Contact Information
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
12/04/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845