DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 10-12 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jacob et al. (US 2015/0123166 A1; hereinafter “Jacob”)
In regard to claim 1, Jacob teaches a method for fabricating a FinFET device (an N-type FinFET device 100) (Fig. 3A, and paragraph 34), comprising:
providing a substrate (a substrate 102) (Fig. 3B and paragraph 34);
forming a drain layer (substrate contact 107) on a fist side of the substrate (substrate contact 107 terminates at the final backside of the substrate 102) (Fig. 4 and paragraph 43);
forming a drift layer (doped region 103A) on a second side of the substrate (the doped region 103A is shown on the top side of the substrate 102 in Fig. 3E) (Fig. 3E and paragraph 38), the drift layer having a fin-shaped portion (a plurality of substrate fins 106) and a recessed portion (a plurality of trenches 104 and the plurality of substrate fins 106 are shown in the doped region 103A in Fig. 3C) (Fig. 3C and paragraph 36);
forming a doped-well layer (a layer 112 ) over the fin-shaped portion of the drift layer (the layer 112 of alternative semiconductor material may be doped) (Fig. 3H and paragraph 41);
forming an insulating layer (gate insulation layer 120A ) over the doped-well layer and over the recessed portion of the drift layer (Fig. 3I and paragraph 42); and
forming a gate electrode (a gate electrode 120B) over the insulating layer (Fig. 3I and paragraph 42).
In regard to claim 2, Jacob teaches wherein the substrate comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon (semiconductor substrate 102 is comprised of a first semiconductor material, such as, silicon) (paragraph 31).
In regard to claim 10, Jacob teaches wherein the insulating layer comprises polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide (the gate insulation layer 120A may be comprised of silicon dioxide) (paragraph 42).
In regard to claim 11, Jacob teaches a FinFET device (an N-type FinFET device 100) (Fig. 3A, and paragraph 34), comprising:
a substrate (a substrate 102) (Fig. 4 and paragraph 34);
a drain layer on (substrate contact 107) a first side of the substrate (substrate contact 107 terminates at the final backside of the substrate 102) (Fig. 4 and paragraph 43);
a drift layer (doped region 103A) on a second side of the substrate(the doped region 103A is shown on the top side of the substrate 102 in Fig. 3E) (Fig. 4 and paragraph 38), the drift layer having a fin-shaped portion (a plurality of substrate fins 106) and a recessed portion (a plurality of trenches 104 and the plurality of substrate fins 106 are shown in the doped region 103A in Fig. 3I) (Fig. 3I and paragraph 36);
a doped-well layer (a layer 112 ) over the fin-shaped portion of the drift layer (the layer 112 of alternative semiconductor material may be doped) (Fig. 4 and paragraph 41);
an insulating layer (gate insulation layer 120A ) over the doped-well layer and over the recessed portion of the drift layer (Fig. 4 and paragraph 42); and
a gate electrode (a gate electrode 120B) over the insulating layer (Fig. 4 and paragraph 42).
In regard to claim 12, Jacob teaches wherein the substrate comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon (semiconductor substrate 102 is comprised of a first semiconductor material, such as, silicon) (paragraph 31).
In regard to claim 20, Jacob teaches wherein the insulating layer comprises polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide (the gate insulation layer 120A may be comprised of silicon dioxide) (paragraph 42).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jacob as applied to claim 2 or 12 above, and further in view of Suzuki et al. (US 2013/0082282 A1; hereinafter “Suzuki”) with support from Ferreira da Silva et al. ( Phys. Rev. B 74, 245201– Published 5 December, 2006, Vol. 74, Iss. 24 — 15 December 2006, Received 26 September 2006; hereinafter “Ferreira da Silva”).
In regard to claim 3, Jacob doesn’t explicitly teach wherein the substrate comprises a first type dopant so as to have a resistivity of less than 25 milliohm-cm.
Suzuki teaches a method for fabricating a FinFET device (a fin-type semiconductor device) (Fig. 5A, and paragraph 9), wherein a substrate comprises a first type dopant so as to have a resistivity of less than 25 milliohm-cm (SiC substrate 12 is a hexagonal crystalline 4H-SiC substrate (n' substrate) containing nitrogen (N) as an n-type impurity in a concentration of approximately 5x1018 cm-1 to 1x1019 cm-1, and with support provided from Ferreira da Silva using Fig.1, the concentration of the nitrogen dopant in a SiC of 300µm thick 4H-SiC substrate would have a resistivity less than 25 mΩ-cm) (Suzuki Fig.1 and paragraph 40) (Ferreira da Silva Fig. 1 and Fig. 2).
It would have been obvious to one skilled in the art to combine the teachings of Jacob with the teachings of Suzuki to have the substrate comprises a first type dopant so as to have a resistivity of less than 25 milliohm-cm since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In regard to claim 13, Jacob doesn’t explicitly teach wherein the substrate comprises a first type dopant so as to have a resistivity of less than 25 milliohm-cm.
Suzuki teaches a FinFET device (a fin-type semiconductor device) (Fig. 5A, and paragraph 9), wherein a substrate comprises a first type dopant so as to have a resistivity of less than 25 milliohm-cm (SiC substrate 12 isa hexagonal crystalline 4H-SiC substrate (n' substrate) containing nitrogen (N) as an n-type impurity in a concentration of approximately 5x1018 cm-1 to 1x1019 cm-1, and with support provided from Ferreira da Silva using Fig. 1, the concentration of the nitrogen dopant in a SiC of 300µm thick 4H-SiC substrate would have a resistivity less than 25 mΩ-cm) (Suzuki Fig.1 and paragraph 40) (Ferreira da Silva Fig. 1 and Fig. 2).
It would have been obvious to one skilled in the art to combine the teachings of Jacob with the teachings of Suzuki to have the substrate comprises a first type dopant so as to have a resistivity of less than 25 milliohm-cm since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jacob in view of Suzuki as applied to claims 3 or 13 above, and further in view of Ren (CN 113410307 A).
In regard to claim 4, Jacob in view of Suzuki doesn’t explicitly teach wherein the drain layer comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon.
Ren teaches a method for fabricating a FinFET device (a field effect transistor structure) (Fig. 2 and paragraph 100), wherein a drain layer (a back surface 12 of the drain substrate 1) comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon (electron flow can output uniformly on the back surface 12 of the drain substrate 1and is formed of silicon) (Fig. 1 and paragraphs 102 and 141).
It would’ve been obvious to one skilled in the art to combine the teachings of Jacob with the teachings of Ren to have the drain layer comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 14, Jacob in view of Suzuki doesn’t explicitly teach wherein the drain layer comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon.
Ren teaches a method for fabricating a FinFET device (a field effect transistor structure) (Fig. 2 and paragraph 100), wherein a drain layer (a back surface 12 of the drain substrate 1) comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon (the back surface 12 of the drain substrate 1 and is formed of silicon and electron flow can output uniformly) (Fig. 1 and paragraphs 102 and 141).
It would’ve been obvious to one skilled in the art to combine the teachings of Jacob with the teachings of Ren to have the drain layer comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 5-9 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jacob in view of Suzuki and Ren as applied to claims 4 or 14 above, and further in view of Gupta et al. (WO 2023285549 A1; hereinafter “Gupta”)
In regard to claim 5, Jacob in view of Suzuki and Ren don’t explicitly teach wherein the drain layer comprises a first concentration of the first type dopant.
Gupta teaches a method for fabricating a FinFET device (a power semiconductor device 1) (Fig. 14 and [pg. 29, lns15-19]), wherein teach wherein a drain layer comprises a first concentration of a first type dopant (the drain region 24 which is of the first conductivity type, too, but, for example, with a maximum doping concentration higher than in the drift region 23) (Fig. 14 and [pg. 29, lns20-25]).
It would have been obvious to one skilled in the art to combine the teachings of Jacob in view of Suzuki and Ren with the teachings of Gupta to have the drain layer comprises a first concentration of the first type dopant since this allows the manufacture of a power semiconductive device with improved electrical behaviors as taught by Gupta ([pg. 21, lns.25-31]) 25-31]).
In regard to claim 6 Jacob teaches wherein the drift layer comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon (an ion implantation process 103 is performed to form a doped region 103A in the substrate 102 and therefore would be made of silicon) (Fig. 3B , paragraphs 31 and 34).
In regard to claim 7, Jacob in view of Suzuki, Ren and Gupta teach wherein the drift layer comprises a second concentration of the first type dopant, the second concentration different from the first concentration (there is the drain region 24 which is of the first conductivity type with a maximum doping concentration higher than in the drift region 23 having the first conductivity type) Fig. 14 and [pg. 29, lns20-25]).
In regard to claim 8, Jacob in view of Suzuki, Ren and Gupta teach wherein the first concentration of the first type dopant is greater than the second concentration of the first type dopant (there is the drain region 24 which is of the first conductivity type with a maximum doping concentration higher than in the drift region 23 having the first conductivity type) (Gupta, Fig. 14 and [pg. 29, lns20-25]).
In regard to claim 9, Jacob in view of Ren and Gupta don’t explicitly teach wherein the doped-well layer comprises a third concentration of a second type dopant.
Suzuki teaches wherein a doped-well layer (p-well region 16) comprises a third concentration of a second type dopant (as p-well region 16 is a has a p conductivity it would have a different dopant with a third concentration from the n layer 14) (Fig. 1 and paragraph 42).
It would have been obvious to one skilled in the art to combine the teachings of Jacob in view of Ren and Gupta with the teachings of Suzuki to have the doped-well layer comprises a third concentration of a second type dopant since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 15, Jacob in view of Suzuki and Ren don’t explicitly teach wherein the drain layer comprises a first concentration of the first type dopant.
Gupta teaches a FinFET device (a power semiconductor device 1) (Fig. 14 and [pg. 29, lns15-19]), wherein teach wherein a drain layer comprises a first concentration of a first type dopant (the drain region 24 which is of the first conductivity type, too, but, for example, with a maximum doping concentration higher than in the drift region 23) (Fig. 14 and [pg. 29, lns20-25]).
It would have been obvious to one skilled in the art to combine the teachings of Jacob in view of Suzuki and Ren with the teachings of Gupta to have the drain layer comprises a first concentration of the first type dopant since this allows the manufacture of a power semiconductive device with improved electrical behaviors as taught by Gupta ([pg. 21, lns. 25-31]).
In regard to claim 16, Jacob teaches wherein the drift layer comprises bulk gallium nitride, diamond, silicon carbide, aluminum nitride, or silicon (an ion implantation process 103 is performed to form a doped region 103A in the substrate 102 and therefore would be made of silicon) (Fig. 3B , paragraphs 31 and 34).
In regard to claim 17, Jacob in view of Suzuki, Ren and Gupta teach wherein the drift layer comprises a second concentration of the first type dopant, the second concentration different from the first concentration (there is the drain region 24 which is of the first conductivity type with a maximum doping concentration higher than in the drift region 23 having the first conductivity type) (Gupta, Fig. 14 and [pg. 29, lns20-25]).
In regard to claim 18, Jacob in view of Suzuki, Ren and Gupta teach wherein the first concentration of the first type dopant is greater than the second concentration of the first type dopant (there is the drain region 24 which is of the first conductivity type with a maximum doping concentration higher than in the drift region 23 having the first conductivity type) (Gupta, Fig. 14 and [pg. 29, lns20-25]).
In regard to claim 19, Jacob in view of Ren and Gupta don’t explicitly teach wherein the doped-well layer comprises a third concentration of a second type dopant.
Suzuki teaches wherein a doped-well layer (p-well region 16) comprises a third concentration of a second type dopant (as p-well region 16 is a has a p conductivity it would have a different dopant with a third concentration from the n layer 14) (Fig. 1 and paragraph 42).
It would have been obvious to one skilled in the art to combine the teachings of Jacob in view of Ren and Gupta with the teachings of Suzuki to have the doped-well layer comprises a third concentration of a second type dopant since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al (US 20230335595 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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