Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The Amendment filed March 9, 2026 has been entered.
Amendments therein overcome the previous prior objection(s) in this application.
Claims 12-13, 15-16, 18-19, 21-22, 24-49, and 32-33 are rejected over the previously applied reference(s).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12-13, 15, 18-19, and 32-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2003/0091135 to Bonafos et al. (“Bonafos”) (cited in an IDS).
With respect to claim 12, Bonafos discloses in Figs. 1 and 5 a method, comprising:
receiving, by a glitch filter associated with a serial interface bus (e.g., serial clock (“digital input signal” (e.g., Para. 27)) bus INPUT(G) shown in Fig. 1), an input signal associated with a glitch (e.g., glitches in the digital input signal INPUT(G) (e.g., Para. 27));
rejecting, by the glitch filter (e.g. the Fig. 5 circuit), the glitch based at least in part on a plurality of state machine transitions (e.g., D1, in response to Input (G) received by INV (shown in Fig. 1) in Fig. 5, transitions through D1’s states, which in turn transitions P, which in turn transitions OUTPUT in Fig. 5, wherein OUTPUT rejects glitches G as shown in Fig. 2 and produces OUTPUT without glitches as shown in Fig. 2, wherein a delay ∆t through T (e.g., Para. 42) may be equal to a maximum duration (e.g., Para. 45) (e.g., 10 ns according to Para. 37) of a glitch G so that any glitches G less than delay ∆t through T are rejected and do not pass through to OUTPUT and OUTPUT is “with no glitch” (e.g., Paras. 37 and 48)) and a set of timers (e.g., T having a delay ∆t (e.g., Para. 42) and series inverters between Q and R of D1 are timers in that they delay (e.g., adjust timing) signals to suppress glitches in OUTPUT) associated with the glitch filter; and
providing, by the glitch filter, the output signal (e.g., OUTPUT) based at least in part on the plurality of state machine transitions (e.g., as discussed above) and the set of timers (e.g., as discussed above), wherein the glitch filter transitions an output state (e.g., OUTPUT) only in response to an input signal edge having a pulse width that is at least a threshold duration (e.g., any glitches longer than a delay ∆t through T (e.g., ∆t corresponding to the threshold duration) are not rejected and pass through to OUTPUT (e.g., Paras. 37 and 48) (e.g., D1, in response to Input (G) received by INV (shown in Fig. 1) in Fig. 5, transitions through D1’s states, which in turn transitions P, which in turn transitions OUTPUT in Fig. 5, wherein OUTPUT rejects glitches G as shown in Fig. 2 and produces OUTPUT without glitches as shown in Fig. 2, wherein a delay ∆t through T (e.g., Para. 42) may be equal to a maximum duration (e.g., Para. 45) (e.g., 10 ns according to Para. 37) of a glitch G so that any glitches G less than delay ∆t through T are rejected and do not pass through to OUTPUT and OUTPUT is “with no glitch” (Paras. 37 and 48)).
With respect to claim 13, the glitch filter (e.g., Fig. 5 circuit) is an asynchronous (e.g., the Fig. 5 circuit does not require a clock input) finite state (e.g., D1-D2 each have two states) machine (AFSM) digital filter.
With respect to claim 15, the glitch filter (e.g., Fig. 5 circuit) is associated with one or more delay cells (e.g., T and series inverters between Q and R of D1) and a latch (e.g., D1), wherein an input signal level (e.g., output of T) is maintained for the one or more delay cells (e.g., output of T is maintained for delay through T upon transition of INPUT(G)), and the latch (e.g., D1) prevents transitions (e.g., from effecting the output signal) of the input signal (e.g., INPUT(G)) that are narrower than (e.g., glitches less than a known maximum duration, which may be smaller in faster systems (i.e., adjustable/programmable (e.g., Para. 37), are prevented from effecting the output signal) a programmable bandwidth setting (i.e., adjustable/programmable (e.g., Para. 37).
With respect to claim 18, the glitch is a rising edge glitch or a falling edge glitch, and the input signal (e.g., INPUT(G)) is a clock signal or a data signal.
With respect to claim 19, without further clarification in the claim specifying the kind of association, the serial interface bus (e.g., INPUT(G)) may be associated with an arbitrary power management integrated circuit (PMIC) at an arbitrary place elsewhere.
With respect to claim 32, the above discussion for claim 12 similarly applies.
With respect to claim 33, without further clarification and/or distinction in the claim, a high timer and a low timer are interpreted to mean any timers that may be labeled as “a high timer” and “a low timer.” T having a delay ∆t (e.g., Para. 42) and series inverters between Q and R of D1 are timers in that they delay (e.g., adjust timing) signals to suppress glitches in OUTPUT and may each be labeled as a “high timer” or a “low timer.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 21-22 and 24-29 are rejected under 35 U.S.C. 103 as being unpatentable over Bonafos.
With respect to claim 21, the above discussion for claim 12 similarly applies. Bonafos fails to disclose that the functions of the Fig. 5 circuit may be controlled/performed/enabled using a non-transitory computer-readable medium storing a set of instructions. However, it was notoriously well known before the effective filing date of the claimed invention that functions of a circuit may be controlled/performed/enabled by a non-transitory computer-readable medium storing a set of instructions. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing of the claimed invention to control/perform/enable the functions of the Fig. 5 circuit of Bonafos using the notoriously well-known method of controlling/performing/enabling a circuit by using a non-transitory computer-readable medium storing a set of instructions because such a modification allows a computer to control/perform/enable the circuit.
With respect to claims 22, 24, and 28-29, the above discussion for dependent claims of claim 12 similarly applies.
With respect to claims 16, 25, and 27, Bonafos fails to disclose use of a switched resistor to automatically adjust/control/match an output impedance in outputting Input (G) to FILT in Fig. 1 to adjust/reduce/minimize reflection/glitches. However, it was notoriously well known before the effective filing date of the claimed invention to use a switched resistor to automatically adjust/match/control an output impedance in outputting a signal and adjust/educe/minimize reflection/glitches. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing of the claimed invention to use, in outputting INPUT(G) to FILT, in Fig. 1 of Bonafos, the notoriously well-known method of to using a switched resistor to automatically adjust/match/control an output impedance in outputting a signal because such a modification adjusts/reduces/minimizes reflection/glitches.
With respect to claim 26, without further clarification in the claim specifying the kind of association, the output driver outputting Input (G) to FILT in Fig. 1 may be associated with an arbitrary programmable slew rate at an arbitrary place elsewhere.
Response to Arguments
Applicant's arguments filed March 9, 2026 have not been found persuasive. For example, Applicant argues that Bonafos does not disclose the glitch filter transitions an output state only in response to an input signal edge having a pulse width that is at least a threshold duration as called for claim 12. However, as stated above in the main body of the rejection, Bonafos discloses such a feature.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Allowable Subject Matter
Claims 14, 17, 23, and 30-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842
Prosecution Insights