DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
02/10/2026 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 02/10/2026. Claims 1 -
13 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4,6-9 and 11-12 are rejected under 35 U.S.C. 103 as being
unpatentable over Li et al. (US 20100293320 A1) in view of La Rosa et al. (US 20080301357 A1) hereinafter Li and La Rosa.
Regarding claim 1, Li teaches A method for emulating electrically-erasable programmable read-only memory by using a flash memory, the method comprising: (see abstract, paragraph [0008], a flash memory can emulate programming and erase like EEPROM)
dividing each of units of the flash memory into a data field and an address field; allocating a part of the units as a first page in a sector; (see Fig 2, paragraph [0059], write log data 230 which is part of sector 128 has address field and data field)
wherein in response to an instruction to write data into a first specific storage unit of the sector, the method comprises: (see Fig 6, paragraph [0082], at step 610 in response to write command to write an updated data at a particular logical address write operation begins)
determining, starting from the first specific storage unit of the first page of the sector, whether each of the address fields of the units of the first page has been written; (see Fig 6, paragraph [0084], at step 630 write log area of active sector is searched to find free location or make determination if the write log area is written)
when one of the address fields is in a written state,
wherein both a data field and an address field of the writable unit have not been written; and (see Fig 6, paragraph [0084], at step 640 the write operation looks for free location in write log area of active sector and make the determination if there is any free location to advance to step 660 or 650)
writing the data into the data field of the writable unit and writing the address field of the final unit into the address of the writable unit. (see Fig 6, paragraph [0084], at step 650 after making determination of free write log location in the sector, both data and logical address field is written to the location)
Li teaches emulating EEPROM with flash memory above. However, Li does not explicitly teach finding a next unit based on the one of the address fields until a final unit is found, wherein an address of the next unit is data written in the one of the address fields, and
On the other hand, La Rosa which also relates to emulating EEPROM with flash
memory teaches finding a next unit based on the one of the address fields until a final unit is found, wherein an address of the next unit is data written in the one of the address fields, and (see Fig 2-5, paragraph [0097], [0110] and [0119], illustrates rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field)
Both Li and La Rosa relate to emulating EEPROM with flash memory. Li teaches
emulating EEPROM with flash memory of single active sector. On the other hand,
La Rosa teaches EEPROM with flash memory and rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Li with La Rosa by incorporating emulating EEPROM with flash memory, as taught by La Rosa, to rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. The combined system of Li - La Rosa allows FLASH memories to be able to compete with EEPROM memories in terms of flexibility of use, without losing their advantages in terms of storage capacity per unit of silicon surface as mentioned in paragraph [0007].
Regarding claim 2, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 1. However, Li - La Rosa combination does not explicitly teach The method according to Claim 1, in response to the instruction to read a second specific storage unit of the sector, further comprising:
determining, starting from the second specific storage unit of an initial page of the sector, whether one of the address fields of the units of the initial page has been written;
when the one of the address fields is in a written state, finding a next unit based on the one of the address fields until a target unit is found, wherein an address field of the target unit has not been written; and
reading a data field of the target unit
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The method according to Claim 1, in response to the instruction to read a second specific storage unit of the sector, further comprising: (see Fig 7, paragraph [0088], illustrates at step 710 in response to read command to read a particular logical address read operation begins)
determining, starting from the second specific storage unit of an initial page of the sector, whether one of the address fields of the units of the initial page has been written; (see Fig 7, paragraph [0090], at step 730 of the read operation it searches for write log data in write log area of active sector if they are written)
when the one of the address fields is in a written state, finding a next unit based on the one of the address fields until a target unit is found, wherein an address field of the target unit has not been written; and (see Fig 7, paragraph [0091], after step 730 the operation finds an entry where write data log is not written for a particular address)
reading a data field of the target unit. (see Fig 7, paragraph [0091], at step 750 after finding that particular address in write log area is not written, data stored in the corresponding entry is read)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 1 is equally applicable to claim 2.
Regarding claim 3, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 1. However, Li - La Rosa combination does not explicitly teach The method according to claim 1, wherein the flash memory is a NAND flash memory built in a microprocessor
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The method according to claim 1, wherein the flash memory is a NAND flash memory built in a microprocessor. (see Fig 1, paragraph [0043], computer system 100 includes processor 114 and flash memory 120)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 2. However, Li - La Rosa combination does not explicitly teach The method according to Claim 2, further comprising: allocating at least one second page in the sector;
wherein in response to the instruction to write the second specific storage unit of the sector, the method further comprises:
when the first page is fully stored, finding a unit of the second page, wherein an address field of the unit of the second page has not been written; and
writing a data field of the found unit of the second page
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The method according to Claim 2, further comprising: allocating at least one second page in the sector;
wherein in response to the instruction to write the second specific storage unit of the sector, the method further comprises: (see Fig 2, paragraph [0065], a second sector 128b-1 can be activated or allocated for write operations to the write-log area 210b-1 of sector 128b-1)
when the first page is fully stored, finding a unit of the second page, wherein an address field of the unit of the second page has not been written; and (see Fig 6, paragraph [0084], at step 640 the write operation looks for free location in write log area of active sector and make the determination if there is any free location to advance to step 660 or 650)
writing a data field of the found unit of the second page. (see Fig 6, paragraph [0084], at step 650 after making determination of free write log location in the sector, both data and logical address field is written to the location)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 1 is equally applicable to claim 4.
Regarding claim 6, Li teaches A method for emulating electrically-erasable programmable read-only memory by using a flash memory, the method comprising: (see abstract, paragraph [0008], a flash memory can emulate programming and erase like EEPROM)
dividing each of units of the flash memory into a data field and an address field; allocating a part of the units as a first page in a sector; (see Fig 2, paragraph [0059], write log data 230 which is part of sector 128 has address field and data field)
wherein in response to an instruction to read a first specific storage unit of the sector, the method comprises: (see Fig 7, paragraph [0088], at step 710 in response to read command to read a particular logical address read operation begins)
determining, starting from the first specific storage unit of the first page of the sector, whether one of the address fields of the units has been written; (see Fig 7, paragraph [0090], at step 730 of the read operation it searches for write log data in write log area of active sector if they are written)
when the one of the address fields is in a written state, wherein an address field of the target unit has not been written; and (see Fig 7, paragraph [0091], after step 730 the operation finds an entry where write data log is not written for a particular address)
reading the data field of the target unit. (see Fig 7, paragraph [0091], at step 750 after finding that particular address in write log area is not written, data stored in the corresponding entry is read)
Li teaches emulating EEPROM with flash memory above. However, Li does not explicitly teach finding a next unit based on the one of the address fields until a final unit is found, wherein an address of the next unit is data written in the one of the address fields, and
On the other hand, La Rosa which also relates to emulating EEPROM with flash
memory teaches finding a next unit based on the one of the address fields until a final unit is found, wherein an address of the next unit is data written in the one of the address fields, and (see Fig 2-5, paragraph [0097], [0110] and [0119], illustrates rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field)
Both Li and La Rosa relate to emulating EEPROM with flash memory. Li teaches
emulating EEPROM with flash memory of single active sector. On the other hand,
La Rosa teaches EEPROM with flash memory and rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Li with La Rosa by incorporating emulating EEPROM with flash memory, as taught by La Rosa, to rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. The combined system of Li - La Rosa allows FLASH memories to be able to compete with EEPROM memories in terms of flexibility of use, without losing their advantages in terms of storage capacity per unit of silicon surface as mentioned in paragraph [0007].
Regarding claim 7, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 6. However, Li - La Rosa combination does not explicitly teach The method according to Claim 6, wherein in response to an instruction to write data into a second specific storage unit of the sector, the method comprises:
determining, starting from the second specific storage unit of the first page of the sector, whether one of the address fields of the units has been written;
if the one of the address fields is in a written state, finding a next unit based on the one of the address fields until a final unit is found, wherein an address field of the final unit has not been written;
finding a writable unit, wherein both a data field and an address field of the writable unit have not been written; and
writing the data into the data field of the writable unit and writing the address field of the final unit into the address of the writable unit
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The method according to Claim 6, wherein in response to an instruction to write data into a second specific storage unit of the sector, the method comprises: (see Fig 2, paragraph [0065], a second sector 128b-1 can be activated or allocated for write operations to the write-log area 210b-1 of sector 128b-1)
determining, starting from the second specific storage unit of the first page of the sector, whether one of the address fields of the units has been written; (see Fig 7, paragraph [0090], at step 730 of the read operation it searches for write log data in write log area of active sector if they are written)
if the one of the address fields is in a written state, finding a next unit based on the one of the address fields until a final unit is found, wherein an address field of the final unit has not been written;
finding a writable unit, wherein both a data field and an address field of the writable unit have not been written; and (see Fig 6, paragraph [0084], at step 640 the write operation looks for free location in write log area of active sector and make the determination if there is any free location to advance to step 660 or 650)
writing the data into the data field of the writable unit and writing the address field of the final unit into the address of the writable unit. (see Fig 6, paragraph [0084], at step 650 after making determination of free write log location in the sector, both data and logical address field is written to the location)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 6 is equally applicable to claim 7.
Regarding claim 8, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 7. However, Li - La Rosa combination does not explicitly teach The method according to Claim 7, further comprising: allocating at least one second page in the sector;
wherein in response to the instruction to write the second specific storage unit of the sector, the method further comprises: when the first page is fully stored,
finding a unit of the second page, wherein an address field of the unit of the second page has not been written; and
writing a data field of the found unit
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The method according to Claim 7, further comprising: allocating at least one second page in the sector; (see Fig 2, paragraph [0065], a second sector 128b-1 can be activated or allocated for write operations to the write-log area 210b-1 of sector 128b-1)
wherein in response to the instruction to write the second specific storage unit of the sector, the method further comprises: when the first page is fully stored, (see Fig 6, paragraph [0084], at step 640 the write operation looks for free location in write log area of active sector and make the determination if there is any free location to advance to step 660 or 650)
finding a unit of the second page, wherein an address field of the unit of the second page has not been written; and (see Fig 6, paragraph [0084], at step 640 the write operation looks for free location in write log area of active sector and make the determination if there is any free location to advance to step 660 or 650)
writing a data field of the found unit. (see Fig 6, paragraph [0084], at step 650 after making determination of free write log location in the sector, both data and logical address field is written to the location)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 6 is equally applicable to claim 8.
Regarding claim 9, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 6. However, Li - La Rosa combination does not explicitly teach The method according to claim 6, wherein the flash memory is a NAND flash memory built in a microprocessor
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The method according to claim 6, wherein the flash memory is a NAND flash memory built in a microprocessor. (see Fig 1, paragraph [0043], computer system 100 includes processor 114 and flash memory 120)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 6 is equally applicable to claim 9.
Regarding claim 11, Li teaches A flash memory system, comprising: a control circuit; and a flash memory, (see Fig 1, paragraph [0047], illustrates a computer stem, processor 114 to control management of data and flash memory 120)
each of units of the flash memory being divided into a data field and an address field, and a part of the units being allocated as a first page in a sector, (see Fig 2, paragraph [0059], write log data 230 which is part of sector 128 has address field and data field)
wherein: when the control circuit receives an instruction to write data into a first specific storage unit of the sector, (see Fig 6, paragraph [0082], at step 610 in response to write command to write an updated data at a particular logical address write operation begins)
the control circuit determines, starting from the first specific storage unit of an initial page of the sector, whether one of the address fields of the unit has been written; (see Fig 6, paragraph [0084], at step 630 write log area of active sector is searched to find free location or make determination if the write log area is written)
when the control circuit determines that the one of the address fields is in a written state, the control circuit finds a next unit based on the one of the address fields until a final unit is found, wherein an address field of the final unit has not been written; (see Fig 6, paragraph [0084], at step 630 write log area of active sector is searched to find free location or make determination if the write log area is written)
the control circuit finds a writable unit, wherein both a data field and an address field of the writable unit have not been written; and (see Fig 6, paragraph [0084], at step 640 the write operation looks for free location in write log area of active sector and make the determination if there is any free location to advance to step 660 or 650)
the control circuit writes the data into the data field of the writable unit and writes the address field of the final unit into the address of the writable unit. (see Fig 6, paragraph [0084], at step 650 after making determination of free write log location in the sector, both data and logical address field is written to the location)
Li teaches emulating EEPROM with flash memory above. However, Li does not explicitly teach the control circuit finds a next unit based on the one of the address fields until a final unit is found, wherein an address of the next unit is data written in the one of the address fields, and
On the other hand, La Rosa which also relates to emulating EEPROM with flash
memory teaches the control circuit finds a next unit based on the one of the address fields until a final unit is found, wherein an address of the next unit is data written in the one of the address fields, and (see Fig 2-5, paragraph [0097], [0110] and [0119], illustrates rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field)
Both Li and La Rosa relate to emulating EEPROM with flash memory. Li teaches
emulating EEPROM with flash memory of single active sector. On the other hand,
La Rosa teaches EEPROM with flash memory and rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Li with La Rosa by incorporating emulating EEPROM with flash memory, as taught by La Rosa, to rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. The combined system of Li - La Rosa allows FLASH memories to be able to compete with EEPROM memories in terms of flexibility of use, without losing their advantages in terms of storage capacity per unit of silicon surface as mentioned in paragraph [0007].
Regarding claim 12, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 11. However, Li - La Rosa combination does not explicitly teach The flash memory according to claim 11, wherein the flash memory is a NAND flash memory, and the flash memory system further comprises a microprocessor having the control circuit and the NAND flash memory
On the other hand, Li which also relates to emulating EEPROM with flash
memory teaches The flash memory according to claim 11, wherein the flash memory is a NAND flash memory, and the flash memory system further comprises a microprocessor having the control circuit and the NAND flash memory. (see Fig 6, paragraph [0084], at step 650 after making determination of free write log location in the sector, both data and logical address field is written to the location)
The same motivation that was utilized for combining Li and La Rosa as set
forth in claim 11 is equally applicable to claim 12.
Claim(s) 5,10 and 13 are rejected under 35 U.S.C. 103 as being
unpatentable over Li in view of La Rosa and further in view of LEUNG et al. (US 20100250875 A1) hereinafter LEUNG.
Regarding claim 5, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 1. However, Li - La Rosa combination does not explicitly teach The method according To Claim 1, wherein the method is further used for writing multiple emulated electrically-erasable programmable read-only memories and the method further comprises:
providing a plurality of sectors corresponding to addresses of the multiple emulated electrically-erasable programmable read-only memories.
On the other hand, LEUNG which also relates to emulating EEPROM with flash memory teaches The method according To Claim 1, wherein the method is further used for writing multiple emulated electrically-erasable programmable read-only memories and the method further comprises:
providing a plurality of sectors corresponding to addresses of the multiple emulated electrically-erasable programmable read-only memories. (see Fig 3, paragraph [0082], describes a plurality of flash memory pages may be used in exemplary embodiments of an EEPROM where pages 0-2 may be used for EEPROM emulation writing)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Li with La Rosa for the reasons set forth in claim 1
above. In addition, Li, La Rosa and LEUNG are considered analogous arts, because
they all relate to emulating EEPROM with flash memory. Li – La Rosa combination teaches emulating EEPROM with flash memory of single active sector. On the other hand, LEUNG teaches EEPROM with flash memory and a plurality of flash memory pages may be used where pages 0-2 may be used for EEPROM emulation writing. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Li – La Rosa combination with LEUNG by incorporating emulating EEPROM with flash memory, as taught by LEUNG, to enable plurality of flash memory pages could be used where pages 0-2 may be used for EEPROM emulation writing. The combined system of Li – La Rosa - LEUNG allows two block-erasable pages of memory ping-pong in this manner such that while one page is being written or read, the other page is being erased and vis-a-vis as mentioned in paragraph [0011].
Therefore, the combination of Li – La Rosa - LEUNG improves cost and size. See LEUNG, paragraph [0010].
Regarding claim 10, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 6. However, Li - La Rosa combination does not explicitly teach The method according to claim 6, wherein the method is further used for reading multiple emulated electrically-erasable programmable read-only memories and the method further comprises:
providing a plurality of sectors corresponding to addresses of the multiple emulated electrically-erasable programmable read-only memories
On the other hand, LEUNG which also relates to emulating EEPROM with flash memory teaches The method according to claim 6, wherein the method is further used for reading multiple emulated electrically-erasable programmable read-only memories and the method further comprises:
providing a plurality of sectors corresponding to addresses of the multiple emulated electrically-erasable programmable read-only memories. (see Fig 3, paragraph [0082], describes a plurality of flash memory pages may be used in exemplary embodiments of an EEPROM where pages 1-2 may be used for EEPROM emulation writing)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Li with La Rosa for the reasons set forth in claim 6
above. In addition, Li, La Rosa and LEUNG are considered analogous arts, because
they all relate to emulating EEPROM with flash memory. Li – La Rosa combination teaches emulating EEPROM with flash memory of single active sector. On the other hand, LEUNG teaches EEPROM with flash memory and a plurality of flash memory pages may be used where pages 0-2 may be used for EEPROM emulation writing. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Li – La Rosa with LEUNG by incorporating emulating EEPROM with flash memory, as taught by LEUNG, to enable plurality of flash memory pages could be used where pages 0-2 may be used for EEPROM emulation writing. The combined system of Li – La Rosa - LEUNG allows two block-erasable pages of memory ping-pong in this manner such that while one page is being written or read, the other page is being erased and vis-a-vis as mentioned in paragraph [0011]. Therefore, the combination of Li – La Rosa - LEUNG improves cost and size. See LEUNG, paragraph [0010].
Regarding claim 13, Li in view of La Rosa teaches emulating EEPROM with flash memory in claim 11. However, Li - La Rosa combination does not explicitly teach The flash memory according to claim 11, wherein the flash memory is provided with a plurality of sectors for emulating multiple emulated electrically-erasable programmable read-only memories
On the other hand, LEUNG which also relates to emulating EEPROM with flash memory teaches The flash memory according to claim 11, wherein the flash memory is provided with a plurality of sectors for emulating multiple emulated electrically-erasable programmable read-only memories. (see Fig 3, paragraph [0082], describes a plurality of flash memory pages may be used in exemplary embodiments of an EEPROM where pages 1-2 may be used for EEPROM emulation writing)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Li with La Rosa for the reasons set forth in claim 11
above. In addition, Li, La Rosa and LEUNG are considered analogous arts, because
they all relate to emulating EEPROM with flash memory. Li – La Rosa combination teaches emulating EEPROM with flash memory of single active sector. On the other hand, LEUNG teaches EEPROM with flash memory and a plurality of flash memory pages may be used where pages 0-2 may be used for EEPROM emulation writing. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Li – La Rosa combination with LEUNG by incorporating emulating EEPROM with flash memory, as taught by LEUNG, to enable plurality of flash memory pages could be used where pages 0-2 may be used for EEPROM emulation writing. The combined system of Li – La Rosa - LEUNG allows two block-erasable pages of memory ping-pong in this manner such that while one page is being written or read, the other page is being erased and vis-a-vis as mentioned in paragraph [0011]. Therefore, the combination of Li – La Rosa - LEUNG improves cost and size. See LEUNG, paragraph [0010].
Response to Arguments
Applicant’s arguments filed on 02/10/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claim 1 mapping by primary reference Li in page 2 of the response: While Li mentions page-level writing (Paragraph [0115]), its retrieval mechanism relies on a look-up table or address translation table (see Fig. 4 of Li). The units in Li are not physically linked via pointers stored within the units themselves. The current application recites a structure where each unit points to the next. Specifically, the step of "writing the address field of the final unit into the address of the writable unit" creates a physical link. This effectively retroactively updates the previous unit to point to the new unit.
Also, the Examiner argues that Li's use of logical addresses is "more efficient" and performs the "same function." However, the test for anticipation is structural identity, not efficiency or general functional similarity.
In brief, in Li, the system looks up a table to find data. In the present invention, the system must traverse the units (like a linked list) to find the end of the chain. Because Li lacks this specific "pointer traversal" and "back-filling" step, it cannot anticipate Claim 1
In summary, applicant argued that primary reference Li does not teach
Traversing the units with pointer to find end. The amendment necessitates
adding secondary reference La Rosa in this regard. For further clarification
examiner cites portion from La Rosa. Also, for applicant’s understanding examiner
would like to explain the teachings of La Rosa and examiner’s interpretation in
more detail here. See Fig 2-5, paragraph [0097], [0110] and [0119], La Rosa teaches rotating sectors S1-S4 each comprising N pages where address or pointer field points toward target pages of the rotating sector. In other words, next unit or target sector address of rotating sectors are pointed by the address field. Also, See Fig 3-6, paragraph [0136], La Rosa teaches when counter CPT1 reaches at the end of rotating sectors, it’s switched to 0. The cited portions clearly teach sectors are rotated for write cycle with target or next address or pointers are written in sectors. Thus, the rejection of claims 1, 6 and 11 is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132