Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This is office action is in response to the application filed on June 11,2024.
2. Claims 1-20 are pending and has been examined.
Drawings
3. Drawings submitted on 06/11/2024 are acceptable.
Claim Rejections - 35 USC § 112
4.The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “the deasserted enable signal” and “the asserted enable signal” in line 4 respectively. There are insufficient antecedent basis for these claim limitations.
Claim 12 recite “the lower voltage rail” in line 6. There is insufficient antecedent basis for this claim limitation.
Claim 16 recite “a bandgap voltage generating circuit” in line 4 should be “the bandgap voltage generating circuit”.
Claims 13-15 dependent on claim 12, thus are also rejected because of their dependency.
Claims 17-20 dependent on claim 16, thus are also rejected because of their dependency.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Zhou “CN103869868”.
In re to claim 1, Zhou discloses an apparatus (Fig. 2 shows a bandgap reference circuit ), comprising: a bandgap voltage generating circuit (first order bandgap reference circuit 2, see parag.0032), comprising: a first current path (current flow through MP1 and Q1) including a first field effect transistor (FET) (MP1) coupled in series with a first bipolar junction transistor (BJT) (Q1) between an upper voltage rail (VDD) and a lower voltage rail (ground);
a second current path (current flow through MP2, resistor R1 and Q2) including a second FET (MP2) coupled in series with a resistor (R1) and a second BJT (Q2) between the upper voltage rail (VDD) and the lower voltage rail (ground); and
a third current path (current flow through MP13 and resistor R3-R5) including a third FET (MP13) coupled in series with a set of one or more resistors (R3-R5) between the upper voltage rail (Vdd) and the lower voltage rail (ground);
a pull-down circuit (starting circuit 1) coupled to gates of the first, second, and
third FETs (drain terminal of MSN2 is coupled to the gate of MP1, MP2 and MP13) ; and
a switched-capacitor circuit (compensation circuit 3) coupled to the gates of the first, second, and third FETs (gate terminal of MP4 and MP8 are coupled to the gated terminals of MP1, MP2 and MP13 respectively) .
In re to claim 9, Zhou discloses (Fig. 3) wherein the pull-down circuit (starting circuit 1) comprises one or more protection field effect transistors (FETs) (MSP2 & MSN2) coupled between the gates of the first, second, and third FETs (drain terminal of MSN2 is coupled to the gate of MP1, MP2 and MP13) and the pull-down FET (gate terminal of MSN2 is coupled to the gate of MNS4 and drain of MSN1)
In re to claim 10, Zhou discloses an apparatus (Fig. 2 shows a bandgap reference circuit ) comprising: a bandgap voltage generating circuit (first order bandgap reference circuit 2, see parag.0032), having a plurality of current paths (current flow through MP1 and Q1, current flow through MP2, resistor R1 and Q2 and current flow through MP13 and resistor R3-R5), each current path comprising a field effect transistor (FET) (MP1,MP2 and MP13 ) , and gates of the FETs of the plurality of current paths coupled together (gate of MP1,MP2 and MP13 are coupled together);
a pull-down start-up circuit (starting circuit 1) coupled to the gates of the FETs of the plurality of current paths of the bandgap voltage generating circuit (drain terminal of MSN2 is coupled to the gate of MP1, MP2 and MP13), the pull-down start-up circuit comprising a pull-down transistor (MNS2) configured to pull down voltages at the gates of the FETs upon start-up of the bandgap voltage generating circuit (see prag. 0045) ; and
a secondary start-up circuit (compensation circuit 3) comprising a switched-capacitor circuit (MP4 and MP8) coupled to the gates of the plurality of FETs of the plurality of current paths of the bandgap voltage generating circuit (gate terminal of MP4 and MP8 are coupled to the gated terminals of MP1, MP2 and MP13 respectively),
the switched-capacitor circuit (MP4 and MP8) configured to draw additional current from the gates of the FETs upon the start-up of the bandgap voltage generating circuit (gate terminal of MP4 and MP8 are coupled to the gated terminals of MP1, MP2 and MP13 to draw current to provide stability , see prag.0030 and 0085) .
Allowable Subject Matter
6. Claims 2-8 and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected because the prior art in the record fails to disclose or suggest the apparatus including the limitation of “wherein the bandgap voltage generating circuit comprises a first switching device coupled between the upper voltage rail and the gates of the first, second, and third FETs.”
Claim 7 is objected because the prior art in the record fails to disclose or suggest the apparatus including the limitation of “a pair of resistors coupled across the first and second inputs of the operational amplifier; and an additional resistor coupled to a node between the pair of resistors and the lower voltage rail.”
Claim 8 is objected because the prior art in the record fails to disclose or suggest the apparatus including the limitation of “ a comparator including a first input coupled to the reference voltage generator, and a second input coupled to a source of the third FET; and a pull-down field effect transistor (FET) coupled between the gates of first, second, and third FETs and the lower voltage rail, wherein the pull-down FET includes a gate coupled to an output of the comparator.”
Claim 11 is objected because the prior art in the record fails to disclose or suggest the apparatus including the limitation of “the bandgap voltage generating circuit comprises a first switching device coupled between an upper voltage rail and the gates of the FETs, wherein the first switching device is configured to close in response to the deasserted enable signal, and open in response to the asserted enable signal.”
Claims 3-6 dependent on claim 2, thus are also objected because of their dependency.
Claims 12-15 dependent on claim 11, thus are also objected because of their dependency.
7. Claims 16-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 9 is allowed because the prior art in the record fails to disclose or suggest a method including the limitation of “partially charging a capacitor in response to disabling a bandgap voltage generating circuit; and enabling a bandgap voltage generating circuit comprising: pulling down voltages at gates of a set of field effect transistors (FETs); and further charging the capacitor to draw additional current from the gates of the set of FETs.”
Claims 17-20 dependent on claim 16, thus are also allowed because of their dependency.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zheng “CN 105912064” the invention belongs to the technical field of integrated circuit, and more particularly, to a high precision and high power supply rejection ratio of the band gap reference source.
HE “CN109725672” the invention relates to a circuit technology field, especially relates to a band gap reference circuit and high-order temperature compensation method.
Uannounced inventor “CN107045370” the invention relates to electronic technology field, especially relates to a band-gap reference voltage source circuit with high-order temperature compensation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838