Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on December 9th, 2025. Claims 1-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7-12, 16, 17, 18 are rejected 35 U.S.C. 103 as being unpatentable over OOISHI et al. (US Pat No. 6166990 A, hereinafter referred to as Ooishi) in view of Ryan et al. (US Pat No. 8947816 B1, hereinafter referred to as Ryan) and further in view of Raychowdhury et al. (USPGPUB No. 2014/0218069 A1, hereinafter referred to as Raychowdhury).
Referring to claim 1, Ooishi discloses a serial interface comprising an I/O (input/output) cell {“bank in memory circuit 2”, see Figs. 6 and 7, Col 13, lines 60-61)} configured to facilitate communication of serial data {“interface circuit 10 includes a serial/parallel conversion circuit 10w”, see Fig. 5, Col 13, lines 28-31}, the I/O cell comprising:
a clock pad configured {“Clock tree 87 includes buffers”, see Fig. 37, Col 34, lines 57-59 } to receive a clock signal {“CLKf”, Col 34, lines 41-44} from the initiator device {“CLKf” from initiator “fine adjust circuit 85”, see Fig. 37, Col 34, lines 41-44};
a data pad configured {data pad “Write/read circuit 5012”, see Fig. 82, Col 2, lines 43-45} to receive a data output signal {“operation mode designating signal”, see Fig. 82, Col 2, line 42} from control logic of the target device {Control logic “Control circuit 5008” as claimed, see Fig. 82, Col 2, lines 40-43};
a clock input buffer coupled to the clock pad {clock input buffer “buffer circuit 86”, see Fig. 37, Col 34, lines 35-37} and configured to receive the clock signal {“buffering clock signal CLKf output”, see Fig. 37, Col 34, lines 35-37};
a flip-flop coupled to the clock input buffer and configured to {“ each [flip flop] buffer in internal circuit 90.”, see Fig. 37, Col 34, lines 59-61}: receive the clock signal from the clock input buffer {“for branching the clock signal from buffer circuit 86”, Col 34, lines 37-38}, receive the data output signal from the control logic of the target device {“ circuit 90 includes an address buffer and a [data output signal] control signal input buffer.”, see Fig. 37, Col 34, lines 59-61, and output the data output signal in synchronization with the clock signal {“operation mode designating signal”, see Fig. 82, Col 2, line 42};
and a data output buffer coupled to the flip-flop {“[data output buffer] bi-directional shift register 102 shifting the stored data bi-directionally”, see Fig. 43, Col 37, lines 60-61}, the data output buffer configured to receive the data output signal output by the flip-flop {“switching element SW2 between latch circuits 102am and 102as to transfer data in response to a transfer designating signal T.phi.”, see Fig. 45a, Col 39, lines 25-27} and to drive the data output signal to the data pad for access by the initiator device {driving “In a latching state, transfer designating signals”, see Fig. 43, Col 39, lines 50-52}.
Ooishi does not appear to explicitly disclose an I/O cell configured to facilitate communication of serial data from a target device to an initiator device,
However, Ryan discloses an I/O cell configured to facilitate communication of serial data from a target device {“powering only the [target device] DSD required” (see Fig. 1a, such as “server rack 100”, Col 1, lines, and Col 1, lines 21-22)} to an initiator device {“for an [initiator sent] active request for data”, see Fig. 1, Col 1, lines 21-22; serial data via “Serially Attached SCSI (SAS) expander board 180” (see Fig. 1a, Col 2, line 32).}.
Ooishi and Ryan are analogous because they are from the same field of endeavor, serial data processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ooishi and Ryan before him or her, to modify Ooishi’s “interface circuit 10” (see Figs. 6 and 7) incorporating Ryan’s cold storage data functionality (see Fig. 1).
The suggestion/motivation for doing so would have been to implement a cold storage serial data transmission where one DSD in the tray is powered at a time, to reduce power, heat, and vibration taking advantage the other inactive DSDs may include components which are not simultaneously needed or utilized, and may therefore be redundant while consuming excess power (Ryan Col 1, lines 23-29 paraphrased).
Therefore, it would have been obvious to combine Ryan with Ooishi to obtain the invention as specified in the instant claim(s).
Neither Ooishi or Ryan does not appear wherein the data output signal output is configured to facilitate communication of serial data to the initiator device.
However, Raychowdhury discloses wherein the data output signal output {data output signal “content output” ([0055]) configured by timing considerations and “multi-supply FF sequential logic unit 700 with boosted slave latch” (see Fig. [0059], 2nd sentence), that “FF sequential logic” in one embodiment “vectored sequential logic configuration 300” ([0032], 1st sentence)} is configured to facilitate communication {“allow device 600 to control [facilitate communication] content output, for example, to audiovisual or other systems” ([0055], last sentence)} of serial data {“Universal Serial Bus (USB) connector”, see Fig. 6 [0056]} to the initiator device {the initiator device “I/O controller 640”, see Fig. 6 [0050], 1st sentence}.
Ooishi/Ryan and Raychowdhury are analogous because they are from the same field of endeavor, serial data processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ooishi/Ryan and Raychowdhury before him or her, to modify Ooishi/Ryan’s system incorporating Raychowdhury’s “vectored sequential logic configuration 300” ([0032], 1st sentence).
The suggestion/motivation for doing so would have been to implement boosting the clock path, i.e. operating the clock path on a higher power supply level compared to the power supply level of the data path, the inherent data contention in the sequential logic unit is reduced resulting in a faster resolution of data which in turn results in a faster data path (e.g., faster by 50% over the data path speed of the flip-flop 100 of FIG. 1) along with allowing the clock distribution network to operate on the lower power supply level (Vmin) to reduce the power consumption in the clock distribution network (Raychowdhury [0021], last two sentences).
Therefore, it would have been obvious to combine Raychowdhury with Ooishi/Ryan to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Ooishi discloses wherein the I/O cell further comprises:
a data output voltage level shifter configured to be coupled {“Bi-directional shift registers FSR and CSR have”, Col 61, lines 40-42} between the flip-flop and the control logic of the target device {“carrying out a shift operation according to control signal CTL”, see Figs. 69 and 45, Col 61, lines 29-31}, wherein the flip-flop is configured to operate in a first voltage domain {“signals QB1-QBn and QF1-QFm in a predetermined sequence [voltage domain]”, see Fig. 45, Col 61, lines 41-43} and the control logic is configured to operate in a second voltage domain {“In the structure of the second shift sequence [voltage domain]”, see Fig. 45, Col 61, lines 57-58}, and the data output voltage level shifter is further configured to translate a voltage level of the data output signal {“changes from the maximum value or from the minimum value”, see Fig. 45, Col 61, lines 53-56} from the second voltage domain to the first voltage domain {“a shift operation is carried out in the shift register”, see Fig. 45, Col 61, lines 55-57}.
As per claim 7, the rejection of claim 1 is incorporated and Ooishi discloses a data storage device comprising the serial interface of claim 1 {data storage device “structure of input/output buffer circuit 7 of FIG. 1.” (Col 12, lines 64-65) including serial interface “interface circuit 10 includes a serial/parallel conversion circuit 10w” (see Fig. 5, Col 13, lines 29-31).}.
Referring to claim 8, is an apparatus claim reciting claim functionality corresponding to the device claim of claim 1, respectively, thereby rejected under the same rationale as claim 1 recited above.
As per claim 9, the rejection of claim 8 is incorporated and Ryan discloses wherein the target device is a preamplifier {“preamp 235” or “preamp 211” (see Fig. 2b, Col 3, lines 8-12)} of a hard disk drive (HDD) {“HDA 200”, see Fig. 2b, Col 5, lines 12} and the initiator device is a controller of the HDD {“primary read channel, controller,”, see Fig. 2C, Col 3, line 28}.
As per claim 10, the rejection of claim 9 is incorporated and Ryan discloses a hard disk drive (HDD) comprising the circuit of claim 9 {“hard disk assembly (HDA)”, see Figs. 2a and 2c, Col 1, lines 45-46}.
As per claim 11, the rejection of claim 8 is incorporated and Ryan discloses wherein the target device is a serial flash memory {“NAND flash memory” that also have serial flash implementation “NOR memory”, see Fig. 1a, Col 2, lines 15-16 and line 237}.
As per claim 12, the rejection of claim 8 is incorporated and Ooishi discloses wherein the I/O cell further comprises:
a data output voltage level shifter coupled {“Bi-directional shift registers FSR and CSR have”, Col 61, lines 40-42} between the flip-flop and the control logic of the target device {“carrying out a shift operation according to control signal CTL”, see Figs. 69 and 45, Col 61, lines 29-31},
wherein the flip-flop is configured to operate in a first voltage domain {“signals QB1-QBn and QF1-QFm in a predetermined sequence [voltage domain]”, see Fig. 45, Col 61, lines 41-43} and the control logic is configured to operate in a second voltage domain {“In the structure of the second shift sequence [voltage domain]”, see Fig. 45, Col 61, lines 57-58}, and wherein the data output voltage level shifter is configured to translate a voltage level of the data output signal {“changes from the maximum value or from the minimum value”, see Fig. 45, Col 61, lines 53-56} from the second voltage domain to the first voltage domain {“a shift operation is carried out in the shift register”, see Fig. 45, Col 61, lines 55-57}.
As per claim 16, the rejection of claim 8 is incorporated and Ooishi discloses a data storage device comprising the serial interface of claim 8 {data storage device “structure of input/output buffer circuit 7 of FIG. 1.” (Col 12, lines 64-65) including serial interface “interface circuit 10 includes a serial/parallel conversion circuit 10w” (see Fig. 5, Col 13, lines 29-31).}.
Referring to claim 17 is a method claim reciting claim functionality corresponding to the device claim of claim 8, thereby rejected under the same rationale as claim 8 recited above.
As per claim 18, the rejection of claim 17 is incorporated and Ooishi discloses further comprising:
receiving, at a data output voltage level shifter of the I/O cell {“Bi-directional shift registers FSR and CSR have”, Col 61, lines 40-42}, the data output signal from the control logic of the target device {“carrying out a shift operation according to control signal CTL”, see Figs. 69 and 45, Col 61, lines 29-31};
translating, with the data output voltage level shifter, a voltage level of the data output signal {“changes from the maximum value or from the minimum value”, see Fig. 45, Col 61, lines 53-56} from a second voltage domain of the control logic {“In the structure of the second shift sequence [voltage domain]”, see Fig. 45, Col 61, lines 57-58} to a first voltage domain of the flip-flop {“a shift operation is carried out in the shift register”, see Fig. 45, Col 61, lines 55-57}; and transmitting the data output signal from the data output voltage level shifter to the flip-flop {“operation mode designating signal”, see Fig. 82, Col 2, line 42}.
Claims 3, 4, 13, 19, and 20 are rejected 35 U.S.C. 103 as being unpatentable over OOISHI in view of Ryan and further in view of Raychowdhury further in view of Johnson et al. (US Pat No. 12148446 B1, hereinafter referred to as Johnson).
As per claim 3, the rejection of claim 2 is incorporated however neither one of the group consisting of Ooishi, Ryan, and Raychowdhury appears to explicitly disclose any limitation in this dependent claim.
Furthermore, Johnson discloses wherein the first voltage domain is from 0V to 1.8V {“regulate [a voltage domain] voltages up to a third threshold (e.g., +1.8V PLR for the serial flash).”, see Fig. 2a, Col 6, lines 63-65} and the second voltage domain is from 0V to 0.8V {“a second operating range (e.g., a +1V PSR for the main logic circuit in the SoC”, see Fig. 2a, Col 6, lines 56-57}.
Ooishi/Ryan/Raychowdhury and Johnson are analogous because they are from the same field of endeavor, serial data processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ooishi/Ryan/Raychowdhury and Johnson before him or her, to modify Ooishi/Ryan/Raychowdhury’s system incorporating Johnson’s “disk and a control circuitry” (see Fig. 2a, Col 5, lines 38-42).
The suggestion/motivation for doing so would have been to implement a minimum switching frequency may be employed such that the switching frequency of the regulator is equal to or greater than the resonance frequency of the RV sensor along with the output of the switching regulator may be shorted to ground to achieve a threshold minimum switching frequency, which can lead to power losses that adversely impact disk drive performance (Johnson Col 2, lines 20-26 paraphrased).
Therefore, it would have been obvious to combine Johnson with Ooishi/Ryan/Raychowdhury to obtain the invention as specified in the instant claim(s).
As per claim 4, the rejection of claim 2 is incorporated however neither one of the group consisting of Ooishi, Ryan, and Raychowdhury appears to explicitly disclose any limitation in this dependent claim.
Furthermore, Johnson discloses wherein the I/O cell further comprises: a clock voltage level shifter configured to be coupled {“PLSI 513”, see Fig. 5, Col 14, lines 15-19} between the clock input buffer {“timer 599”, see Figs. 3 and 4, Col 14, lines 47-53} and the control logic of the target device {“comprises [control] logic circuitry 505-a”, see Figs. 5 and 6, Col 15, lines 18-21}, wherein the clock voltage level shifter is further configured to translate a voltage level of the clock signal {“magnitude of the voltage rating of the NSR”, see Fig. 6, Col 15, lines 22-26} from the first voltage domain to the second voltage domain {“nBSR may have a voltage rating of −18V, while the NSR [translating to] may have a voltage rating of −3V”, see Fig. 6, Col 15, lines 25-28}.
The 103 motivation for this dependent claim relied upon as recited in claim 3.
As per claim 13, the rejection of claim 12 is incorporated however neither one of the group consisting of Ooishi, Ryan, and Raychowdhury appears to explicitly disclose any limitation in this dependent claim.
Furthermore, Johnson discloses wherein the |/O cell further comprises:
a clock voltage level shifter coupled {“PLSI 513”, see Fig. 5, Col 14, lines 15-19} between the clock input buffer {“timer 599”, see Figs. 3 and 4, Col 14, lines 47-53} and the control logic of the target device {“comprises [control] logic circuitry 505-a ”, see Figs. 5 and 6, Col 15, lines 18-21} and configured to translate a voltage level of the clock signal {“magnitude of the voltage rating of the NSR”, see Fig. 6, Col 15, lines 22-26} from the first voltage domain to the second voltage domain {“nBSR may have a voltage rating of −18V, while the NSR [translating to] may have a voltage rating of −3V”, see Fig. 6, Col 15, lines 25-28}.
The 103 motivation for this dependent claim relied upon as recited in claim 3.
As per claim 19, the rejection of claim 18 is incorporated however neither one of the group consisting of Ooishi, Ryan, and Raychowdhury appears to explicitly disclose any limitation in this dependent claim.
Furthermore, Johnson discloses wherein the first voltage domain is an I/O voltage domain from 0V to 1.8V {“regulate [a voltage domain] voltages up to a third threshold (e.g., +1.8V PLR for the serial flash).”, see Fig. 2a, Col 6, lines 63-65}, and the second voltage domain is a digital core voltage domain from 0V to 1.8V {“a second operating range (e.g., a +1V PSR for the main logic circuit in the SoC”, see Fig. 2a, Col 6, lines 56-57}.
The 103 motivation for this dependent claim relied upon as recited in claim 3.
As per claim 20, the rejection of claim 18 is incorporated however neither one of the group consisting of Ooishi, Ryan, and Raychowdhury appears to explicitly disclose any limitation in this dependent claim.
Furthermore, Johnson discloses further comprises:
receiving, at a clock voltage level shifter of the I/O cell {“PLSI 513”, see Fig. 5, Col 14, lines 15-19}, the clock signal from the clock input buffer {“timer 599”, see Figs. 3 and 4, Col 14, lines 47-53};
translating, with the clock voltage level shifter, a voltage level of the clock signal {“nBSR may have a voltage rating of −18V, while the NSR [translating to] may have a voltage rating of −3V”, see Fig. 6, Col 15, lines 25-28} from the first voltage domain to the second voltage domain {“magnitude of the voltage rating of the NSR”, see Fig. 6, Col 15, lines 22-26}; and transmitting the clock signal from the clock voltage level shifter {“comprises [control] logic circuitry 505-a”, see Figs. 5 and 6, Col 15, lines 18-21} to a clock tree of the target device {clock tree “actuator arm assemblies and primary actuators besides the one actuator assembly 19 and the one primary actuator 20 in the example of FIGS. 2A and 2B, and other numbers of fine actuators on each actuator” (Col 9, lines 4-7).
The 103 motivation for this dependent claim relied upon as recited in claim 3.
Claims 5, 6, 14, and 15 are rejected 35 U.S.C. 103 as being unpatentable over OOISHI in view of Ryan and further in view of Raychowdhury further in view of Johnson and further in view of Colombo et al. (USPGPUB No. 2022/0308645 A1, hereinafter referred to as Colombo).
As per claim 5, the rejection of claim 4 is incorporated however neither one from the group consisting of Ooishi, Ryan, Raychowdhury, and Johnson appears to explicitly disclose any limitation in this dependent claim.
Additionally, Colombo discloses wherein the I/O cell further comprises:
a data input buffer coupled to the data pad {“pin/pad circuitry 30”, see Figs. 3 and 8, [0138]}, wherein the data pad is further configured to receive a data input signal from the initiator device {“a comparator or preferably a Schmitt trigger 308 configured to set the value of the signal IN by comparing the voltage at the pin P with at least one [data input signal] threshold value”, see Fig. 8 [0141]};
and a data input voltage level shifter configured to be coupled {“pull-up resistor RPU and/or the pull-down resistor RPD may be selectively enabled as a function of a signal PU_EN and a signal PD_EN,”, see Fig. 8 [0146], 2nd sentence} between the data input buffer and the control logic of the target device {“[control logic] reset management circuit 116a is”, see Fig. 7 [0136] 1st sentence}, wherein the data input voltage level shifter is configured to translate a voltage level of the data input signal {“one or more analog-to-digital converters AD and/or digital-to-analog converters DA”, see Figs. 1 and 2 [0011]} from the first voltage domain to the second voltage domain {“pull-down resistor RPD will [translate] set the voltage at the input of the input stage IS to a low level”, see Fig. 8 [0149]}.
Ooishi/Ryan/Johnson/Raychowdhury and Colombo are analogous because they are from the same field of endeavor, serial data processing.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ooishi/Ryan/Johnson/Raychowdhury and Colombo before him or her, to modify Ooishi/Ryan/Johnson’s system incorporating Colombo’s “pin/pad circuitry 30” (see Figs. 3 and 8).
The suggestion/motivation for doing so would have been to implement a strong pull-up or pull-down has a lower resistance value and thus requires a higher current which causes the change of the logic level of the signal IN will be faster, because the impedance (determined by the pad resistance and parasitic capacitance) is small (Colombo [0153] paraphrased).
Therefore, it would have been obvious to combine Colombo with Ooishi/Ryan/Johnson/Raychowdhury to obtain the invention as specified in the instant claim(s).
As per claim 6, the rejection of claim 5 is incorporated and Colombo discloses wherein the data output buffer and the data input buffer are tri-state buffers {“output stage OS may comprise a tristate driver/buffer circuit 300”, see Fig. 8 [0139]}.
As per claim 14, the rejection of claim 13 is incorporated however neither one from the group consisting of Ooishi, Ryan, Raychowdhury, and Johnson appears to explicitly disclose any limitation in this dependent claim.
Additionally, Colombo discloses wherein the I/O cell further comprises:
a data input buffer coupled to the data pad {“pin/pad circuitry 30”, see Figs. 3 and 8, [0138]}, wherein the data pad is further configured to receive a data input signal from the initiator device {“a comparator or preferably a Schmitt trigger 308 configured to set the value of the signal IN by comparing the voltage at the pin P with at least one [data input signal] threshold value”, see Fig. 8 [0141]}; and a data input voltage level shifter coupled {“pull-up resistor RPU and/or the pull-down resistor RPD may be selectively enabled as a function of a signal PU_EN and a signal PD_EN,”, see Fig. 8 [0146], 2nd sentence} between the data input buffer and the control logic of the target device {“[control logic] reset management circuit 116a is”, see Fig. 7 [0136] 1st sentence}, wherein the data input voltage level shifter is configured to translate a voltage level of the data input signal {“one or more analog-to-digital converters AD and/or digital-to-analog converters DA”, see Figs. 1 and 2 [0011]} from the first voltage domain to the second voltage domain {“pull-down resistor RPD will [translate] set the voltage at the input of the input stage IS to a low level”, see Fig. 8 [0149]}.
The 103 motivation for this dependent claim relied upon as recited in claim 5.
As per claim 15, the rejection of claim 14 is incorporated and Colombo discloses wherein the data output buffer and the data input buffer are tri-state buffers {“output stage OS may comprise a tristate driver/buffer circuit 300”, see Fig. 8 [0139]}.
Response to Arguments
Applicant’s arguments filed on 12/09/2025 have been considered but deemed moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative the current state of the art regarding claim 1’s “serial data”, “I/O cell”, or “target device”: US 12373381 B1, US 20250053190 A1, US 20240429902 A1, US 20110264436 A1, US 20060290385 A1, and US 6487648 B1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
Prosecution Insights