DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the recited limitations such as “wherein the NTC thermistor is configured to: sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor.” (emphasis added), as recited in claim 1; “the NTC thermistor is configured to reduce the gate resistance until the junction temperature is reduced below the threshold level.”, as recited in claim 2; “the NTC thermistor is configured to increase the gate resistance based on a reduced current load associated with the gate drive voltage.”, as recited in claim 4; “sensing, via the NTC thermistor, a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing, via the NTC thermistor, a gate resistance of the linear gate resistor”, as recited in claim 11, “when the junction temperature meets or exceeds a threshold level, reducing, via the negative temperature coefficient thermistor, a gate resistance of the linear gate resistor, includes: reducing the gate resistance based on an inverse linear relationship with an increase in the sensed junction temperature.”, as recited in claim 12; “when the junction temperature meets or exceeds a threshold level, reducing, via the NTC thermistor, a gate resistance of the linear gate resistor, includes: when the junction temperature meets or exceeds a threshold level, reducing the gate resistance until the junction temperature is reduced below the threshold level.”, as recited in claim 13; and “increasing, via the NTC thermistor, the gate resistance based on a reduced current load associated with the gate drive voltage.”, as recited in claim 14; are not supported by the disclosure. There is nothing in the disclosure describing/supporting the above recited limitations. Correction and/or clarification is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claimed limitation such as “wherein the NTC thermistor is configured to: sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor.” (emphasis added), in the base claim 1, is not described in the specification. There is no written description in the specification that properly described how the NTC thermistor can perform the claimed function such as “sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor”. Since there is no detail discloses the operation of the NTC thermistor (410 in instant Fig. 4), the specification does not provide a disclosure of corresponding structure in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. Furthermore, the claimed limitations of claims 2 and 4 have the same issues. Correction and/or clarification is required and no new matter should be entered.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claimed limitation such as “wherein the NTC thermistor is configured to: sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor.” (emphasis added), in the base claim 1, is not described in the specification. The details of such claimed functions are not seen in the description of the preferred embodiment. For example, it is not clear how the NTC thermistor (410 in instant Fig. 4) can sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor. Therefore, it is not clear as currently defined, how the NTC thermistor can perform that recited function. Note that one of ordinary skill in the art would understand that a basic function of the NTC thermistor is to decrease its resistance as temperature increases and to increase its resistance as temperature decreases rather than as claimed “sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor” in the base claim 1. Furthermore, the claimed limitations of claims 2 and 4 have the same issues. Correction and/or clarification is required and no new matter should be entered.
Claims 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claimed limitation such as “sensing, via the NTC thermistor, a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing, via the NTC thermistor, a gate resistance of the linear gate resistor.”, in the base claim 11, is not described in the specification. There is no written description in the specification that properly described how the NTC thermistor (410 in instant Fig. 4) can perform the claimed function such as “sensing a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing a gate resistance of the linear gate resistor”. Since there is no detail discloses the operation of the NTC thermistor, the specification does not provide a disclosure of corresponding structure in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. Note that these method limitations correspond to the apparatus limitations in claim 1 discussed in section 6 above. Furthermore, the claimed limitations of claims 12-14 have the same issues. Correction and/or clarification is required and no new matter should be entered.
Claims 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claimed limitation such as “sensing, via the NTC thermistor, a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing, via the NTC thermistor, a gate resistance of the linear gate resistor.” in the base claim 11, is not described in the specification. The details of such claimed functions are not seen in the description of the preferred embodiment. For example, it is not clear how the NTC thermistor (410 in instant Fig. 4) can operate the claimed functions such as “sensing a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing a gate resistance of the linear gate resistor”. Therefore, it is not clear as currently defined, how the NTC thermistor can perform those recited functions. Note that one of ordinary skill in the art would understand that a basic function of the NTC thermistor is to decrease its resistance as temperature increases and to increase its resistance as temperature decreases rather than as claimed “sensing a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing a gate resistance of the linear gate resistor” in the base claim 11. Note that these method limitations correspond to the apparatus limitations in claim 1 discussed in section 7 above. Furthermore, the claimed limitations of claims 12-14 have the same issues. Correction and/or clarification is required and no new matter should be entered.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is indefinite because the limitation “at least one semiconductor switch configured to supply a gate drive voltage to the semiconductor device in response to a control signal received from a control switch, the at least one semiconductor switch associated with: a radiated emissions limit; and a junction temperature” (emphasis added) is misdescriptive. It is misdescriptive because Claim 1 defines that the one semiconductor switch is associated with radiated emissions limit and junction temperature. However, in the claim, the at least one semiconductor switch is defined as the element providing the gate drive voltage, thereby corresponding to transistors Q1 and Q2 of the embodiment of Fig. 4. Based on the description, it is rather understood that the radiated emission limit and the junction temperature rather apply to the semiconductor device (406, fig. 4) and not to the semiconductor switch (Q1, Q2, fig. 4) as claimed. Furthermore, Claims 2-10 are rejected due to their dependencies on the base claim 1.
Claim 11 is indefinite because the limitation “the semiconductor switch configured for supplying a gate drive voltage to the semiconductor device in response to a control signal received from the control switch, the semiconductor switch associated with a radiated emissions limit and a junction temperature,” is misdescriptive, see the above discussion with regard to Claim 1, see section 12.
Note that Claims 11-20 are associated method claims and they correspond to the recited apparatus of Claims 1-10. Furthermore, Claims 12-20 are rejected due to their dependencies on the base claim 11.
Claim 1 is indefinite because the claimed limitation such as “wherein the NTC thermistor is configured to: sense a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reduce one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by reducing a gate resistance of the linear gate resistor.” (emphasis added), in the base claim 1, is unclear. For example, one of ordinary skill in the art would understand that a basic function of the NTC thermistor is to decrease its resistance as temperature increases and to increase its resistance as temperature decreases, thus it is unclear how the NTC thermistor can perform the above claimed functions. Therefore, the base claim 1 is indefinite and claims 2-10 are rejected due to their dependencies on the base claim 1.
Furthermore, the claimed limitations of claims 2 and 4 have the same issues.
Claim 11 is indefinite because the claimed limitation such as “sensing, via the NTC thermistor, a junction temperature associated with at least one of the on state or the off state; and when the junction temperature meets or exceeds a threshold level, reducing, via the NTC thermistor, a gate resistance of the linear gate resistor.” (emphasis added) is unclear, see the above discussion with regard to Claim 1 (section 14). Note that Claims 11-20 are associated method claims and they correspond to the recited apparatus of Claims 1-10. Claims 12-20 are rejected due to their dependencies on the base claim 11.
Furthermore, the claimed limitations of claims 12-14 have the same issues.
Claim 11 is indefinite because the limitation "a semiconductor device ", in line 8, lacks clear antecedent basis. It is unclear if the limitation is referring to previously recited semiconductor device in line 1 of the claim, or introducing another semiconductor device. It appears that they are the same. Appropriate correction and/or clarification is required. Furthermore, claims 12-20 are rejected due to their dependencies on the base claim 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-17, 19 and 20, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0021102, IDS, hereinafter referred to as Kim).
With regard to claim 1, Kim discloses (see Fig. 12) a gate drive circuit for a semiconductor device comprising at least one semiconductor switch (inherent in the driver 140) configured to supply a gate drive voltage (output of driver 140) to the semiconductor device in response to a control signal received from a control switch (inherent), the at least one semiconductor device (Claim 1 defines that the one semiconductor switch is associated with radiated emissions limit and junction temperature. However, in the claim, the at least one semiconductor switch is defined as the element providing the gate drive voltage, thereby corresponding to transistors Q1 and Q2 of the embodiment of Fig. 4. Based on the description, it is rather understood that the radiated emission limit and the junction temperature rather apply to the semiconductor device (406, fig. 4) and not to the semiconductor switch (Q1, Q2, fig. 4) as claimed) associated with a radiated emissions limit (inherent); and a junction temperature (inherent); wherein the gate drive voltage is one of: a positive voltage (see the high output voltage of 140, fig. 1) corresponding to an on state, the on state associated with at least one of a turn-on switching timing or a turn-on switching loss (inherent, any electronic switch causes switching losses); and a non-positive voltage (see the low output voltage of 140, fig. 1, which is necessarily a zero voltage or a negative voltage) corresponding to an off state, the off state associated with at least one of a turn-off switching timing or a turn-off switching loss (inherent, any electronic switch causes switching losses); and a gate resistance device serially connected between the at least one semiconductor switch and the at least one semiconductor device (see sections 12-13 above}, the gate resistance device thermally coupled to the at least one semiconductor device (see sections 12-13 above), the gate resistance device comprising a negative temperature coefficient "NTC" thermistor (161) and a linear gate resistor (Rg) connected in parallel (see fig. 12); wherein the NTC thermistor is configured to: sense a junction temperature associated with at least one of the on state or the off state (inherent, see also [0068] and [0130]); and when the junction temperature meets or exceeds a threshold level (as the resistance varies in a continuous manner in a thermistor, any arbitrary temperature can be considered as a threshold temperature from which the resistance varies, regardless of the resistance variations below this temperature), reduce one or more of the associated turn-on or tum-off switching timing or the associated urn-on or turn-off switching loss by reducing a gate resistance of the linear (the resistor in parallel with the NTC thermistor is defined as a linear gate resistor. The term linear is unclear since it is not clear with which parameter the resistance of the linear gale resistor varies in a linear manner. Furthermore, this feature does not appear to be supported by the description, since the description defines this element as having a fixed resistance with temperature (see e.g. fig. 5A). In this ESOP, the term linear is ignored for assessing novelty/inventive step) gate resistor (the arrangement is the same as in the present application, therefore, the decrease of the gate resistance when the temperature of the semiconductor device increases will have the same effect as in the present application, namely to decrease switching time and switching losses. see also [0131]).
With regard to claim 2, wherein the NTC thermistor (410 in Fig. 4) is configured to reduce the gate resistance until the junction temperature is reduced below the threshold level.
With regard to claim 3, wherein the NTC thermistor (410 in Fig. 4) is configured to reduce the gate resistance based on an inverse linear relationship with an increase in the sensed junction temperature.
With regard to claim 4, wherein the NTC thermistor (410 in Fig. 4) is configured to increase the gate resistance based on a reduced current load associated with the gate drive voltage.
With regard to claim 5, wherein the NTC thermistor (410 in Fig. 4) is configured to increase the gate resistance based on a reduction in the sensed junction temperature.
With regard to claim 6, wherein the linear gate resistor (Rg) is associated with: a minimum gate resistance corresponding to the radiated emissions limit; and a maximum gate resistance based on a power capacity of the semiconductor switch.
With regard to claim 7, wherein the at least one semiconductor switch includes at least one insulated gate bipolar transistor, IGBT (see [0083]).
With regard to claim 9, wherein the turn-on switching timing includes at least one of: a turn-on delay associated with the on state; a rise time associated with the on state; or a charging time associated with the on state.
With regard to claim 10, wherein the turn-off switching timing includes at least one of: a turn-off delay associated with the off state; a fall time associated with the off state; and a discharging time associated with the off state.
With regard to claim 11, all limitations of the present claim are likewise anticipated by Kim. The method limitations recited herein are implicitly disclosed by the gate-drive circuit previously addressed in connection with claim 1; see Section 19.
With regard to claim 12, wherein when the junction temperature meets or exceeds a threshold level, reducing, via the negative temperature coefficient thermistor, a gate resistance of the linear gate resistor, includes: reducing the gate resistance based on an inverse linear relationship with an increase in the sensed junction temperature.
With regard to claim 13, wherein when the junction temperature meets or exceeds a threshold level, reducing, via the NTC thermistor, a gate resistance of the linear gate resistor, includes: when the junction temperature meets or exceeds a threshold level, reducing the gate resistance until the junction temperature is reduced below the threshold level.
With regard to claim 14, the method further comprises increasing, via the NTC thermistor, the gate resistance based on a reduced current load associated with the gate drive voltage.
With regard to claim 15, the method further comprises increasing, via the NTC thermistor, the gate resistance based on a reduction in the sensed junction temperature.
With regard to claim 16, wherein the linear gate resistor is associated with: a minimum gate resistance corresponding to the radiated emissions limit; and a maximum gate resistance based on a power capacity of the semiconductor switch.
With regard to claim 17, wherein the semiconductor switch is an insulated gate bipolar transistor, IGBT (see [0083]).
With regard to claim 19, wherein the turn-on switching timing includes at least one of: a turn-on delay associated with the on state; a rise time associated with the on state; or a charging time associated with the on state.
With regard to claim 20, wherein the turn-off switching timing includes at least one of: a turn-off delay associated with the off state; a fall time associated with the off state; or a discharging time associated with the off state.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 and 18, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
With regard to claim 8, as discussed above with regard to claim 1, Fig. 12 of Kim shows a gate drive circuit for a semiconductor device meeting all of the recited elements of the claimed gate drive circuit for a semiconductor device, except for not disclosing the semiconductor device is a system-on-a-chip, SoC; and the at least one semiconductor switch and the gate resistance device includes at least one surface-mounted device, SMD. It is notoriously well known in the art that the system on a chip (SoC) is an integrated circuit combines all of a system’s essential components onto a single piece of silicon, eliminating the need for separate, bulky system parts. This integration simplifies circuit board design and delivers improved power efficiency and speed without compromising functionality. SMD refers to electronic components that are designed to be mounted directly onto the surface of a printed circuit board (PCB), without the need for drilling holes. This mounting technique eliminates the need for drilling holes, making the assembly process more efficient and enabling the production of smaller, lighter, and more densely packed electronic devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to integrate these designed technique into the circuit described in Kim in order to reduce the size of the circuit and consume lesser energy.
Claim 18 is unpatentable over Kim for the same reasons addressed with respect to claim 8, as the reasoning applied to the subject-matter of claim 8 applies, mutatis mutandis, to the corresponding independent method claim 18.
Conclusion
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/HAI L NGUYEN/Primary Examiner, Art Unit 2842 December 15, 2025