DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kehl et al. (US 2022/0399290 A1).
In regard to claim 1, Kehl teaches a stacked assembly (a multi-level package 700) (Fig. 7A and paragraph 30), comprising:
a first semiconductor die (a ring frame 104, and a circuit die 110 supported by a base die 106 in a second level 154) (Fig. 1A, Fig. 1B, and paragraphs 27 and 31);
a second semiconductor die secured to the first semiconductor die (a ring frame 104, circuit die 110 having supported by a base die 106 in a first level 152) (Fig. 1A, Fig. 1B, and paragraphs 27 and 31); and
a dielectric encasing (edge caps 702) at least the second semiconductor die (the edge caps 702 contact conductive materials the examiner takes official notice that the edge caps 702 must be dielectric in order for the device to function) (Fig. 7A, Fig. 7B and paragraphs 59-60), wherein the dielectric defines a cooling channel (channels 706) having at least one inlet (a fluid input port 704) and at least one outlet (a fluid output port 708) (Fig. 7A and paragraph 60), and wherein the cooling channel is configured to direct cooling fluid to at least the second semiconductor die (the channels 706 can be configured to enhance cooling at certain die locations) (Fig. 7C and paragraph 61).
In regard to claim 2, Kehl teaches wherein the cooling channel is defined within the dielectric (the cooling channels are shown in the edge caps 702 in Fig. 7B).
In regard to claim 3, Kehl teaches further comprising a cooling fluid mover coupled to at least one of the at least one inlet and the at least one outlet (as the fluid input port 704 can receive coolant that can flow through channels 706, the examiner takes official notice that there must be an attached fluid mover to the fluid input port 704) (paragraph 60).
In regard to claim 4, Kehl teaches further comprising cooling fluid (coolant) in the cooling channel and the fluid mover (as the fluid input port 704 can receive coolant that can flow through channels 706, the examiner takes official notice that there must be cooling fluid in the cooling channel and the fluid mover) (paragraph 60).
In regard to claim 5, Kehl teaches wherein the first semiconductor die comprises a logic die and the second semiconductor die comprises a memory die (a first level 152 can comprise a memory die, and a second level 154 can comprise an FPGA die) (paragraph 31).
In regard to claim 6, Kehl teaches wherein the logic die and the memory die are bonded together using at least metal bond pads (pads 212) on each of the logic die and the memory die (the ring frame 104 and circuit die 110 supported by a base die 106 on the first and second level 152 and 154 are shown bonded by pads 212 and solder bumps 219 in Fig. 1B) (Fig. 1b, Fig. 2B and paragraphs 34-35).
In regard to claim 7, Kehl teaches wherein the logic die and the memory die are bonded together using hybrid bonding (as shown in Fig. 1B, the ring frame 204 formed of silicon and the dies are bonded using solder 219) (Fig. 2B and paragraphs 34-35), further comprising through-silicon vias (vias 202 are through silicon vias (TSV)) extending from at least some of the metal bond pads on the memory die through the memory die (the pads 212 on the base die 214 are shown with TSVs 202 through the portion of the die containing the ring frame 204) (Fig. 2B, Fig. 2C and paragraphs 32-34).
In regard to claim 14, Kehl teaches further comprising a lid (a lid as shown in annotated Fig. 7C) surrounding the first and second semiconductor dies (annotated Fig. 7C), wherein the cooling channel passes through the lid (the fluid channels 706 are shown in the lid in Fig. 7C).
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In regard to claim 15, Kehl teaches wherein a first side of the second semiconductor die is secured to the first semiconductor die and wherein the cooling channel is further configured to direct cooling fluid to a second side of the second semiconductor die opposite the first side of the second semiconductor die (as the bottom side of the ring frame 104 and, circuit die 110 supported by a base die 106 in a first level 152 is secured to the ring frame 104 and, circuit die 110 supported by a base die 106 in a second level 154, the cooling channels on the top would be on the second side of the elements mapped as the second semiconductor die) (Fig. 7C).
In regard to claim 16, Kehl teaches wherein the cooling channel is configured with a plurality of main portions perpendicular to the second semiconductor die and a plurality of secondary portions transverse to the main portions (as shown in Fig. 7C the fluid channels 706 completely surround the device and the ring frame 104 and, circuit die 110 supported by a base die 106 in a first level 152 while being connected to each other, therefore, there are fluid channels 706 with a plurality of main portions perpendicular to the second semiconductor die and a plurality of secondary portions transverse to the main portions) (Fig. 7C).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kehl et al. (US 2022/0399290 A1) as applied to claim 7, and further in view of Tong et al. (US 20240421027 A1; hereinafter “Tong”).
In regard to claim 8, Kehl doesn’t explicitly teach further comprising a laminate soldered to the through-silicon vias using solder bumps.
Tong teaches a stacked assembly (a semiconductor package 70A) (Fig. 7 and paragraph 169), comprising a laminate (a first substrate 210) soldered to through-silicon vias (through vias 256) using solder bumps (connector 262) (Fig. 28E and paragraph 169).
It would be obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Tong to have a laminate soldered to the through-silicon vias using solder bumps since this allows for a device with increased heat dissipation capability taught by Tong (paragraph 174).
In regard to claim 9, Kehl doesn’t explicitly teach further comprising an underfill between the memory die and the laminate.
Tong teaches further comprising an underfill (the dielectric layer 270) between a memory die (memory die 252) and the laminate (Fig. 28E, paragraphs 172 and 174).
It would’ve been obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Tong to have an underfill between the memory die and the laminate since this allows for unwanted short protection of exposed surfaces of the device as taught by Tong (paragraph 175).
In regard to claim 10, Kehl teaches wherein the logic die extends horizontally beyond the memory die (the circuit die 110 on the second level 154 is shown extending past the circuit die 110 on the first level 152 in Fig. 1A and Fig. 1B).
Kehl doesn’t explicitly teach further comprising peripheral through-device vias interconnecting the logic die and the laminate outward of a periphery of the memory die.
Tong teaches further comprising peripheral through-device vias (vias 256 in the interposer 230 in the periphery of the memory die 252 as shown in annotated Fig. 28E) interconnecting a logic die (a processor die 2202) and the laminate outward of a periphery of the memory die (as shown in Fig. 28E, the vias 256 in the interposer 230 interconnect the processor die 2202 and the substrate 210 in the periphery of the memory die 252) (Fig. 28E and paragraph 185).
It would’ve been obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Tong to have through-device vias interconnecting the logic die and the laminate outward of a periphery of the memory die, as this allows for electrical connections to occur while providing heat dissipation within the device as taught by Tong (paragraphs 171 and 174).
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Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kehl et al. (US 2022/0399290 A1) as applied to claim 4, and further in view of Chainer (US 2017/0186728 A1).
In regard to claim 11, Kehl doesn’t explicitly teach wherein the cooling fluid is selected from the group consisting of air, helium, and nitrogen, and wherein the fluid mover is selected from the group consisting of a fan and a blower.
Chainer teaches a stacked assembly (a chip stack 800) (Fig. 8 and paragraph 73), wherein the cooling fluid is selected from the group consisting of air, helium, and nitrogen (gas coolants such as air, nitrogen, helium, or mixtures of these and other gases may be used instead of liquid coolants) (paragraph 72), and wherein the fluid mover is selected from the group consisting of a fan and a blower (to achieve comparable cooling with a gas coolant high speed jets may be required which are known to comprise fans and blowers) (paragraph 72).
It would’ve been obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Chainer to have the cooling fluid selected from the group consisting of air, helium, and nitrogen, and wherein the fluid mover is selected from the group consisting of a fan and a blower since using a gas coolant reduces the chance of material corrosion as taught by Chainer (paragraph 72).
In regard to claim 12, Kehl doesn’t explicitly teach wherein the cooling fluid includes water and wherein the fluid mover comprises a pump.
Chainer teaches wherein the cooling fluid includes water and wherein the fluid mover comprises a pump (liquid coolants may be utilized such as water, and as each microchannel cooler 620 has its own inlet/outlet for fluid coolant to circulate through the microchannel coolers 620, the examiner takes official notice that there must be a pump in order for the water to circulate throughout the device) (paragraphs 53 and 72).
It would’ve been obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Chainer to have the cooling fluid includes water and wherein the fluid mover comprises a pump since water is a known coolant with increased thermal conductivity when compared to other materials as taught by Chainer (paragraph 72).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kehl et al. (US 2022/0399290 A1) as applied to claim 4, and further in view of Or-Bach et al. (US 2023/0187397 A1; hereinafter “Or-Bach”).
In regard to claim 13, Kehl doesn’t explicitly teach wherein the dielectric is selected from the group consisting of silicon oxide, silicon nitride, epoxy compound, and molding compound.
Or-Bach teaches a stacked assembly (cooled 3D device 4001) (Fig. 40B and paragraph 297), wherein a dielectric (a material of a micro-channel 4016) is selected from the group consisting of silicon oxide, silicon nitride, epoxy compound, and molding compound (the inner surface of the micro-channel 4016 may be further protected by silicon nitride) (Fig. 40B and paragraph 297).
It would’ve been obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Or-Bach to have the dielectric selected from the group consisting of silicon oxide, silicon nitride, epoxy compound, and molding compound since this provides increased protection from coolant fluid as taught by Or-Bach (paragraph 297).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kehl et al. (US 2022/0399290 A1) as applied to claim 1, and further in view of Haba et al. (US 2025/0253208 A1; hereinafter “Haba”).
In regard to claim 17, Kehl doesn’t explicitly teach wherein the dielectric resides on only an upper side of the cooling channel.
Haba teaches a stacked assembly (a plurality of device packages 201) wherein a dielectric (a manifold 210) resides on only an upper side of a cooling channel (the manifold is shown on the upper sides of coolant channels 226) (Fig. 2 and paragraphs 57 and 67).
It would’ve been obvious to one skilled in the art to combine the teachings of Kehl with the teachings of Haba to have the dielectric reside on only an upper side of the cooling channel since this allows direct cooling to the devices which increase cooling efficiency as taught by Haba (paragraphs 4 and 69).
Allowable Subject Matter
Claims 18-20 are allowed.
The following is the Office's statement of reasons for allowance:
Regarding claims 18, the prior art of record, taken alone or in combination, fails to teach or suggest:
“depositing a sacrificial layer in the at least one cooling channel; forming a layer of ultraviolet-transparent material above the at least one cooling channel; applying ultraviolet radiation to the sacrificial layer through the layer of ultraviolet-transparent material to cause gasification and removal of the sacrificial material; and depositing a second dielectric layer outward of the layer of ultraviolet-transparent material to at least partially enclose the at least one cooling channel, to produce a second assembly”.
Kehl is considered a close prior art of record. However, Kehl fails to teach, depositing a sacrificial layer in the at least one cooling channel; forming a layer of ultraviolet-transparent material above the at least one cooling channel; applying ultraviolet radiation to the sacrificial layer through the layer of ultraviolet-transparent material to cause gasification and removal of the sacrificial material; and depositing a second dielectric layer outward of the layer of ultraviolet-transparent material to at least partially enclose the at least one cooling channel, to produce a second assembly. Kehl is silent regarding any masking or irradiation techniques used if the formation of the cooling channels.
Tong is considered a close prior art of record. However, Tong fails to teach, depositing a sacrificial layer in the at least one cooling channel; forming a layer of ultraviolet-transparent material above the at least one cooling channel; applying ultraviolet radiation to the sacrificial layer through the layer of ultraviolet-transparent material to cause gasification and removal of the sacrificial material; and depositing a second dielectric layer outward of the layer of ultraviolet-transparent material to at least partially enclose the at least one cooling channel, to produce a second assembly. Tong is silent regarding any masking or irradiation techniques used if the formation of the cooling channels.
Chainer is considered a close prior art of record. However, Chainer fails to teach, depositing a sacrificial layer in the at least one cooling channel; forming a layer of ultraviolet-transparent material above the at least one cooling channel; applying ultraviolet radiation to the sacrificial layer through the layer of ultraviolet-transparent material to cause gasification and removal of the sacrificial material; and depositing a second dielectric layer outward of the layer of ultraviolet-transparent material to at least partially enclose the at least one cooling channel, to produce a second assembly. Chainer is silent regarding any masking or irradiation techniques used if the formation of the cooling channels.
Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 18-20 are allowable over the prior arts of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kollipara et al. (US 2024/0194565 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893