DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Packages with Bridge Structure and Redistribution Patterns and Methods of Manufacturing the Same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, and 9-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (US 11482497).
Regarding Claim 1, Lin et al discloses a semiconductor package (package structure PKG1 [column 15, lines 20-27] Fig 2G viewed from 180 degrees) comprising:
a redistribution layer (redistribution structure RDL 120 [column 15, lines 28-40] Fig 2G viewed from 180 degrees);
a first lower post (conductive vias 110 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the redistribution layer (120 Fig 2G viewed from 180 degrees);
a second lower post (conductive vias 110 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the redistribution layer (12 Fig 2G viewed from 180 degrees) and spaced laterally apart from the first lower post (110 left Fig 2G viewed from 180 degrees);
a first upper connection post (connectors 104 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the first lower post (110 (left) Fig 2G viewed from 180 degrees);
a second upper connection post (connectors 104 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the second lower post (110 (right) Fig 2G viewed from 180 degrees);
a bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) on the redistribution layer (120 Fig 2G viewed from 180 degrees) and between the first lower post (110 (left) Fig 2G viewed from 180 degrees) and the second lower post (110 (right) Fig 2G viewed from 180 degrees);
a semiconductor device (die 100 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the first upper connection post (104 (left) Fig 2G viewed from 180 degrees) and a first area (shown in annotated Fig 2G viewed from 180 degrees) of the bridge structure (19, 26, and structure shown in annotated Fig 2G viewed from 180 degrees);
a semiconductor chip (die 100 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the second upper connection post (104 (right) Fig 2G viewed from 180 degrees) and a second area (shown in annotated Fig 2G viewed from 180 degrees) of the bridge structure (19, 26, and structure shown in annotated Fig 2G viewed from 180 degrees) and spaced laterally apart from the semiconductor device (100 (left) Fig 2G viewed from 180 degrees); and
a lower molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown in annotated Fig 2G viewed from 180 degrees) on the redistribution layer (120 Fig 2G viewed from 180 degrees) and covering sidewalls of the first (110 (left) Fig 2G viewed from 180 degrees) and second lower posts (110 (right) Fig 2G viewed from 180 degrees) and sidewalls of the first (104 (left) Fig 2G viewed from 180 degrees) and second upper connection posts (104 (right) Fig 2G viewed from 180 degrees),
wherein the lower molding layer (116, 108, and lower portion of 106 shown in annotated Fig 2G viewed from 180 degrees) is in direct contact with a bottom surface of the semiconductor device (100 (left) Fig 2G viewed from 180 degrees) and a bottom surface of the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees).
PNG
media_image1.png
850
1200
media_image1.png
Greyscale
PNG
media_image2.png
758
1031
media_image2.png
Greyscale
Regarding Claim 2, Lin et al discloses the limitations of claim 1 as explained above. Lin et al further discloses
further comprising an upper molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees) covering a sidewall of the semiconductor device (100 (left) Fig 2G viewed from 180 degrees) and a sidewall of the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees),
wherein the lower molding layer (116, 108, and lower portion of 106 shown above in annotated Fig 2G viewed from 180 degrees) is in direct contact with a bottom surface of the upper molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees).
Regarding Claim 3, Lin et al discloses the limitations of claim 2 as explained above. Lin et al further discloses
wherein the bottom surface of the upper molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees) is coplanar with the bottom surface of the semiconductor device (100 (left) Fig 2G viewed from 180 degrees) and the bottom surface of the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees).
Regarding Claim 4, Lin et al discloses the limitations of claim 2 as explained above. Lin et al further discloses
wherein the lower molding layer (116, 108, and lower portion of 106 shown in annotated Fig 2G viewed from 180 degrees) and the upper molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees) each include a same epoxy-based molding compound (106 may include epoxy [column 9, lines 50-67]).
Regarding Claim 5, Lin et al discloses the limitations of claim 2 as explained above. Lin et al further discloses
further comprising: a first upper bridge post (conductive posts 16 (left) [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees) between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the semiconductor device (100 (left) Fig 2G viewed from 180 degrees); and
a second upper bridge post (conductive posts 16 (right) [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees) between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees),
wherein the upper molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees) is spaced apart from the first upper bridge post (16 (left) Fig 2C and Fig 2G viewed from 180 degrees) and the second upper bridge post (16 (right) Fig 2C and Fig 2G viewed from 180 degrees).
Regarding Claim 6, Lin et al discloses the limitations of claim 5 as explained above. Lin et al further discloses
wherein the lower molding layer (116, 108, and lower portion of 106 shown in annotated Fig 2G viewed from 180 degrees) extends between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees) and between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the semiconductor device (100 (left) Fig 2G viewed from 180 degrees) and covers sidewalls of the first (16 (left) Fig 2C and Fig 2G viewed from 180 degrees) and second (16 (right) Fig 2C and Fig 2G viewed from 180 degrees) upper bridge posts.
Regarding Claim 7, Lin et al discloses the limitations of claim 1 as explained above. Lin et al further discloses
wherein the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown above in annotated Fig 2G viewed from 180 degrees) comprises: bridge wires (interconnection structure 15 [column 3, lines 10-43] Fig 3A viewed from 180 degrees); and through-vias (TSV 19 Fig 2G viewed from 180 degrees) spaced apart (spaced apart vertically) from the bridge wires (15 Fig 3A viewed from 180 degrees),
wherein the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees) is electrically connected to the semiconductor device (100 (left) Fig 2G viewed from 180 degrees) through the bridge wires (15 Fig 3A viewed from 180 degrees), and
wherein the semiconductor chip (100 (right) Fig 2G viewed from 180 degrees) and the semiconductor device (100 (left) Fig 2G viewed from 180 degrees) are electrically connected to the redistribution layer (120 Fig 2G viewed from 180 degrees) through the through-vias (TSV 19 Fig 2G viewed from 180 degrees).
Regarding Claim 9, Lin et al discloses a semiconductor package (package structure PKG1 [column 15, lines 20-27] Fig 2G viewed from 180 degrees) comprising:
a first semiconductor chip (die 100 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees);
a second semiconductor chip (die 100 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) spaced laterally apart from the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees);
a first upper connection post (connectors 104 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a bottom surface of the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees) and connected to the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees);
a second upper connection post (connectors 104 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a bottom surface of the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees) and connected to the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees);
a first lower post (conductive vias 110 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a bottom surface of the first upper connection post (104 (left) Fig 2G viewed from 180 degrees);
a second lower post (conductive vias 110 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a bottom surface of the second upper connection post (104 (right) Fig 2G viewed from 180 degrees);
a bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) on the bottom surface of the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees) and the bottom surface of the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees) and spaced laterally apart from the first (110 (left) Fig 2G viewed from 180 degrees) and second lower posts (110 (right) Fig 2G viewed from 180 degrees);
a first molding layer (upper portion of encapsulant 106 column 15, lines 28-40] (shown in annotated Fig 2G viewed from 180 degrees) covering sidewalls of the first (100 (left) Fig 2G viewed from 180 degrees) and second (100 (right) Fig 2G viewed from 180 degrees) semiconductor chips and spaced apart from the first (104 (left) Fig 2G viewed from 180 degrees) and second upper connection posts (104 (right) Fig 2G viewed from 180 degrees); and
a second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown in annotated Fig 2G viewed from 180 degrees) on a bottom surface of the first molding layer (116, 108, and lower portion of 106 Fig 2G viewed from 180 degrees),
wherein the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown in annotated Fig 2G viewed from 180 degrees) covers the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees), sidewalls of the first and second lower posts (110 (left and right) Fig 2G viewed from 180 degrees), and sidewalls of the first and second upper connection posts (104 (left and right) Fig 2G viewed from 180 degrees).
PNG
media_image1.png
850
1200
media_image1.png
Greyscale
PNG
media_image3.png
623
1075
media_image3.png
Greyscale
Regarding Claim 10, Lin et al discloses the limitations of claim 9 as explained above. Lin et al further discloses
wherein the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown above in annotated Fig 2G viewed from 180 degrees) is in direct contact with the bottom surface of the first molding layer (upper portion of encapsulant 106 column 15, lines 28-40] (shown above in annotated Fig 2G viewed from 180 degrees), the bottom surface of the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees), and the bottom surface of the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees).
Regarding Claim 11, Lin et al discloses the limitations of claim 9 as explained above. Lin et al further discloses
further comprising: a first upper bridge post (conductive posts 16 (left) [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees) between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees); and
a second upper bridge post (conductive posts 16 (right) [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees) between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees),
wherein the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown above in annotated Fig 2G viewed from 180 degrees) extends onto a top surface of the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and covers sidewalls of the first (16 (left) Fig 2C and Fig 2G viewed from 180 degrees) and second upper bridge posts (16 (right) Fig 2C and Fig 2G viewed from 180 degrees).
Regarding Claim 12, Lin et al discloses the limitations of claim 11 as explained above. Lin et al further discloses
further comprising bridge solder balls (conductive cap 17 [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees) respectively provided between the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) and the first (16 (left) Fig 2C and Fig 2G viewed from 180 degrees) and second (16 (right) Fig 2C and Fig 2G viewed from 180 degrees) upper bridge posts,
wherein the bridge solder balls (17 Fig 2C and Fig 2G viewed from 180 degrees) are in direct contact with bottom surfaces of the first (16 (left) Fig 2C and Fig 2G viewed from 180 degrees) and second (16 (right) Fig 2C and Fig 2G viewed from 180 degrees) upper bridge posts, and wherein the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown above in annotated Fig 2G viewed from 180 degrees) covers sidewalls of the bridge solder balls (17 Fig 2C and Fig 2G viewed from 180 degrees).
Regarding Claim 13, Lin et al discloses the limitations of claim 9 as explained above. Lin et al further discloses
further comprising a redistribution layer (redistribution structure RDL 120 [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a bottom surface of the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown above in annotated Fig 2G viewed from 180 degrees), wherein the redistribution layer (120 Fig 2G viewed from 180 degrees) comprises: redistribution patterns (RDL1, RDL2, and RDL3 Fig 2G viewed from 180 degrees); and
seed patterns (RDL1, RDL2, and RDL3 include a seed layer (not shown) [column 15, lines 28-40]) on top surfaces of the redistribution patterns (RDL1, RDL2, and RDL3 Fig 2G viewed from 180 degrees), and wherein at least one of the seed patterns (seed pattern associated with the via V of RDL1 [column 15, lines 28-40] Fig 2G viewed from 180 degrees) is in direct contact with a bottom surface of the first lower post (110 (left) Fig 2G viewed from 180 degrees).
Regarding Claim 14, Lin et al discloses the limitations of claim 13 as explained above. Lin et al further discloses
further comprising conductive patterns (conductive via 26 [column 16, lines 28-34] Fig 2G viewed from 180 degrees) between the redistribution layer (120 Fig 2G viewed from 180 degrees) and the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown above in annotated Fig 2G viewed from 180 degrees) and electrically connected to the redistribution patterns,
wherein the bridge structure (19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees) comprises:
a base substrate (encapsulant material layer 28’ [column 6, lines 41-67] Fig 2C and Fig 2G viewed from 180 degrees);
bridge wires (interconnection structure 15 [column 3, lines 44-67] Fig 3A, and Fig 2C and Fig 2G viewed from 180 degrees) on the base substrate (28’ Fig 2C and Fig 2G viewed from 180 degrees); and
through-vias (TSV 19 Fig 2C and Fig 2G viewed from 180 degrees) that extend through the base substrate (28’ Fig 2C and Fig 2G viewed from 180 degrees) and are electrically separated from the bridge wires (15 Fig 3A, Fig 2C and Fig 2G viewed from 180 degrees), and
wherein the through-vias (TSV 19 Fig 2C and Fig 2G viewed from 180 degrees) are electrically connected to the conductive patterns (26 Fig 2G viewed from 180 degrees).
Regarding Claim 15, Lin et al discloses the limitations of claim 14 as explained above. Lin et al further discloses
wherein the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] shown above in annotated Fig 2G viewed from 180 degrees) further extends to a gap area between the redistribution layer (120 Fig 2G viewed from 180 degrees) and the bridge structure (19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees) and further covers sidewalls of the conductive patterns (26 Fig 2G viewed from 180 degrees).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 11482497) in view of GOH et al (US 2023/0395576).
Regarding Claim 8, Lin et al discloses the limitations of claim 1 as explained above. Lin et al does not disclose
wherein the semiconductor device comprises:
a first lower semiconductor chip; and
a plurality of first upper semiconductor chips stacked on the first lower semiconductor chip.
GOH et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the semiconductor device (memory die stacks 120 [0024] Fig 1) comprises: a first lower semiconductor chip (lower most memory die 122 [0024] Fig 1); and
a plurality of first upper semiconductor chips (upper 3 memory die 122 [0024] Fig 1) stacked on the first lower semiconductor chip (lower most memory die 122 Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al to include a chip stack package as taught by GOH et al in order to optimize the memory functioning capability by having a stack of memory dies [0024]. Further, a person of ordinary skill in the art would have recognized that including a stack of memory dies would be advantageous in meeting small size parameters of the device while optimizing functional capability (see MPEP 2143.I(D)).
Regarding Claim 16, Lin et al discloses the limitations of claim 9 as explained above. Lin et al does not disclose
wherein the first semiconductor chip comprises a first lower semiconductor chip, wherein the semiconductor package comprises:
a plurality of first upper semiconductor chips stacked on the first lower semiconductor chip; and an inner molding layer on a top surface of the first lower semiconductor chip and covering sidewalls of the plurality of first upper semiconductor chips, and
wherein the second semiconductor chip is a different type from the first lower semiconductor chip and the first upper semiconductor chip.
GOH et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first semiconductor chip (memory die stacks 120 [0024] Fig 1) comprises a first lower semiconductor chip (lower most memory die 122 [0024] Fig 1), wherein the semiconductor package comprises:
a plurality of first upper semiconductor chips (upper 3 memory die 122 [0024] Fig 1) stacked on the first lower semiconductor chip (lower most memory die 122 [0024] Fig 1); and
an inner molding layer (mold layer 125 [0022] Fig 1) on a top surface of the first lower semiconductor chip (lower most memory die 122 [0024] Fig 1) and covering sidewalls of the plurality of first upper semiconductor chips (upper 3 memory die 122 [0024] Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al to include a chip stack package as taught by GOH et al in order to optimize the memory functioning capability by having a stack of memory dies [0024]. Further, a person of ordinary skill in the art would have recognized that including a stack of memory dies would be advantageous in meeting small size parameters of the device while optimizing functional capability (see MPEP 2143.I(D)).
The combination of Lin et al and GOH et al now discloses
wherein the second semiconductor chip (die 100 may be a CPU unit die [column 8, lines 25-45] Fig 2G viewed from 180 degrees Lin et al) is a different type from the first lower semiconductor chip (lower most memory die 122 [0024] Fig 1 GOH et al) and the first upper semiconductor chip (second memory die 122 [0024] Fig 1 GOH et al).
Claims 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 11482497) in view of Yamagishi et al (US 2006/0197679), and Liao et al (US 10340253), and in further view of GOH et al (US 2023/0395576).
Regarding Claim 17, Lin et al discloses a semiconductor package (package structure PKG1 [column 15, lines 20-27] Fig 2G viewed from 180 degrees) comprising:
a redistribution layer (redistribution structure RDL 120 [column 15, lines 28-40] Fig 2G viewed from 180 degrees) comprising an insulating layer (polymer layers PM1, PM2, PM3 [column 14, lines 14-51] Fig 2G viewed from 180 degrees), redistribution patterns (redistribution layers RDL1, RDL2, RDL3 [column 14, lines 14-51] Fig 2G viewed from 180 degrees), seed patterns (seed layer (not shown) [column 14, lines 14-51] Fig 2G viewed from 180 degrees), and redistribution pads (RDL1 and RDL3 Fig 2G viewed from 180 degrees);
lower posts (conductive vias 110 [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a top surface of the redistribution layer (120 Fig 2G viewed from 180 degrees) and electrically connected to the redistribution patterns (RDL1, RDL2, RDL3 Fig 2G viewed from 180 degrees), the lower posts (110 Fig 2 G viewed from 180 degrees) comprising a first lower post (110 (left) Fig 2G viewed from 180 degrees) and a second lower post (110 (right) viewed from 180 degrees) spaced laterally apart from each other;
a first upper connection post (connectors 104 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the first lower post (110 (left) Fig 2G viewed from 180 degrees);
a second upper connection post (connectors 104 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the second lower post (110 (right) Fig 2G viewed from 180 degrees);
a bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown in annotated Fig 2G viewed from 180 degrees) on the top surface of the redistribution layer (120 Fig 2G viewed from 180 degrees) and between the first lower post (110 (left) Fig 2G viewed from 180 degrees) and the second lower post (110 (right) Fig 2G viewed from 180 degrees);
a first semiconductor chip (die 100 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a top surface of the first upper connection post (104 (left) fig 2G viewed from 180 degrees) and a first area (shown in annotated Fig 2G viewed from 180 degrees) of the bridge structure (TSV 19, 26, and structure shown in annotated Fig 2G viewed from 180 degrees) and connected to the first upper connection post (104 (left) Fig 2G viewed from 180 degrees) and the bridge structure (TSV 19, 26, and structure shown in annotated Fig 2G viewed from 180 degrees),
a second semiconductor chip (die 100 (right) [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on a top surface of the second upper connection post (104 (right) Fig 2G viewed from 180 degrees) and a second area (shown in annotated Fig 2G viewed from 180 degrees) of the bridge structure (TSV 19, 26, and structure shown in annotated Fig 2G viewed from 180 degrees) and connected to the second upper connection post (104 (right) Fig 2G viewed from 180 degrees) and the bridge structure (TSV 19, 26, and structure shown in annotated Fig 2G viewed from 180 degrees),
the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees) spaced laterally apart from the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees);
a first molding layer (upper portion of 106 shown in annotated Fig 2G viewed from 180 degrees) covering a sidewall of the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees) and a sidewall of the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees); and
a second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] Fig 2G viewed from 180 degrees) on the top surface of the redistribution layer (120 Fig 2G viewed from 180 degrees) and covering sidewalls of the first (110 (left) Fig 2G viewed from 180 degrees) and second (110 (right) Fig 2G viewed from 180 degrees) lower posts and sidewalls of the first (104 (left) Fig 2G viewed from 180 degrees) and second upper connection posts (104 (right) Fig 2G viewed from 180 degrees),
wherein the second molding layer (116, 108, and lower portion of 106 Fig 2G viewed from 180 degrees) is in direct contact with a bottom surface of the first molding layer (upper portion of 106 shown in annotated Fig 2G viewed from 180 degrees), a bottom surface of the first semiconductor chip (100 (left) Fig 2G viewed from 180 degrees), and a bottom surface of the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees).
PNG
media_image1.png
850
1200
media_image1.png
Greyscale
PNG
media_image3.png
623
1075
media_image3.png
Greyscale
Lin et al does not disclose
a package substrate comprising lower substrate pads, substrate wires, and upper substrate pads;
solder ball terminals on bottom surfaces of the lower substrate pads;
a redistribution layer on a top surface of the package substrate;
connection solder balls between the package substrate and the redistribution layer and connected to the upper substrate pads and the redistribution pads;
a chip stack package on a top surface of the first upper connection post and a first area of the bridge structure and connected to the first upper connection post and the bridge structure, the chip stack package comprising a first lower semiconductor chip;
the second semiconductor chip spaced laterally apart from the chip stack package;
a first molding layer covering a sidewall of the chip stack package; and
wherein the second molding layer is in direct contact with a bottom surface of the chip stack package.
Yamagishi et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
a package substrate (mounting substrate 401 [0056] Fig 5) comprising lower substrate pads (shown in annotated Fig 5), substrate wires (mounting substrate wiring 402 [0056] Fig 5), and upper substrate pads (shown in annotated Fig 5).
PNG
media_image4.png
672
1030
media_image4.png
Greyscale
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al to include a package substrate comprising lower substrate pads, substrate wires, and upper substrate pads as taught by Yamagishi et al in order to provide and optimize electrical function between multiple semiconductor chips/devices [0056]. Further, a person of ordinary skill in the art would have recognized that optimizing electrical function between multiple semiconductor chips/devices would further optimize the function and capabilities of the device (see MPEP 2143.I(D)).
The combination of Lin et al and Yamagishi et al now discloses
a redistribution layer (redistribution structure RDL 120 [column 15, lines 28-40] Fig 2G viewed from 180 degrees Lin et al) on a top surface of the package substrate (401 Fig 5 Yamagishi et al);
solder balls (connectors 122 [column 15, lines 28-40] Fig 2G viewed from 180 degrees Lin et al) between the package substrate (401 Fig 5 Yamagishi et al) and the redistribution layer (120 Fig 2G viewed from 180 degrees Lin et al) and connected to the upper substrate pads (shown in annotated Fig 5 Yamagishi et al) and the redistribution pads (RDL1 and RDL3 Fig 2G viewed from 180 degrees Lin et al).
The combination of Lin et al and Yamagishi et al does not disclose
solder ball terminals on bottom surfaces of the lower substrate pads;
a chip stack package on a top surface of the first upper connection post and a first area of the bridge structure and connected to the first upper connection post and the bridge structure, the chip stack package comprising a first lower semiconductor chip;
the second semiconductor chip spaced laterally apart from the chip stack package;
a first molding layer covering a sidewall of the chip stack package; and
wherein the second molding layer is in direct contact with a bottom surface of the chip stack package.
Liao et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
solder ball terminals (connectors 48 [column 11, lines 9-22] Fig 1L) on bottom surfaces of the lower substrate pads (pads 47 [column 11, lines 9-22] Fig 1L);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lin et al and Yamagishi et al to include solder ball terminals on bottom surfaces of the lower substrate pads as taught by Liao et al in order to provide external connection to the device from other package components such as a printed circuit board, a flex PCB, or the like [column 11, lines 9-22]. Further, a person of ordinary skill in the art would have recognized that connecting other package components to the semiconductor packaging device would be advantageous in optimizing the electrical and functional capability of the device (see MPEP 2143.I(D)).
The combination of Lin et al, Yamagishi et al, and Liao et al does not disclose
a chip stack package on a top surface of the first upper connection post and a first area of the bridge structure and connected to the first upper connection post and the bridge structure, the chip stack package comprising a first lower semiconductor chip;
the second semiconductor chip spaced laterally apart from the chip stack package;
a first molding layer covering a sidewall of the chip stack package; and
wherein the second molding layer is in direct contact with a bottom surface of the chip stack package.
GOH et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
a chip stack package (memory die stacks 120 [0024] Fig 1);
the chip stack package (120 Fig 1) comprising a first lower semiconductor chip (lower most memory die 122 [0024] Fig 1);
the second semiconductor chip (die module 130 [0023] Fig 1) spaced laterally apart from the chip stack package (120 Fig 1);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lin et al, Yamagishi et al, and Liao et al to include a chip stack package as taught by GOH et al in order to optimize the memory functioning capability by having a stack of memory dies [0024]. Further, a person of ordinary skill in the art would have recognized that including a stack of memory dies would be advantageous in meeting small size parameters of the device while optimizing functional capability (see MPEP 2143.I(D)).
The combination of Lin et al, Yamagishi et al, Liao et al, and GOH et al now discloses
a chip stack package (120 Fig 1 GOH et al) on a top surface of the first upper connection post (connectors 104 (left) [column 15, lines 28-40] Fig 2G viewed from 180 degrees Lin et al) and a first area of the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) and connected to the first upper connection post (104 (left) Fig 2G viewed from 180 degrees Lin et al) and the bridge structure, the chip stack package (120 Fig 1 GOH et al) comprising a first lower semiconductor chip (lower most 122 Fig 1 GOH et al);
a first molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees Lin et al) covering a sidewall of the chip stack package (120 Fig 1 GOH et al); and
wherein the second molding layer (encapsulant material layer 116 [column 15, lines 28-40], dielectric layer 108 [column 15, lines 28-40], and lower portion of encapsulant 106 [column 15, lines 28-40] Fig 2G viewed from 180 degrees Lin et al) is in direct contact with a bottom surface of the chip stack package (120 Fig 1 GOH et al).
Regarding Claim 18, the combination of Lin et al, Yamagishi et al, Liao et al, and GOH et al discloses the limitation of claim 17. The combination of Lin et al, Yamagishi et al, Liao et al, and GOH et al does not disclose
further comprising:
a first upper bridge post (conductive posts 16 (left) [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees Lin et al) between the bridge structure (TSV 19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) and the chip stack package (120 Fig 1 GOH et al);
a second upper bridge post (conductive posts 16 (right) [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees Lin et al) between the bridge structure (TSV 19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) and the second semiconductor chip (100 (right) Fig 2G viewed from 180 degrees Lin et al); and
bridge solder balls (conductive cap 17 [column 3, lines 10-43] Fig 2C and Fig 2G viewed from 180 degrees) between the bridge structure (TSV 19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) and the first upper bridge posts (16 (left) Fig 2C and Fig 2G viewed from 180 degrees) and between the bridge structure (TSV 19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) and the second upper bridge posts (16 (right) Fig 2C and Fig 2G viewed from 180 degrees),
wherein the first molding layer (upper portion of 106 shown above in annotated Fig 2G viewed from 180 degrees Lin et al) is spaced apart from the first (16 (left) Fig 2C and Fig 2G viewed from 180 degrees Lin et al) and second upper bridge posts (16 (right) Fig 2C and Fig 2G viewed from 180 degrees) and the bridge solder balls (17 Fig 2C and Fig 2G viewed from 180 degrees).
Regarding Claim 20, the combination of Lin et al, Yamagishi et al, Liao et al, and GOH et al discloses the limitations of claim 17 as explained above. The combination of Lin et al, Yamagishi et al, Liao et al, and GOH further discloses
wherein a bottom surface of the bridge structure (TSV 19, conductive via 26 [column 16, lines 28-34], and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) is spaced apart from the redistribution layer (120 Fig 2G viewed from 180 degrees Lin et al), and
wherein the second molding layer (116, 108, and lower portion of 106 Fig 2G viewed from 180 degrees Lin et al) extends between the bottom surface of the bridge structure (19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al) and the redistribution layer (120 Fig 2G viewed from 180 degrees Lin et al) and covers the bottom surface of the bridge structure (19, 26, and structure shown above in annotated Fig 2G viewed from 180 degrees Lin et al).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 11482497) in view of Yamagishi et al (US 2006/0197679), Liao et al (US 10340253), and GOH et al (US 2023/0395576), and in further view of Schultz et al (US 2025/0300146).
Regarding Claim 19, the combination of Lin et al, Yamagishi et al, Liao et al, and GOH discloses the limitations of claim 18 as explained above. The combination of Lin et al, Yamagishi et al, Liao et al, and GOH et al does not directly disclose
wherein a height of the first upper connection post is about 5 µm to about 10 µm,
wherein a height of the first upper bridge post is about 5 µm to about 10 µm,
wherein a height of the second upper connection post is about 5 µm to about 10 µm, and
wherein a height of the second upper bridge post is about 5 µm to about 10 µm.
Shultz et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a height of the bridge is about 5 µm to about 10 µm (Si-less bridge 89 may have a height of 2-8 microns [0133] Fig 11).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lin et al, Yamagishi et al, Liao et al, and GOH et al to include wherein a height of the first upper connection post is about 5 µm to about 10 µm, wherein a height of the first upper bridge post is about 5 µm to about 10 µm, wherein a height of the second upper connection post is about 5 µm to about 10 µm, and wherein a height of the second upper bridge post is about 5 µm to about 10 µm as taught by Shultz et al in order to have a bridge that connects between two or more chiplets [0133] and is negligible for the next level of bump [0068], and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that optimizing the height of the bridge elements would be advantageous in meeting the small size requirements of the packaging device (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lu et al (US 2023/0087325) which discloses a plurality of chips stacked in a staggered manner [0051], and Choi et al (US 2021/0366874) which discloses a bridge die and redistribution layer patterns [0068].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights