Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 6-11 of, filed September 7, 2026, with respect to the rejection(s) of claim(s) 1, 17, and under Iucolano (US 20230246086 A1), Wang (US 20250374662 A1), and Kavrik (US 20240355934 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Matsuura (US 20130328105 A1), Pankove (US 4985742 A), and Dubey (US 20200411407 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (US 20130328105 A1) in further view of Pankove (US 4985742 A).
Regarding independent claim 1, Matsuura teaches a transistor ([0002], "More particularly, it relates to a technology effectively applicable to an IGBT device technology and a method for manufacturing an IGBT."), comprising: a gate electrode material (Fig. 2, 14; [0225], "Therein, trench gate electrodes 14 are embedded via the gate insulation film 22, respectively."); a gate insulator material (Fig. 2, 22; [0225], "Therein, trench gate electrodes 14 are embedded via the gate insulation film 22, respectively."); and a channel structure (Fig. 2, 15; [0170], "...and the depth of the P type body region 15 (channel region) is about 1.2 micrometers."), wherein the gate insulator material is between the channel structure and the gate electrode material (Fig. 2, 14, 22, 15, (The gate electrode is isolated from the channel region by the insulating film)).
However, Matsuura does not teach and the channel structure includes a first portion, a second portion, a third portion, and wherein: the second portion is between the first portion and the third portion, and the first portion and the third portion include gallium and nitrogen, and the second portion includes silicon and carbon, or the first portion and the third portion include silicon, and the second portion includes gallium and nitrogen.
However, in the same field of endeavor, Pankove teaches the channel structure includes a first portion, a second portion, a third portion, and wherein: the second portion is between the first portion and the third portion, and the first portion and the third portion include gallium and nitrogen, and the second portion includes silicon and carbon, or the first portion and the third portion include silicon, and the second portion includes gallium and nitrogen (Fig. 2B, 30, 32, 35; (Col.. 6, Lines 8-14), "In a second embodiment of the power transistor 17 shown in FIG. 2B, a p-type silicon carbide layer 30 has a surface 31 adjacent an n-type gallium nitride layer 32 With which it forms a first heterojunction 33. On an opposite surface 34 of the silicon carbide layer 30, a second n-type layer 35 made of gallium nitride is provided.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor of Matsuura with the channel structure of Pankove so that "high temperature operating characteristics are also provided", (Pankove, Col.3, Lines 1-2).
Regarding independent claim 17, Matsuura teaches an integrated circuit (IC) structure ([0002], "The present invention relates to a semiconductor device (or a semiconductor integrated circuit device)…"), comprising: a transistor ([0002], "More particularly, it relates to a technology effectively applicable to an IGBT device technology and a method for manufacturing an IGBT."); and a conductive structure coupled to the transistor (Fig. 5, 7; [0161], "The metal gate wire 7 is coupled to the metal gate electrode 5 formed of, for example, the same aluminum type wiring layer as the previous one."), wherein the transistor includes: a gate electrode (Fig. 2, 14; [0225], "Therein, trench gate electrodes 14 are embedded via the gate insulation film 22, respectively."), a gate insulator (Fig. 2, 22; [0225], "Therein, trench gate electrodes 14 are embedded via the gate insulation film 22, respectively."), and a channel structure (Fig. 2, 15; [0170], "...and the depth of the P type body region 15 (channel region) is about 1.2 micrometers."), wherein the gate insulator is between the channel structure and the gate electrode (Fig. 2, 14, 22, 15, (The gate electrode is isolated from the channel region by the insulating film)).
However, Matsuura does not teach the channel structure includes a first portion comprising gallium and nitrogen, and the channel structure further includes a second portion comprising silicon and carbon.
However, in the same field of endeavor, Pankove teaches the channel structure includes a first portion comprising gallium and nitrogen, and the channel structure further includes a second portion comprising silicon and carbon (Fig. 2B, 30, 32, 35; (Col.. 6, Lines 8-14), "In a second embodiment of the power transistor 17 shown in FIG. 2B, a p-type silicon carbide layer 30 has a surface 31 adjacent an n-type gallium nitride layer 32 With which it forms a first heterojunction 33. On an opposite surface 34 of the silicon carbide layer 30, a second n-type layer 35 made of gallium nitride is provided.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the IC of Matsuura with the channel structure of Pankove so that "high temperature operating characteristics are also provided", (Pankove, Col.3, Lines 1-2).
Regarding dependent claim 18, Matsuura, as previously modified by Pankove, teaches the IC structure according to claim 17. Pankove further teaches wherein the channel structure further includes a third portion, and wherein the third portion includes gallium and nitrogen, and the second portion is between the first portion and the third portion, or the third portion includes silicon and carbon, and the first portion is between the second portion and the third portion (Fig. 2B, 30, 32, 35; (Col.. 6, Lines 8-14), "In a second embodiment of the power transistor 17 shown in FIG. 2B, a p-type silicon carbide layer 30 has a surface 31 adjacent an n-type gallium nitride layer 32 With which it forms a first heterojunction 33. On an opposite surface 34 of the silicon carbide layer 30, a second n-type layer 35 made of gallium nitride is provided.").
Claim(s) 2-4, 7, 10-12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (US 20130328105 A1) in further view of Pankove (US 4985742 A) and Kim (US 20230354605 A1).
Regarding dependent claims 2, 3, 4, 7, 10, 11, 12, and 15, Matsuura, as previously modified by Pankove, teaches the transistor according to claim 1. However, as previously combined, they do not teach wherein, along a direction of a gate length of the transistor, the second portion is adjacent to the first portion, and the third portion is adjacent to the second portion (Claim 2); the transistor according to claim 2, wherein, in the direction, a dimension of the first portion or a dimension of the third portion is between about 10% and about 80% of a dimension of the second portion (Claim 3); the transistor according to claim 3, wherein, in the direction, the dimension of the first portion is substantially equal to the dimension of the third portion (Claim 4); the transistor according to claim 2, wherein, in planes perpendicular to the direction, a dimension of the first portion is substantially equal to a dimension of the third portion (Claim 7); the transistor according to claim 1, wherein the second portion is stacked above the first portion and the third portion is stacked above the second portion (Claim 10); the transistor according to claim 10, wherein a thickness of the second portion is at least about 50% larger than a thickness of the first portion or a thickness of the second portion (Claim 11); the transistor according to claim 11, wherein the thickness of the first portion is substantially equal to the thickness of the third portion (Claim 12); or the transistor according to claim 11, wherein the sum of the thickness of the first portion, the thickness of the second portion, and the thickness of the second portion is between about 5 nanometers and about 100 nanometers (Claim 15).
However, in the same field of endeavor, Kim teaches wherein, along a direction of a gate length of the transistor, the second portion is adjacent to the first portion, and the third portion is adjacent to the second portion (Fig. 9B, CL1, CL2, CL3; [0099], “The second channel layer CL2 may be located between the first and third channel layers CL1 and CL3.”); wherein, in the direction, a dimension of the first portion or a dimension of the third portion is between about 10% and about 80% of a dimension of the second portion ([0099], “A thickness of the second channel layer CL2 may range from about 5 nm to about 10 nm. A thickness of the third channel layer CL3 may be about 1 nm.”, (This is within the 10-80% range)); wherein, in the direction, the dimension of the first portion is substantially equal to the dimension of the third portion ([0099], “In other words, the thicknesses of the first and third channel layers CL1 and CL3 may be substantially equal to each other…”); wherein, in planes perpendicular to the direction, a dimension of the first portion is substantially equal to a dimension of the third portion (Fig. 9B, CL1, CL2, CL3, (The thicknesses in the vertical direction are all the same)); wherein the second portion is stacked above the first portion and the third portion is stacked above the second portion (Fig. 7A, CL1, CL2, CL3; [0076], “The second channel layer CL2 may be disposed between the first and third channel layers CL1 and CL3.”); wherein a thickness of the second portion is at least about 50% larger than a thickness of the first portion or a thickness of the [third] portion ([0076], “A thickness of the second channel layer CL2 in the first direction D1 may range from about 5 nm to about 10 nm. A thickness of the third channel layer CL3 in the first direction D1 may be about 1 nm.” (This is greater than 50%)); wherein the thickness of the first portion is substantially equal to the thickness of the third portion ([0076], “For example, the first and third channel layers CL1 and CL3 may have substantially the same thickness in the first direction D1…”); and wherein the sum of the thickness of the first portion, the thickness of the second portion, and the thickness of the second portion is between about 5 nanometers and about 100 nanometers ([0076], “A thickness of the first channel layer CL1 in the first direction D1 may be about 1 nm. A thickness of the second channel layer CL2 in the first direction D1 may range from about 5 nm to about 10 nm. A thickness of the third channel layer CL3 in the first direction D1 may be about 1 nm.” (This ranges from 7-12 nm, which is within the 5-100 nm range)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura and Pankove with the structured portions of Kim so as “to increase an integration density, a resistance and/or a current driving ability of the transistor” (Kim, [0003]).
Claim(s) 5, 6, 8, 9, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (US 20130328105 A1) in further view of Pankove (US 4985742 A) Kim (US 20230354605 A1), and Ha (US 20230276634 A1).
Regarding dependent claim 5, Matsuura, as modified by Pankove and Kim, teaches the transistor according to claim 3. However, as previously combined, they do not teach wherein, in the direction, the dimension of the first portion is smaller than the dimension of the third portion.
However, Ha teaches wherein, in the direction, the dimension of the first portion is smaller than the dimension of the third portion (Fig. 2, II-II’, 161, 162, 163; The first portion is smaller than the third portion)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura, Pankove, and Kim with the sizes of the sections of Ha so as that “the difference in the amount of current further increases according to the turned-on channel layer” (Ha, [0085]).
Regarding dependent claim 6, Matsuura, as modified by Pankove and Kim, teaches the transistor according to claim 3. However, as previously combined, they do not teach wherein, in the direction, the dimension of the first portion is larger than the dimension of the third portion.
However, Ha teaches wherein, in the direction, the dimension of the first portion is larger than the dimension of the third portion (Fig. 2, I-I’, 161, 162, 163; The first portion is larger than the third portion)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura, Pankove, and Kim with the sizes of the sections of Ha so as that “the difference in the amount of current further increases according to the turned-on channel layer” (Ha, [0085]).
Regarding dependent claim 8, Matsuura, as modified by Pankove and Kim, teaches the transistor according to claim 7. However, as previously combined, they do not teach wherein, in the planes perpendicular to the direction, the dimension of the first portion is different from a dimension of the second portion.
However, Ha teaches wherein, in the planes perpendicular to the direction, the dimension of the first portion is different from a dimension of the second portion (Fig. 10, 141b, 142b, 143b; [0083], “…first to third channel layers 141b, 142b, and 143b constituting a channel structure 140b may have first to third widths L1, L2, and L3 different from each other in the Y-direction…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura, Pankove, and Kim with the sizes of the sections of Ha so as that “the difference in the amount of current further increases according to the turned-on channel layer” (Ha, [0085]).
Regarding dependent claim 9, Matsuura, as modified by Pankove and Kim, teaches the transistor according to claim 7. However, as previously combined, they do not teach wherein, in the planes perpendicular to the direction, a dimension of the first portion is smaller than a dimension of the third portion.
However, Ha teaches wherein, in the planes perpendicular to the direction, a dimension of the first portion is smaller than a dimension of the third portion. (Fig. 10, 141b, 142b, 143b; [0084], “The first channel layer 141b may have a first width L1, the second channel layer 142b may have a second width L2 less than the first width L1, and the third channel layer 143b may have a third width L3 less than the second width L2.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura, Pankove, and Kim with the sizes of the sections of Ha so as that “the difference in the amount of current further increases according to the turned-on channel layer” (Ha, [0085]).
Regarding dependent claim 13, Matsuura, as modified by Pankove and Kim, teaches the transistor according to claim 11. However, as previously combined, they do not teach wherein the thickness of the first portion is smaller than the thickness of the third portion.
However, Ha teaches wherein the thickness of the first portion is smaller than the thickness of the third portion (Fig. 10, 143b, 141b; (The thicknesses increase for each layer in the z direction.)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura, Pankove, and Kim with the sizes of the sections of Ha so as that “the difference in the amount of current further increases according to the turned-on channel layer” (Ha, [0085]).
Regarding dependent claim 14, Matsuura, as modified by Pankove and Kim, teaches the transistor according to claim 11. However, as previously combined, they do not teach wherein the thickness of the first portion is smaller than the thickness of the third portion.
However, Ha teaches wherein the thickness of the first portion is larger than the thickness of the third portion (Fig. 2, I-I’, 161, 162, 163; The first portion is larger than the third portion)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura, Pankove, and Kim with the sizes of the sections of Ha so as that “the difference in the amount of current further increases according to the turned-on channel layer” (Ha, [0085]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura (US 20130328105 A1) in further view of Pankove (US 4985742 A), Yen (US 20240154008 A1) and Koh (US 20240213250 A1).
Regarding dependent claim 16, Matsuura, as previously modified by Pankove, teaches the transistor according to claim 1. However, as previously combined, they do not teach wherein: the channel structure is shaped like a fin, and the gate insulator material wraps around the fin, or the channel structure is shaped as a wire, and the gate insulator material wraps around the wire.
However, Yen teaches wherein: the channel structure is shaped like a fin, and the gate insulator material wraps around the fin (Fig. 4F, 214, 225, 130; [0070], “The channel layer 214 is located in the fin 225.”, [0065], “…forming a gate dielectric material and a gate conductor material above the channel cap layer…”), and Koh teaches the channel structure is shaped as a wire, and the gate insulator material wraps around the wire (Fig. 1B, 106A, 106B, 108; [0043], “The semiconductor channels (e.g., ribbons, wires, etc.) of the first transistor…”, [0046], “The semiconductor channels 106A and 106B are surrounded on three sides by a gate dielectric 108.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the transistor as described by the combination of Matsuura and Pankove with the fin shaped channel of Yen so as that the channel “protrudes from the surface of the buffer layer” (Yen, [0076]), or the wire shaped channel of Koh so as to “provide improved short channel control” (Koh, [0003]).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dubey (US 20200411407 A1), in view of Pankove (US 4985742 A).
Regarding independent claim 19, Dubey teaches an integrated circuit (IC) package (Fig. 1, 100; [0015], "FIG. 1 is a side, cross-sectional view of an example IC package 100 with a STIM 104."), comprising: an IC die, comprising a transistor (Fig. 7, 1640; [0042], "The die 1502 may include one or more transistors (e.g., some of the transistors 1640 of FIG. 7, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components."); and a further component, coupled to the IC die (Fig. 5, 108; [0036], "The dies 106-1 and 106-2 are coupled to an interposer 108 by interconnects 122, and the interposer 108 is coupled to the package substrate 102 by interconnects 126 (which may take the form of any of the interconnects 122 disclosed herein, such as first-level interconnects).").
However, Dubey does not teach wherein a channel region of the transistor includes a first portion and a second portion in contact with the first portion, the first portion includes a semiconductor material comprising gallium and nitrogen, and the second portion includes a semiconductor material comprising silicon and carbon.
However, in the same field of endeavor, Dubey teaches wherein a channel region of the transistor includes a first portion and a second portion in contact with the first portion, the first portion includes a semiconductor material comprising gallium and nitrogen, and the second portion includes a semiconductor material comprising silicon and carbon (Fig. 2B, 30, 32, 35; (Col.. 6, Lines 8-14), "In a second embodiment of the power transistor 17 shown in FIG. 2B, a p-type silicon carbide layer 30 has a surface 31 adjacent an n-type gallium nitride layer 32 With which it forms a first heterojunction 33. On an opposite surface 34 of the silicon carbide layer 30, a second n-type layer 35 made of gallium nitride is provided.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the IC package of Dubey with the channel structure of Pankove so that "high temperature operating characteristics are also provided", (Pankove, Col.3, Lines 1-2).
Regarding dependent claim 20, Dubey, as previously modified by Pankove, teaches the IC package according to claim 19, and further teaches wherein the further component is one of a package substrate, an interposer, or a further IC die (Fig. 5, 108; [0036], "The dies 106-1 and 106-2 are coupled to an interposer 108 by interconnects 122, and the interposer 108 is coupled to the package substrate 102 by interconnects 126 (which may take the form of any of the interconnects 122 disclosed herein, such as first-level interconnects).").
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20210257499 A1,.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 5712707996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights