Prosecution Insights
Last updated: April 19, 2026
Application No. 18/740,871

SWITCHING MODULE

Non-Final OA §102§103
Filed
Jun 12, 2024
Examiner
GONZALEZ, MILTON
Art Unit
2852
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sansha Electric Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
91%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
497 granted / 638 resolved
+9.9% vs TC avg
Moderate +13% lift
Without
With
+12.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
656
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
46.9%
+6.9% vs TC avg
§102
29.9%
-10.1% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 638 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6, 7, 12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Martin et al. (US 10,749,443). Regarding claim 1, Martin et al. discloses a switching module (see Fig. 33) comprising: a plurality of switching elements (elements 302, Fig. 33) connected in parallel, the plurality of switching elements each including a first electrode (see annotated Fig. 33 below), a second electrode (see annotated Fig. 33 below), and a control electrode (see annotated Fig. 33 below) that controls a main current flowing between the first electrode and the second electrode by a potential difference with respect to the second electrode; a first electrode wiring (see annotated Fig. 33 below) electrically connected to the first electrode of each of the plurality of switching elements; a second electrode wiring (see annotated Fig. 33 below) electrically connected to the second electrode of each of the plurality of switching elements; a control electrode wiring (see annotated Fig. 33 below) electrically connected to the control electrode of each of the plurality of switching elements; and a Kelvin wiring (see annotated Fig. 33 below) including a common Kelvin wiring (see annotated Fig. 33 below) and individual Kelvin wirings (see annotated Fig. 33 below) electrically connecting the common Kelvin wiring to the second electrode of each of the plurality of switching elements, wherein the Kelvin wiring has a Kelvin wiring predetermined portion that is at least a part of the Kelvin wiring, and the Kelvin wiring predetermined portion is at least one of the individual Kelvin wirings corresponding to at least one of the plurality of switching elements and has a resistance value of 1 mΩ or more (see col. 23, lines 4-32), or the Kelvin wiring predetermined portion is at least a part of the common Kelvin wiring and has a resistance value of 3 mΩ or more (see col. 23, lines 4-32). Regarding claim 2, Martin et al. discloses a switching module, wherein the plurality of switching elements are a number n (n is an integer of 2 or more) of switching elements, and the Kelvin wiring predetermined portion is the individual Kelvin wirings corresponding to a number n or n - 1 of the switching elements (see Fig. 33). Regarding claim 3, Martin et al. discloses a switching module, wherein the Kelvin wiring predetermined portion has a resistance value of 4 mΩ or more (see col. 23, lines 4-32). Regarding claim 4, Martin et al. discloses a switching module, wherein the Kelvin wiring predetermined portion has a resistance value of 10 mΩ or more (see col. 23, lines 4-32). Regarding claim 6, Martin et al. discloses a switching module, wherein the common Kelvin wiring extends so as to have both ends (see Fig. 33), the individual Kelvin wirings corresponding to the plurality of switching elements are electrically connected to the common Kelvin wiring at an interval (see Fig. 33), and the Kelvin wiring predetermined portion is a portion between a pair of points in the common Kelvin wiring (see Fig. 33), the pair of points to which a pair of the individual Kelvin wirings of a pair of the switching elements adjacent to each other are connected (see Fig. 33), and the portion corresponds to all of the switching elements (see Fig. 33). Regarding claim 7, Martin et al. discloses a switching module, wherein the Kelvin wiring predetermined portion has a resistance value of 12 mΩ or more (see col. 23, lines 4-32). Regarding claim 12, Martin et al. discloses a switching module, wherein the control electrode wiring includes a common control electrode wiring having one end connected to a control wiring terminal and another end terminated (see Fig. 33), and individual control electrode wirings electrically connecting the common control electrode wiring to the control electrode of each of the plurality of switching elements (see Fig. 33). Regarding claim 14, Martin et al. discloses a switching module, wherein the switching elements are an insulated gate bipolar transistor (IGBT), a field effect transistor, or a bipolar transistor (see col. 5, lines 48-58). PNG media_image1.png 736 914 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Martin et al. (US 10,749,443). Regarding claims 5, 8, 9, and 11, even assuming arguendo, without conceding, that Martin et al. does not disclose the claimed resistance values, Martin et al. shows that the resistance value of the Kelvin wiring predetermined portion is a result effective variable (see col. 23, lines 4-32). MPEP § 2144.05 (II)(A) states that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”, so determining the optimum or workable value of resistance is not an inventive limitation, since it could be determined by one with ordinary skill in the art through routine experimentation as a matter of obvious design choice for the desired practical application. Regarding claim 10, even assuming arguendo, without conceding, that Martin et al. does not disclose a sum of a resistance value of the Kelvin wiring predetermined portion and a resistance value of a control electrode resistor disposed on the control electrode wiring of the switching elements corresponding to the Kelvin wiring predetermined portion being a recommended gate resistance value of the switching elements, the examiner takes official notice of the fact that this feature is well known in the art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply a known technique to a known device ready for improvement to yield predictable results. Since it is known that low gate resistance would lead to a fast switching speed and low switching loss, but may also cause higher stresses on the semiconductor devices, selecting a gate resistance to seek a compromise between switching loss, switching delay, and stresses would be a matter of obvious design choice for the desired practical application. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Martin et al. (US 10,749,443) in view of Ewanchuk et al. (US 11,448,557). Regarding claim 13, even assuming arguendo, without conceding, that Martin et al. does not disclose the control electrode wiring including a plurality of single control electrode wirings connected to a plurality of control wiring terminals, Ewanchuk et al. shows that this feature is well known in the art. Ewanchuk et al. discloses a switching module (element PM’, Fig. 1b), wherein the control electrode wiring (see Fig. 1b) includes a plurality of single control electrode wirings connected to a plurality of control wiring terminals (see Fig. 1b), respectively, at one end and electrically connected to the control electrode of each of the plurality of switching elements (elements T’1, T’2, T’3, Fig. 1b) at another end (see Fig. 1b). Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply a known technique to a known device ready for improvement to yield predictable results, such as allowing the plurality of gates to be individually controlled. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yokoi et al. (US 2021/0141006) discloses a semiconductor device including power transistors coupled in parallel, each having a Kelvin terminal. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to MILTON GONZALEZ whose telephone number is (571)270-7914. The examiner can normally be reached 8:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WALTER LINDSAY can be reached at (571) 272-1674. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WALTER L LINDSAY JR/Supervisory Patent Examiner, Art Unit 2852 /M.G/Examiner, Art Unit 2852 3/18/2026
Read full office action

Prosecution Timeline

Jun 12, 2024
Application Filed
Mar 18, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
91%
With Interview (+12.7%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 638 resolved cases by this examiner. Grant probability derived from career allow rate.

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