Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This is in response to applicant’s filing date of June 12 , 2024. Claims 1-22 are currently pending.
Priority
Acknowledgment is made of applicant’s claim for foreign priority to Application KR10-2024-0023845, filed on February 19, 2024. The certified copy of the application as required by 37 CFR 1.55 has been received.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 12, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: comparison circuit, process information signal generation circuit, process voltage generation circuit, flag signal generation circuit, comparison voltage signal generation circuit, flag signal decoding circuit, cycle signal generation circuit, generating a plurality of flag signals, and generating a plurality of counting detection signals in claims 1 - 22.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections -- 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chang Hyun KIM (US-20190057730-A1)(“Kim”) and Michael B. Venditti (US-8779819-B1)(“Venditti”).
As per claim 1, Kim discloses semiconductor device (Figure 1) comprising:
a comparison circuit configured to generate a flag signal by comparing a voltage level of a reference voltage with a voltage level of a process voltage (Kim at Figure 1, flag generation circuit 5, and Para. [0033] discloses generating a flag signal based on a reference and process (RUND) signal:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled. A logic level of the reference flag SFLAG, which is enabled, may be set to be different according to the embodiments.”)
a process information signal generation circuit configured to generate a process information signal that indicates process variation based on a counting detection signal that is generated based on the flag signal (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”) and based on timing of pulses included in a cycle signal (Kim at Figure 1, judgement generator 3 and code generation circuit 7, and Para.[0031] discloses the generation of a judgment signal that is based on a timing of pulses:” judgement pulse generation circuit 3 may generate the judgement pulse JUDP in response to the period signal RUND, the initialization signal INT<5:1> and a clock signal CLK. The judgement pulse generation circuit 3 may generate the judgement pulse JUDP after a predetermined number of cycles of the clock signal CLK corresponding to a logic level combination of the initialization signal INT<5:1> elapses in a time period that the period signal RUND is enabled.”).
Kim does not disclose, but Venditti discloses a triggering process that begins after a start of a process variation detection operation (Vendetti at Column 7, Lines 21-36, discloses generating an enabling signal (pd_en) that causes a circuit to enable or disable certain circuit for testing or determining certain variations:” a PU_EN or PD_EN control signal is asserted, the appropriate data signal (e.g., a data signal or the inverted data signal) is applied by pre-driver circuitry 88, to the corresponding PMOS or NMOS devices, which are part of the output driver. When a PU_EN control signal is de-asserted, the pre-driver circuitry 88 is set such that the gate terminal of the corresponding PMOS device in the output driver is pulled to the positive supply to disable it. Similarly, when a PD_EN control signal is de-asserted, pre-driver circuitry 88 is set such that the gate terminal of the corresponding NMOS device in the output driver is pulled to ground to disable it. Disabling one or more PMOS or NMOS devices in this manner serves the purpose of increasing the device portion of the path resistance of the unit drive cell in moderately coarse steps, as expressed by Equation 5”.).
Vendetti is considered to be analogous to the claimed invention because it is in the same field of systems which detects voltage and timing variations in semiconductor devices. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim further in view of Vendetti to allow for finding if a semiconductor device is exhibiting voltage and timing variations by asserting certain control signals that would selectively enable or disable certain circuits. Motivation to do so would allow for reducing negative effects of semiconductor process variations by providing a means to ensure that, under particularly fast process, voltage, and temperature operating conditions, output transition times can be slowed down to fall in the acceptable range called for by the applicable specification. (Vendetti at Column 1, Lines 37-39.).
As per claim 2, Kim and Vendetti disclose a semiconductor device of claim 1, wherein the process voltage is a voltage having a voltage level that varies depending on the process variation, and wherein the cycle signal is a signal having pulses generated at timing that varies depending on the process variation (Vendetti at Column 2, Lines 1-5, discloses that variation can have negative effects on voltage and timing signals:” silicon process variation, operating voltage and temperature, and random mismatch effects, R.sub.PU and R.sub.PD will vary in an absolute sense and with respect to each other. The rise time (t.sub.rise) and fall time can be defined accordingly with dependency on R.sub.PU and R.sub.PD, as per Equation 1.”).
As per claim 3, Kim and Vendetti disclose a semiconductor device of claim 1, wherein the comparison circuit comprises:
a process voltage generation circuit comprising a PMOS transistor and an NMOS transistor and configured to drive the process voltage based on a driving force of the PMOS transistor and a driving force of the NMOS transistor (Vendetti at Column 2, Lines 36-42, discloses a voltage generation circuit:” an important source of rise and fall time mismatch in a voltage mode transmitter originates from mismatches in the on-resistance of the PMOS (r.sub.PMOS) and NMOS (r.sub.NMOS) devices 74 and 76 shown at FIG. 3B. R.sub.SER is a series resistance that can be attributable, for example, to a polysilicon resistor in some embodiments or to highly doped metals in other embodiments.”); and
a flag signal generation circuit configured to generate the flag signal by comparing the process voltage and the reference voltage during an interval while a comparison enable signal is enabled (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”).
As per claim 4, Kim and Vendetti disclose a semiconductor device of claim 3, wherein the process voltage generation circuit comprises:
the PMOS transistor disposed between a power source voltage and a first node and configured to drive the process voltage to a voltage level of the power source voltage when the process voltage is driven at a voltage level of a ground voltage (Vendetti at Column 7, Lines 7-40, discloses that PMOS transistor can be set voltage or ground:” a PU_EN control signal is de-asserted, the pre-driver circuitry 88 is set such that the gate terminal of the corresponding PMOS device in the output driver is pulled to the positive supply to disable it.”); and
the NMOS transistor disposed between the first node and the ground voltage and configured to drive the process voltage to the voltage level of the ground voltage when the process voltage is driven at the voltage level of the power source voltage (Vendetti at Column 7, Lines 7-40, discloses that NMOS transistor can be set voltage or ground:” pre-driver circuitry 88 is set such that the gate terminal of the corresponding NMOS device in the output driver is pulled to ground to disable it. Disabling one or more PMOS or NMOS devices in this manner serves the purpose of increasing the device portion of the path resistance of the unit drive cell in moderately coarse steps, as expressed by Equation 5.”).
As per claim 5, Kim and Vendetti disclose a semiconductor device of claim 3, wherein the flag signal generation circuit comprises:
a comparison voltage signal generation circuit configured to generate a comparison voltage signal by comparing the process voltage and the reference voltage during the interval while the comparison enable signal is enabled (Kim at Para. [0033] discloses comparing a process voltage (RUND) and a reference voltage (SROD) at Figure 1:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled.”); and
a flag signal decoding circuit configured to generate the flag signal based on a combination of logic levels of bits of the comparison voltage signal (Kim at Para. [0034] discloses a flag decoder that generates a calibration signal:” detection signal generation circuit 6 may generate a detection signal STOP_CAL in response to the reference flag SFLAG and the judgement pulse JUDP. The detection signal generation circuit 6 may latch the reference flag SFLAG and may buffer the latched reference flag SFLAG to generate the detection signal STOP_CAL, at a point of time that the judgement pulse JUDP is generated.”).
As per claim 6, Kim and Vendetti disclose a semiconductor device of claim 5, wherein the comparison voltage signal generation circuit comprises:
a comparison signal generation circuit configured to generate a comparison signal by comparing the process voltage and the reference voltage (Kim at Para. [0032] discloses generating a comparison signal from two voltage inputs:” reference signal generation circuit 4 may generate the reference signal SROD in response to a calibration code CAL_CD<2:1> and the period signal RUND. The reference signal generation circuit 4 may generate the reference signal SROD corresponding to a periodic signal whose cycle is controlled according to a logic level combination of the calibration code CAL_CD<2:1>.”) ; and
a comparison voltage signal output circuit configured to generate the comparison voltage signal by buffering the comparison signal during the interval while the comparison enable signal is enabled and configured to generate the comparison voltage signal that is disabled during the interval while the comparison enable signal is disabled (Kim at Para. [0034] discloses buffering a comparison signal until an enabling signal is received:” detection signal generation circuit 6 may generate a detection signal STOP_CAL in response to the reference flag SFLAG and the judgement pulse JUDP. The detection signal generation circuit 6 may latch the reference flag SFLAG and may buffer the latched reference flag SFLAG to generate the detection signal STOP_CAL, at a point of time that the judgement pulse JUDP is generated.”).
As per claim 7, Kim discloses a semiconductor device (Figure 1) comprising:
;
a counting detection signal generation circuit configured to generate a counting detection signal by comparing a target counting signal with a counting signal that counts pulses of the cycle signal (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”) (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”); and
a process information signal generation circuit configured to generate a process information signal that indicates process variation based on the counting detection signal (Kim at Figure 1, judgement generator 3 and code generation circuit 7, and Para.[0031] discloses the generation of a judgment signal that is based on a timing of pulses:” judgement pulse generation circuit 3 may generate the judgement pulse JUDP in response to the period signal RUND, the initialization signal INT<5:1> and a clock signal CLK. The judgement pulse generation circuit 3 may generate the judgement pulse JUDP after a predetermined number of cycles of the clock signal CLK corresponding to a logic level combination of the initialization signal INT<5:1> elapses in a time period that the period signal RUND is enabled.”) and a flag signal (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”).
Kim does not disclose, but Venditti discloses a cycle signal generation circuit configured to generate a cycle signal having pulses generated at timing that varies depending on process variation (Vendetti at Column 7, Lines 21-36, discloses generating an enabling signal (pd_en) that causes a circuit to enable or disable certain circuit for testing or determining certain variations:” a PU_EN or PD_EN control signal is asserted, the appropriate data signal (e.g., a data signal or the inverted data signal) is applied by pre-driver circuitry 88, to the corresponding PMOS or NMOS devices, which are part of the output driver. When a PU_EN control signal is de-asserted, the pre-driver circuitry 88 is set such that the gate terminal of the corresponding PMOS device in the output driver is pulled to the positive supply to disable it. Similarly, when a PD_EN control signal is de-asserted, pre-driver circuitry 88 is set such that the gate terminal of the corresponding NMOS device in the output driver is pulled to ground to disable it. Disabling one or more PMOS or NMOS devices in this manner serves the purpose of increasing the device portion of the path resistance of the unit drive cell in moderately coarse steps, as expressed by Equation 5”.).
Vendetti is considered to be analogous to the claimed invention because it is in the same field of systems which detects voltage and timing variations in semiconductor devices. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim further in view of Vendetti to allow for finding if a semiconductor device is exhibiting voltage and timing variations by asserting certain control signals that would selectively enable or disable certain circuits. Motivation to do so would allow for reducing negative effects of semiconductor process variations by providing a means to ensure that, under particularly fast process, voltage, and temperature operating conditions, output transition times can be slowed down to fall in the acceptable range called for by the applicable specification. (Vendetti at Column 1, Lines 37-39.).
As per claim 8, Kim and Vendetti disclose a semiconductor device of claim 7, wherein the cycle signal generation circuit is configured to:
increase a frequency of pulse generation of the cycle signal when the process variation is lower, and reduce a frequency of pulse generation of the cycle signal when the process variation is higher (Kim at Para. [0089] discloses changing the SROD signal (Fig. 1) to maintain a stable process signal notwithstanding the variations in the circuit:” the clock signal CLK is an external signal which is regularly toggled regardless of variation of characteristics of transistors included in the cycle control circuit, the clock signal CLK may have a constant cycle even though the characteristics of the transistors vary according to process/voltage/temperature (PVT) conditions. Thus, the cycle of the reference signal SROD, which is controlled by the clock signal CLK, is stably maintained to have a constant value regardless of a variation of the characteristics of the transistors.”) .
As per claim 9, Kim and Vendetti disclose a semiconductor device of claim 7, wherein the counting detection signal generation circuit comprises:
a counting circuit configured to generate the counting signal comprising bits that are sequentially counted based on pulses of the cycle signal received during an interval while a counting enable signal is enabled (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a counting sequence:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”) (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”); and
a counting comparison circuit configured to generate the counting detection signal by comparing the counting signal and the target counting signal (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”).
As per claim 10, Kim and Vendetti disclose a semiconductor device of claim 7, further comprising a comparison circuit configured to generate the flag signal by comparing a reference voltage and a process voltage having a voltage level that varies depending on the process variation (Kim at Figure 1, flag generation circuit 5, and Para. [0033] discloses generating a flag signal based on a reference and process (RUND) signal:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled. A logic level of the reference flag SFLAG, which is enabled, may be set to be different according to the embodiments.”).
As per claim 11, Kim and Vendetti disclose a semiconductor device of claim 10, wherein the comparison circuit comprises:
a process voltage generation circuit comprising a PMOS transistor and an NMOS transistor and configured to drive the process voltage based on a driving force of the PMOS transistor and a driving force of the NMOS transistor (Vendetti at Column 2, Lines 36-42, discloses a voltage generation circuit:” an important source of rise and fall time mismatch in a voltage mode transmitter originates from mismatches in the on-resistance of the PMOS (r.sub.PMOS) and NMOS (r.sub.NMOS) devices 74 and 76 shown at FIG. 3B. R.sub.SER is a series resistance that can be attributable, for example, to a polysilicon resistor in some embodiments or to highly doped metals in other embodiments.”); and
a flag signal generation circuit configured to generate the flag signal by comparing the process voltage and the reference voltage during an interval while a comparison enable signal is enabled (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”).
As per claim 12, Kim and Vendetti disclose a semiconductor device of claim 11, wherein the process voltage generation circuit comprises:
the PMOS transistor disposed between a power source voltage and a first node and configured to drive the process voltage to a voltage level of the power source voltage when the process voltage is driven at a voltage level of a ground voltage (Vendetti at Column 7, Lines 7-40, discloses that PMOS transistor can be set voltage or ground:” a PU_EN control signal is de-asserted, the pre-driver circuitry 88 is set such that the gate terminal of the corresponding PMOS device in the output driver is pulled to the positive supply to disable it.”); and
the NMOS transistor disposed between the first node and the ground voltage and configured to drive the process voltage to the voltage level of the ground voltage when the process voltage is driven at the voltage level of the power source voltage (Vendetti at Column 7, Lines 7-40, discloses that NMOS transistor can be set voltage or ground:” pre-driver circuitry 88 is set such that the gate terminal of the corresponding NMOS device in the output driver is pulled to ground to disable it. Disabling one or more PMOS or NMOS devices in this manner serves the purpose of increasing the device portion of the path resistance of the unit drive cell in moderately coarse steps, as expressed by Equation 5.”)
As per claim 13, Kim and Vendetti disclose a semiconductor device of claim 11, wherein the flag signal generation circuit comprises:
a comparison voltage signal generation circuit configured to generate a comparison voltage signal by comparing the process voltage and the reference voltage during the interval while the comparison enable signal is enabled (Kim at Para. [0033] discloses comparing a process voltage (RUND) and a reference voltage (SROD) at Figure 1:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled.”); and
a flag signal decoding circuit configured to generate the flag signal based on a combination of logic levels of bits of the comparison voltage signal (Kim at Para. [0034] discloses a flag decoder that generates a calibration signal:” detection signal generation circuit 6 may generate a detection signal STOP_CAL in response to the reference flag SFLAG and the judgement pulse JUDP. The detection signal generation circuit 6 may latch the reference flag SFLAG and may buffer the latched reference flag SFLAG to generate the detection signal STOP_CAL, at a point of time that the judgement pulse JUDP is generated.”).
As per claim 13, Kim and Vendetti disclose a semiconductor device of claim 13, wherein the comparison voltage signal generation circuit comprises:
a comparison voltage signal generation circuit configured to generate a comparison voltage signal by comparing the process voltage and the reference voltage during the interval while the comparison enable signal is enabled (Kim at Para. [0033] discloses comparing a process voltage (RUND) and a reference voltage (SROD) at Figure 1:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled.”); and
a comparison voltage signal output circuit configured to generate the comparison voltage signal by buffering the comparison signal during the interval while the comparison enable signal is enabled and configured to generate the comparison voltage signal that is disabled during the interval while the comparison enable signal is disabled (Kim at Para. [0034] discloses a flag decoder that generates a calibration signal:” detection signal generation circuit 6 may generate a detection signal STOP_CAL in response to the reference flag SFLAG and the judgement pulse JUDP. The detection signal generation circuit 6 may latch the reference flag SFLAG and may buffer the latched reference flag SFLAG to generate the detection signal STOP_CAL, at a point of time that the judgement pulse JUDP is generated.”).
As per claim 15, Kim discloses a semiconductor device (Figure 1) comprising:
a comparison circuit configured to generate a plurality of flag signals in response to detecting a voltage level of a process voltage having a voltage level that varies depending on process variation (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”);
a counting detection signal generation circuit configured to generate a plurality of counting detection signals by comparing a counting signal with a first target counting signal (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”), a second target counting signal, a third target counting signal, and a fourth target counting signal (Kim at Figure 1, judgement generator 3 and code generation circuit 7, and Para.[0031] discloses the generation of a judgment signal that is based on a timing of pulses:” judgement pulse generation circuit 3 may generate the judgement pulse JUDP in response to the period signal RUND, the initialization signal INT<5:1> and a clock signal CLK. The judgement pulse generation circuit 3 may generate the judgement pulse JUDP after a predetermined number of cycles of the clock signal CLK corresponding to a logic level combination of the initialization signal INT<5:1> elapses in a time period that the period signal RUND is enabled.”), ; and
a process information signal generation circuit configured to generate a process information signal that indicates process variation based on the counting detection signal (Kim at Figure 1, judgement generator 3 and code generation circuit 7, and Para.[0031] discloses the generation of a judgment signal that is based on a timing of pulses:” judgement pulse generation circuit 3 may generate the judgement pulse JUDP in response to the period signal RUND, the initialization signal INT<5:1> and a clock signal CLK. The judgement pulse generation circuit 3 may generate the judgement pulse JUDP after a predetermined number of cycles of the clock signal CLK corresponding to a logic level combination of the initialization signal INT<5:1> elapses in a time period that the period signal RUND is enabled.”) and a flag signal (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”).
Kim does not disclose, but Venditti discloses wherein the counting signal counts pulses of a cycle signal having pulse timing that varies depending on the process variation (Vendetti at Column 2, Lines 1-5, discloses that variation can have negative effects on voltage and timing signals:” silicon process variation, operating voltage and temperature, and random mismatch effects, R.sub.PU and R.sub.PD will vary in an absolute sense and with respect to each other. The rise time (t.sub.rise) and fall time can be defined accordingly with dependency on R.sub.PU and R.sub.PD, as per Equation 1.”).
Vendetti is considered to be analogous to the claimed invention because it is in the same field of systems which detects voltage and timing variations in semiconductor devices. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim further in view of Vendetti to allow for finding if a semiconductor device is exhibiting voltage and timing variations by asserting certain control signals that would selectively enable or disable certain circuits. Motivation to do so would allow for reducing negative effects of semiconductor process variations by providing a means to ensure that, under particularly fast process, voltage, and temperature operating conditions, output transition times can be slowed down to fall in the acceptable range called for by the applicable specification. (Vendetti at Column 1, Lines 37-39.).
As per claim 16, Kim and Vendetti disclose a semiconductor device of claim 15, wherein the comparison circuit generates the plurality of flag signals by comparing the process voltage with a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage each at a constant voltage level unaffected by process variation (Kim at Para. [0089] discloses changing the SROD signal (Fig. 1) to maintain a stable process signal notwithstanding the variations in the circuit:” the clock signal CLK is an external signal which is regularly toggled regardless of variation of characteristics of transistors included in the cycle control circuit, the clock signal CLK may have a constant cycle even though the characteristics of the transistors vary according to process/voltage/temperature (PVT) conditions. Thus, the cycle of the reference signal SROD, which is controlled by the clock signal CLK, is stably maintained to have a constant value regardless of a variation of the characteristics of the transistors.”).
As per claim 17, Kim and Vendetti disclose a semiconductor device of claim 15, wherein the comparison circuit generates the plurality of flag signals based on a change in a driving force of a PMOS transistor and a driving force of an NMOS transistor, which PMOS transistor and NMOS transistor drive the process voltage(Vendetti at Column 2, Lines 36-42, discloses a voltage generation circuit:” an important source of rise and fall time mismatch in a voltage mode transmitter originates from mismatches in the on-resistance of the PMOS (r.sub.PMOS) and NMOS (r.sub.NMOS) devices 74 and 76 shown at FIG. 3B. R.sub.SER is a series resistance that can be attributable, for example, to a polysilicon resistor in some embodiments or to highly doped metals in other embodiments.”).
As per claim 18, Kim and Vendetti disclose a semiconductor device of claim 15, wherein the comparison circuit comprises:
a process voltage generation circuit comprising a PMOS transistor and an NMOS transistor and configured to drive the process voltage based on a driving force of the PMOS transistor and a driving force of the NMOS transistor (Vendetti at Column 2, Lines 36-42, discloses a voltage generation circuit:” an important source of rise and fall time mismatch in a voltage mode transmitter originates from mismatches in the on-resistance of the PMOS (r.sub.PMOS) and NMOS (r.sub.NMOS) devices 74 and 76 shown at FIG. 3B. R.sub.SER is a series resistance that can be attributable, for example, to a polysilicon resistor in some embodiments or to highly doped metals in other embodiments.”); and
a flag signal generation circuit configured to generate the plurality of flag signals by comparing the process voltage and a plurality of reference voltages during an interval while a comparison enable signal is enabled (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”).
As per claim 19, Kim and Vendetti disclose a semiconductor device of claim 18, wherein the process voltage generation circuit comprises:
the PMOS transistor disposed between a power source voltage and a first node and configured to drive the process voltage to a voltage level of the power source voltage when the process voltage is driven at a voltage level of a ground voltage (Vendetti at Column 7, Lines 7-40, discloses that PMOS transistor can be set voltage or ground:” a PU_EN control signal is de-asserted, the pre-driver circuitry 88 is set such that the gate terminal of the corresponding PMOS device in the output driver is pulled to the positive supply to disable it.”); and
the NMOS transistor disposed between the first node and the ground voltage and configured to drive the process voltage to the voltage level of the ground voltage when the process voltage is driven at the voltage level of the power source voltage (Vendetti at Column 7, Lines 7-40, discloses that NMOS transistor can be set voltage or ground:” pre-driver circuitry 88 is set such that the gate terminal of the corresponding NMOS device in the output driver is pulled to ground to disable it. Disabling one or more PMOS or NMOS devices in this manner serves the purpose of increasing the device portion of the path resistance of the unit drive cell in moderately coarse steps, as expressed by Equation 5.”).
As per claim 20, Kim and Vendetti disclose a semiconductor device of claim 18, wherein the flag signal generation circuit comprises:
a comparison voltage signal generation circuit configured to generate a plurality of comparison voltage signals by comparing the process voltage and the plurality of reference voltages during the interval while the comparison enable signal is enabled (Kim at Para. [0033] discloses comparing a process voltage (RUND) and a reference voltage (SROD) at Figure 1:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled.”) (Kim at Para. [0033] discloses comparing a process voltage (RUND) and a reference voltage (SROD) at Figure 1:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled.”); and
a flag signal decoding circuit configured to generate the plurality of flag signals based on a combination of logic levels of the plurality of comparison voltage signals (Kim at Para. [0034] discloses a flag decoder that generates a calibration signal:” detection signal generation circuit 6 may generate a detection signal STOP_CAL in response to the reference flag SFLAG and the judgement pulse JUDP. The detection signal generation circuit 6 may latch the reference flag SFLAG and may buffer the latched reference flag SFLAG to generate the detection signal STOP_CAL, at a point of time that the judgement pulse JUDP is generated.”) (Kim at Para. [0034] discloses a flag decoder that generates a calibration signal:” detection signal generation circuit 6 may generate a detection signal STOP_CAL in response to the reference flag SFLAG and the judgement pulse JUDP. The detection signal generation circuit 6 may latch the reference flag SFLAG and may buffer the latched reference flag SFLAG to generate the detection signal STOP_CAL, at a point of time that the judgement pulse JUDP is generated.”).
As per claim 21, Kim and Vendetti disclose a semiconductor device of claim 15, wherein the counting detection signal generation circuit comprises:
a counting circuit configured to generate the counting signal comprising bits that are sequentially counted based on pulses of the cycle signal received during an interval while a counting enable signal is enabled (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a counting sequence:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”) (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”); and
a counting comparison circuit configured to generate the counting detection signal by comparing the counting signal and the target counting signal (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”).
As per claim 22, Kim discloses a method (Figure 17) comprising:
generating a plurality of flag signals (Kim at Figure 1, flag generation circuit 5, and Para. [0033] discloses generating a flag signal based on a reference and process (RUND) signal:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND. The flag generation circuit 5 may generate the reference flag SFLAG which is enabled in synchronization with a point of time that a predetermined number of cycles of the reference signal SROD elapses in a time period that the period signal RUND is enabled. A logic level of the reference flag SFLAG, which is enabled, may be set to be different according to the embodiments.”);
generating a counting signal that counts pulses of a cycle signal having pulse timing that varies depending on the process variation (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”) (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”);
generating a plurality of counting detection signals by comparing the counting signal with each of a plurality of target counting signals (Kim at Figure 1, module 5, and Para. [0033] discloses generating a flag based on a comparison of two voltages:” flag generation circuit 5 may generate a reference flag SFLAG in response to the reference signal SROD and the period signal RUND.”) ; and
generating a process information signal that indicates the process variation based on the plurality of counting detection signals (Kim at Figure 1, judgement generator 3 and code generation circuit 7, and Para.[0031] discloses the generation of a judgment signal that is based on a timing of pulses:” judgement pulse generation circuit 3 may generate the judgement pulse JUDP in response to the period signal RUND, the initialization signal INT<5:1> and a clock signal CLK. The judgement pulse generation circuit 3 may generate the judgement pulse JUDP after a predetermined number of cycles of the clock signal CLK corresponding to a logic level combination of the initialization signal INT<5:1> elapses in a time period that the period signal RUND is enabled.”) and the plurality of flag signals (Kim at Figure 1, code generation 7, and Para. [0035] discloses generating a process information such as calibration and sense codes:” code generation circuit 7 may generate the calibration code CAL_CD<2:1> and a sense code FCD<2:1> in response to the detection signal STOP_CAL and the judgement pulse JUDP. The code generation circuit 7 may generate the calibration code CAL_CD<2:1> that is counted in response to the detection signal STOP_CAL and the judgement pulse JUDP.”).
Kim does not disclose, but Venditti discloses triggering a process in response to detecting a process voltage (Vendetti at Column 7, Lines 21-36, discloses generating an enabling signal (pd_en) that causes a circuit to enable or disable certain circuit for testing or determining certain variations:” a PU_EN or PD_EN control signal is asserted, the appropriate data signal (e.g., a data signal or the inverted data signal) is applied by pre-driver circuitry 88, to the corresponding PMOS or NMOS devices, which are part of the output driver. When a PU_EN control signal is de-asserted, the pre-driver circuitry 88 is set such that the gate terminal of the corresponding PMOS device in the output driver is pulled to the positive supply to disable it. Similarly, when a PD_EN control signal is de-asserted, pre-driver circuitry 88 is set such that the gate terminal of the corresponding NMOS device in the output driver is pulled to ground to disable it. Disabling one or more PMOS or NMOS devices in this manner serves the purpose of increasing the device portion of the path resistance of the unit drive cell in moderately coarse steps, as expressed by Equation 5”.).
Vendetti is considered to be analogous to the claimed invention because it is in the same field of systems which detects voltage and timing variations in semiconductor devices. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim further in view of Vendetti to allow for finding if a semiconductor device is exhibiting voltage and timing variations by asserting certain control signals that would selectively enable or disable certain circuits. Motivation to do so would allow for reducing negative effects of semiconductor process variations by providing a means to ensure that, under particularly fast process, voltage, and temperature operating conditions, output transition times can be slowed down to fall in the acceptable range called for by the applicable specification. (Vendetti at Column 1, Lines 37-39.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
HUANG; SHIH-HSIUNG (US-20240113723-A1) TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTER HAVING ASYNCHRONOUS CONTROL;
Froelich; Daniel S. et al. (US-20220163588-A1) SYSTEMS, METHODS, AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TESTING;
Mori; Kaoru (US-10957378-B1) Control circuit and control method thereof for pseudo static random access memory;
NEIDORFF; Robert Allan et al. (US-20210013805-A1) SEMICONDUCTOR PROCESS VARIATION DETECTOR;
AIPPERSPACH; Anthony G. et al. (US-20170242066-A1) ON-CHIP DIAGNOSTIC CIRCUITRY MONITORING MULTIPLE CYCLES OF SIGNAL SAMPLES;
WAKII; Takeshi et al. (US-20120049811-A1) OUTPUT SWITCHING CIRCUIT;
Bai; Xiaoliang et al. (US-20110245948-A1) Method And Circuit To Generate Race Condition Test Data At Multiple Supply Voltages;
Naffziger; Samuel D. et al. (US-7148755-B2) System and method to adjust voltage;
Belleau, Raoul J. (US-20050225314-A1) Method of measuring duty cycle;
Frisch, Arnold M. et al. (US-20050097420-A1) Apparatus for jitter testing an IC;
Kanda; Kazushige et al. (US-6469573-B2) Semiconductor integrated circuit;
Donnelly; Kevin S. et al. (US-5959481-A) Bus driver circuit including a slew rate indicator circuit having a one shot circuit;
Norman; Robert D. et al. (US-5956289-A) Clock signal from an adjustable oscillator for an integrated circuit;
Suma; Katsuhiro et al. (US-5400290-A) Semiconductor device allowing accurate characteristics test.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELLIS B. RAMIREZ whose telephone number is (571)272-8920. The examiner can normally be reached 7:30 am to 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ramon Mercado can be reached at 571-270-5744. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
ELLIS B. RAMIREZ
Primary Examiner
Art Unit 3658
/ELLIS B. RAMIREZ/Examiner, Art Unit 3658
Prosecution Insights