Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 10, 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byeongwoo Koo et al. (A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET”, IEEE).
Regarding claim 1, Byeongwoo Koo et al. disclose a digital-to-analog converter (DAC) circuit (fig. 1) comprising: a serializer circuit (Top part of fig. 1) comprising a plurality of multiplexers (note the multiplexers in fig. 1) and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers (page 87, left hand column, lines 2- 14); and a cell array (current cell in fig. 1) comprising a plurality of unit cells and configured to output an analog signal based on the serial code (fig. 1), and wherein the serializer circuit (fig. 1) comprises: a pseudo random number generation circuit (note the PRNG in fig. 1) configured to generate random numbers in response to edges of a first clock signal (page 87, line 21 – 23); a first switch circuit (DEM, fig. 1;page 87, left hand column lines 18 - 22) connected to a first multiplexer; a second switch circuit (DEM) connected to a second multiplexer (there are four DEM in the DEM block, see page 87, left hand column lines 17 – 24); and a random number circuit (it is between PRNG and the DEM blocks in fig. 1) configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively (fig. 1).
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Claim 11 is the method of claim 1.
Regarding claim 11, Byeongwoo Koo et al. disclose method of controlling a digital-to-analog converter (DAC) circuit (fig.1 ), the method comprising: applying a first clock signal to a pseudo random number generation (PRNG) circuit generating random numbers (note in the circuit) in response to edges of an applied clock signal (page 87, line 21 – 23); transmitting different random numbers generated in response to different edges of the first clock signal from a pseudo random number generation circuit to a first switch circuit (DEM) connected to a first multiplexer and a second switch circuit (DEM, fig. 1) connected to a second multiplexer, respectively (there are four DEM in the DEM block, see page 87, left hand column lines 17 – 24); and generating an analog signal based on a serial code comprising codes output from the first switch circuit and the second switch circuit, wherein the codes output from the first switch circuit (DEM) and the second switch circuit (DEM) are generated based on the random numbers (it is between PRNG and the DEM blocks in fig. 1) .
Regarding claim 9, Byeongwoo Koo et al. disclose a digital-to-analog converter (DAC) circuit (fig. 1) wherein the pseudo random number generation circuit (PRNG) is further configured to generate pseudo random numbers (it is between PRNG and the DEM blocks in fig. 1) according to a specified probability, respectively, in response to the edges of the first clock signal (Fig. 1).
Regarding claim 10, Byeongwoo Koo et al. disclose a digital-to-analog converter (DAC) circuit (fig. 1) wherein the cell array (not the cell array in figs. 1, 3) is further configured to output the analog signal comprising a voltage signal generated by applying a preset current to unit cells selected based on the serial code among the plurality of unit cells (figs. 1, 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bin et al. (USPGPUB 2023/0253991) in view of Byeongwoo Koo et al. (A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET”, IEEE).
Regarding claim 16, Bin et al. disclose an electronic device (figs. 3, 4) that transmits and receives an RF (radio frequency) signal (1002), the electronic device comprising: a digital-to-analog converter (DAC) circuit (24, fig. 4) configured to convert a digital signal into an analog signal; and an antenna (1004) configured to output the analog signal as the RF signal (figs. 3, 4) but do not disclose an electronic device where the DAC circuit comprises: a serializer circuit comprising a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array comprising a plurality of unit cells and configured to output the analog signal based on the serial code, and wherein the serializer circuit comprises: a pseudo random number generation circuit configured to generate random numbers in response to edges of a first clock signal; a first switch circuit connected to a first multiplexer and a second switch circuit connected to a second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively. However, Byeongwoo Koo et al., in the same field of endeavor, disclose an electronic device where a DAC a digital-to-analog converter (DAC) circuit (fig. 1) comprising: a serializer circuit (Top part of fig. 1) comprising a plurality of multiplexers (note the multiplexers in fig. 1) and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers (page 87, left hand column, lines 2- 14); and a cell array (current cell in fig. 1) comprising a plurality of unit cells and configured to output an analog signal based on the serial code (fig. 1), and wherein the serializer circuit (fig. 1) comprises: a pseudo random number generation circuit (note the PRNG in fig. 1) configured to generate random numbers in response to edges of a first clock signal (page 87, line 21 – 23); a first switch circuit (DEM, fig. 1;page 87, left hand column lines 18 - 22) connected to a first multiplexer; a second switch circuit (DEM) connected to a second multiplexer (there are four DEM in the DEM block, see page 87, left hand column lines 17 – 24); and a random number circuit (it is between PRNG and the DEM blocks in fig. 1) configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively (fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art time of the effective filing of the invention to modify at the Bin et al. with that of Byeongwoo Koo et al. in order to improve the performance of the electronic device.
Regarding claim 20, the combination of Bin et al. and Byeongwoo Koo et al. would achieve the same end result as the claimed invention since Byeongwoo Koo et al. disclose an electronic device (fig. 1), wherein the cell array (current cell array in figs. 1 and 3) is further configured to output the analog signal comprising a voltage signal generated by applying a preset current to unit cells selected based on the serial code among the plurality of unit cells (figs. 1, 3; page 86, left hand column, second paragraph to right hand column). Therefore, it would have been obvious to one of ordinary skill in the art time of the effective filing of the invention to modify at the Bin et al. with that of Byeongwoo Koo et al. in order to improve the performance of the electronic device.
Allowable Subject Matter
Claims 2 – 8, 12 – 15, 17 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior arts made of record fail to disclose an DAC in which a random number circuit comprise a first synchronous circuit configured to transmit, in response to a second clock signal, a first random number generated by the pseudo random number generation circuit in response to a first edge of the first clock signal to the first switch circuit; and a second synchronous circuit configured to transmit, in response to a third clock signal different from the second clock signal, a second random number generated by the pseudo random number generation circuit in response to a second edge of the first clock signal to the second switch circuit..
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845