Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 6-7 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20190207868 A1 to Chang et al in view of US 20220345417 A1 to Kasichainula et al. (“Kasichainula”).
Regarding claim 1, Chang taught a packet processing system (“high performance computing system”/”data center”) comprising: a network device that transmits and receives a plurality of packets through a network; and a computing device that processes the plurality of packets (consider Fig. 12 and paragraphs 0051-0052 regarding “compute devices and “accelerator devices” and also paragraph 0107, “For example, packets 1800, 1820, and 1840 can be used by a compute device or an accelerator device to communicate with another device and/or each other”)
wherein the computing device is configured to generate a plurality of pieces of transmission metadata related to a quality of service (QoS) of the plurality of packets, add the plurality of pieces of generated transmission metadata to the plurality of packets, and transmit the plurality of packets to which the plurality of pieces of transmission metadata are added to the network device, (consider paragraph 0093 wherein the “compute device” “can receive a packet from another device using interface 1700 and process any content of the packet (e.g., header and/or payload)”) (consider further paragraph 0107 regarding “packets” that “can be used by a compute device or an accelerator device to communicate with another device and/or each other” including a “header” containing “packet meta data” which “indicate how the network packet was processed or how the network packet is to be processed by the receiver” including “quality of service (QoS) designation, encryption parameters (e.g., algorithm to use and key), accelerator selection (e.g., address), accelerator command (e.g., actions an accelerator is to perform), next accelerator selection (e.g., address of next accelerator to select), and so forth. An address of an accelerator can be an accelerator's MAC address or an index (e.g., 0, 1, 2, and so forth)”) (consider further paragraph 0133 wherein “a determination can be made as to a next stage processing for a packet” which “can be made in connection with processing of a packet (e.g., by inspection of a header, VLAN tag, MPLS header, meta-data, or payload) so that after the processing of the packet, there is to be additional processing to be performed on the packet or information determined based on the processing of the packet”)
and the network device is configured to transmit the plurality of packets through the network according to a transmission order determined based on the plurality of pieces of transmission metadata. (consider paragraphs 0098-0099 wherein “prioritization of processing can occur based on flow identifiers, contexts, states, and requesting applications” such that “priority levels can be assigned based on input buffers or queues such that an input buffer or queue has a higher priority level than another input buffer or queue”) (consider further paragraph 0112, “An accelerator could use a command to determine how to process content and a priority of processing (e.g., priority queue allocation) could be determined based on priority.”) (consider further paragraphs 0114-0115 regarding “multiple Quality of Service (QoS) level queues to allocate packets for processing” wherein a “received packet is allocated to a QoS queue based on the determined QoS level” such that “a particular queue can be allocated for serving packets according to a particular QoS” which “can allow for prioritization of packet processing and can potentially reduce deadlock, provide traffic isolation, or packet priority management and reassignment” by “a packet classifier (e.g., flexible parsing unit)” which “can determine a QoS level of the received packet based on one or more of: a header of the received packet”) (consider also paragraph 0120, specifically “Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet”),
wherein the computing device includes:
a network application for performing processing on the plurality of packets; and a scheduling module that generates the plurality of pieces of transmission metadata related to the QoS of the plurality of packets and transmits the plurality of packets and the plurality of pieces of transmission metadata to the network device, (consider Fig. 15 regarding the “environment the compute device may establish”) (consider further paragraph 0092 wherein “an accelerator sled can indicate information in an encapsulating packet that can be used by a compute device. The compute device can use the information to determine how to interact with the accelerator sled. For example, information such as accelerator selection, accelerator command, flow identifier, priority, queue level, buffer level, and so forth can be used to determine how to process content of the packet or to interact with the remote device” wherein “an encapsulating packet can include a priority designation to indicate a priority level to assign a packet and corresponding task such that the receiver can use the priority level designation to allocate to the packet and corresponding task”) and
the network device includes:
a transmission queue that stores the plurality of packets and the plurality of pieces of transmission metadata received from the scheduling module; (consider further paragraph 0099, specifically “Interface 1754 can use an input queue 1756 to store received packets from interface 1706 and other devices for processing by one or more of accelerators 1752-0 to 1752-N”)
a transmission module that dequeues the plurality of packets stored in the transmission queue according to the transmission order determined based on the plurality of pieces of transmission metadata; and a transmission interface that transmits the plurality of dequeued packets to the network. (consider paragraph 0099 regarding “interfaces” which “can use an input queue 1756 to store received packets from interface 1706 and other devices for processing by one or more of accelerators 1752-0 to 1752-N” and “priority levels can be associated with an input or output buffer so that packets with a higher priority level can be allocated more bandwidth for transmission or higher priority in terms of use of an accelerator”) (consider further paragraph 0095, specifically “interface 1706 can encapsulate a portion of the content of the received packet into an encapsulating packet and transmit the encapsulating packet to accelerator cluster 1750 for processing using one or more of accelerators 1752-0 to 1752-N. The portion of the content can include content of the received packet and/or content that is determined using one or more of accelerators 1704-0 to 1704-M after processing content of the received packet. In some embodiments, the encapsulating packet that carries the portion of the received packet can include information in its header such that the receiver (e.g., accelerator cluster 1750) can use the information to decide how to process or handle content of the encapsulating packet”) (again, consider paragraph 0120, specifically “Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet”) (consider further generally paragraphs 0122-0130 regarding the ”allocation of packets to a particular quality of service” including wherein “a priority level queue can store packets allocated for processing by one or more processors”),
wherein the computing device includes a memory and a processor; the processor of the computing device is configured to perform a function of the scheduling module by a program stored in the memory; and the transmission module of the network device is composed of a hardware component for performing a function of the transmission module. (consider generally paragraphs 0053-0055 and 0057 regarding the composition of the “compute device” including a “processor” and “memory” containing “programs” and a “network interface controller” wherein “compute device 1202 may receive a data packet at its network interface controller (NIC). The compute device 1202 can store the data packet in local memory of the NIC or on a host device. The compute device 1202 can analyze the packet to determine if processing is to take place before the data packet is sent from the NIC to another component of the compute device 1202, such as a processor” such that “compute device 1202 can use either a local accelerator device (e.g., provided within compute device 1202) or a remote accelerator device (e.g., provided with accelerator sled 1204) to process any content of the data packet”) (consider also paragraph 0059 regarding the “accelerator device”)
wherein the transmission queue includes a single priority queue; a dequeuing order of the plurality of packets stored in the transmission queue is determined based on a transmission time of the transmission metadata; and the transmission module transmits the dequeued packet to the network through the transmission interface at the transmission time of the transmission metadata. (again, consider paragraph 0112, regarding a “process” that “can be used by any compute device or accelerator cluster, among others, to process received packets” wherein “An accelerator could use a command to determine how to process content and a priority of processing (e.g., priority queue allocation) could be determined based on priority.”) (consider further paragraph 0116 regarding “In a case where packets (or a portion thereof) are to be transmitted to a remote device (e.g., accelerator cluster), a network interface can select packet(s) for transmission from a queue based on bandwidth allocation. For example, packets from a queue can be selected based on first-in-first-out selection for transmission using an allocated bandwidth.”) (consider further paragraph 0120, “Various embodiments provide for an accelerator to set a QoS level of a packet transmitted to another device. Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet. A packet classifier that receives a response packet can determine a same level of QoS for accelerator use requests and responses to accelerator use based on packet classification.”) (consider further paragraph 0124, “Priority levels can be assigned to packets based on designations received in the packets or based on processing of received packets. For example, packet classifier 2020 can determine a priority or QoS of a packet received from network interface 2010 or network interface 2012 based on processing of the packet. For example, processing can include inspecting one or more of: the source IP address, the destination IP address, source MAC address, destination MAC address, VLAN tag contents, MPLS header, meta-data, and so forth. In some examples, event block 2008 can determine a priority of a packet received through network interface 2012 based on a specified priority in the received packet”)
Chang may be interpreted as not expressly teaching wherein the computing device and the network device are configured to support time sensitive networking (TSN), however, Chang does reasonably teach that the computing device and the network device are configured to support the time sensitive transmission of networking data. (again, consider paragraphs 0098-0099, 0107, 0112, 0114-0115, and 0120)
In an analogous art relating to transmission of packets using computing and network devices, Kasichainula taught that computing devices and network device may be configured to support time sensitive networking to the extent that such was well known and used in the art. (consider paragraphs 0001, 0003 and 0013-0014 regarding time sensitive networks and applications, time-sensitive networking as a field and standardized network infrastructure which provide “low latency and scalable gate control for time-sensitive networks, configuring multiple time-sensitive applications to share the same physical network link, and providing time-aware energy efficient network communication”) (consider also paragraphs 0011 and 0213 which teach various devices used with such time-sensitive network infrastructures including computing and network devices)
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of these references such that their combination includes every element as claimed. One skilled in the art could have combined the teachings by known methods such as integration of software routines with no changes to the operation of either reference such that, in combination, each element merely performs the same function as it does separately. Additionally, Examiner finds that, based on the references' analogous disclosure regarding transmission of packets using computing and network devices, further demonstrates that a combination of their features would have been known and obvious. Therefore, such a combination of the teachings of the references would have yielded nothing more than predictable results to one of ordinary skill in the art.
Regarding claim 6, the combined teachings of Chang and Kasichainula taught the packet processing system of claim 1.
Chang further taught wherein:
the network device further includes an offload accelerator (“accelerator device”); and the offload accelerator encrypts the plurality of dequeued packets using an encryption key and transmits the plurality of dequeued packets to the transmission module. (consider paragraph 0059, specifically “Accelerator device 1312 may be embodied as any type of device capable of performing certain computing tasks more quickly or more efficiently (e.g., lower time and/or lower power) relative to the processor 1302. For example, the accelerator device 1312 may be particularly well suited for tasks such as matrix multiplication, implementing a neural network, image processing, encryption, decryption, etc.”) (consider further paragraph 0105, specifically “Packets received at compute device 1702 could be determined to be processed using encryption. The packets can be encapsulated in an encapsulating packet and sent to a particular accelerator among accelerators 1752-0 to 1752-N in accelerator cluster 1750 for encryption. The packet can include meta-data that includes an identifier of an encryption algorithm to use and a key to use (or a location of a key). An accelerator among accelerators 1752-0 to 1752-N can perform encryption, form a packet with encrypted content, and send the encrypted content to compute device 1702 in the formed packet”)
Regarding claim 7, Chang taught a packet processing system (“high performance computing system”/”data center”) comprising:
a network device that transmits and receives a plurality of packets through a network; and a computing device that processes the plurality of packets, (consider Fig. 12 and paragraphs 0051-0052 regarding “compute devices and “accelerator devices” and also paragraph 0107, “For example, packets 1800, 1820, and 1840 can be used by a compute device or an accelerator device to communicate with another device and/or each other”)
wherein the network device is configured to generate a plurality of pieces of reception metadata related to a quality of service (QoS) of the plurality of packets, add the plurality of pieces of reception metadata to the plurality of packets, and transmit the plurality of packets to which the plurality of pieces of reception metadata are added to the computing device, and (consider paragraph 0093 wherein the “compute device” “can receive a packet from another device using interface 1700 and process any content of the packet (e.g., header and/or payload)”) (consider further paragraph 0107 regarding “packets” that “can be used by a compute device or an accelerator device to communicate with another device and/or each other” including a “header” containing “packet meta data” which “indicate how the network packet was processed or how the network packet is to be processed by the receiver” including “quality of service (QoS) designation, encryption parameters (e.g., algorithm to use and key), accelerator selection (e.g., address), accelerator command (e.g., actions an accelerator is to perform), next accelerator selection (e.g., address of next accelerator to select), and so forth”) (consider further paragraph 0133 wherein “a determination can be made as to a next stage processing for a packet” which “can be made in connection with processing of a packet (e.g., by inspection of a header, VLAN tag, MPLS header, meta-data, or payload) so that after the processing of the packet, there is to be additional processing to be performed on the packet or information determined based on the processing of the packet”)
the computing device is configured to process the plurality of packets according to a processing order determined based on the plurality of pieces of reception metadata. (consider paragraphs 0098-0099 wherein “prioritization of processing can occur based on flow identifiers, contexts, states, and requesting applications” such that “priority levels can be assigned based on input buffers or queues such that an input buffer or queue has a higher priority level than another input buffer or queue”) (consider further paragraph 0112, “An accelerator could use a command to determine how to process content and a priority of processing (e.g., priority queue allocation) could be determined based on priority.”) (consider further paragraphs 0114-0115 regarding “multiple Quality of Service (QoS) level queues to allocate packets for processing” wherein a “received packet is allocated to a QoS queue based on the determined QoS level” such that “a particular queue can be allocated for serving packets according to a particular QoS” which “can allow for prioritization of packet processing and can potentially reduce deadlock, provide traffic isolation, or packet priority management and reassignment” by “a packet classifier (e.g., flexible parsing unit)” which “can determine a QoS level of the received packet based on one or more of: a header of the received packet”) (consider also paragraph 0120, specifically “Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet”)
wherein:
the network device includes:
a reception interface that receives the plurality of packets through the network; a reception module that generates the plurality of pieces of reception metadata related to the QoS of the plurality of received packets and adds the plurality of pieces of generated reception metadata to the plurality of packets; and a reception queue that stores the plurality of packets and the plurality of pieces of reception metadata received from the reception module, (consider Fig. 15 regarding the “environment the compute device may establish”) (consider further paragraph 0092 wherein “an accelerator sled can indicate information in an encapsulating packet that can be used by a compute device. The compute device can use the information to determine how to interact with the accelerator sled. For example, information such as accelerator selection, accelerator command, flow identifier, priority, queue level, buffer level, and so forth can be used to determine how to process content of the packet or to interact with the remote device” wherein “an encapsulating packet can include a priority designation to indicate a priority level to assign a packet and corresponding task such that the receiver can use the priority level designation to allocate to the packet and corresponding task”) (consider further paragraph 0112 regarding a “process” that “can be used by any compute device or accelerator cluster, among others, to process received packets” wherein “At 1952, a packet is received from a remote device. For example, the remote device can be a compute device, accelerator cluster, accelerator sled, among other examples. At 1954, the packet can be processed. For example, the received packet can be processed to determine how to handle content of the packet. At 1956, information and/or commands provided in the received packet can be processed”) and
the computing device includes:
a network application that performs processing on the plurality of packets; and a policing module that transmits the plurality of packets stored in the reception queue to the network application according to the processing order determined based on the plurality of pieces of reception metadata. (again, consider paragraph 0112, regarding a “process” that “can be used by any compute device or accelerator cluster, among others, to process received packets” wherein “An accelerator could use a command to determine how to process content and a priority of processing (e.g., priority queue allocation) could be determined based on priority.”) (consider further paragraph 0117, “In a case where packets (or portions thereof) are to be processed by a local accelerator, the packet (or a pointer to the packet) can be transferred to the relevant local accelerator for processing. For example, packets allocated to a highest priority queue that are allocated for processing by the designated local accelerator A can be selected to be processed by local accelerator A. Next, packets allocated to a next highest priority queue that are allocated for processing by the designated local accelerator A can be selected to be processed by local accelerator A, and so forth”) (consider further paragraph 0120, “Various embodiments provide for an accelerator to set a QoS level of a packet transmitted to another device. Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet. A packet classifier that receives a response packet can determine a same level of QoS for accelerator use requests and responses to accelerator use based on packet classification.”) (consider further paragraph 0124, “Priority levels can be assigned to packets based on designations received in the packets or based on processing of received packets. For example, packet classifier 2020 can determine a priority or QoS of a packet received from network interface 2010 or network interface 2012 based on processing of the packet. For example, processing can include inspecting one or more of: the source IP address, the destination IP address, source MAC address, destination MAC address, VLAN tag contents, MPLS header, meta-data, and so forth. In some examples, event block 2008 can determine a priority of a packet received through network interface 2012 based on a specified priority in the received packet”),
wherein the computing device includes a memory and a processor; the processor of the computing device is configured to perform a function of the policing module by a program stored in the memory; and the reception module of the network device is composed of a hardware component for performing a function of the reception module. (consider generally paragraphs 0053-0055 and 0057 regarding the composition of the “compute device” including a “processor” and “memory” containing “programs” and a “network interface controller” wherein “compute device 1202 may receive a data packet at its network interface controller (NIC). The compute device 1202 can store the data packet in local memory of the NIC or on a host device. The compute device 1202 can analyze the packet to determine if processing is to take place before the data packet is sent from the NIC to another component of the compute device 1202, such as a processor” such that “compute device 1202 can use either a local accelerator device (e.g., provided within compute device 1202) or a remote accelerator device (e.g., provided with accelerator sled 1204) to process any content of the data packet”) (consider also paragraph 0059 regarding the “accelerator device”) (again, consider paragraph 0124, “For example, packet classifier 2020 can determine a priority or QoS of a packet received from network interface 2010 or network interface 2012 based on processing of the packet”)
wherein the reception queue includes a single priority queue; the processing order of the plurality of packets is determined based on information related to a QoS of the plurality of pieces of reception metadata; and the policing module transmits the plurality of packets to the network application according to the determined processing order. (again, consider paragraph 0112, regarding a “process” that “can be used by any compute device or accelerator cluster, among others, to process received packets” wherein “An accelerator could use a command to determine how to process content and a priority of processing (e.g., priority queue allocation) could be determined based on priority.”) (consider further paragraph 0120, “Various embodiments provide for an accelerator to set a QoS level of a packet transmitted to another device. Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet. A packet classifier that receives a response packet can determine a same level of QoS for accelerator use requests and responses to accelerator use based on packet classification.”) (consider further paragraph 0124, “Priority levels can be assigned to packets based on designations received in the packets or based on processing of received packets. For example, packet classifier 2020 can determine a priority or QoS of a packet received from network interface 2010 or network interface 2012 based on processing of the packet. For example, processing can include inspecting one or more of: the source IP address, the destination IP address, source MAC address, destination MAC address, VLAN tag contents, MPLS header, meta-data, and so forth. In some examples, event block 2008 can determine a priority of a packet received through network interface 2012 based on a specified priority in the received packet”) (consider further paragraph 0133 wherein “At 2102, a determination can be made as to a next stage processing for a packet. For example, the determination can be made in connection with processing of a packet (e.g., by inspection of a header, VLAN tag, MPLS header, meta-data, or payload) so that after the processing of the packet, there is to be additional processing to be performed on the packet or information determined based on the processing of the packet. Next stage processing can be performed by a local device, accelerator, host device processor, remote accelerator, network interface, and so forth” and that “a packet parser, accelerator, event block or other device or process can determine a next accelerator to process packet or destination of packet. Packet processing paths can be predefined or configurable. An example processing path includes…providing the packet to a host. Many other processing paths can be specified including whether a local or remote accelerator is to be used)”)
Chang may be interpreted as not expressly teaching wherein the computing device and the network device are configured to support time sensitive networking (TSN), however, Chang does reasonably teach that the computing device and the network device are configured to support the time sensitive transmission of networking data. (again, consider paragraphs 0098-0099, 0107, 0112, 0114-0115, and 0120)
In an analogous art relating to transmission of packets using computing and network devices, Kasichainula taught that computing devices and network device may be configured to support time sensitive networking to the extent that such was well known and used in the art. (consider paragraphs 0001, 0003 and 0013-0014 regarding time sensitive networks and applications, time-sensitive networking as a field and standardized network infrastructure which provide “low latency and scalable gate control for time-sensitive networks, configuring multiple time-sensitive applications to share the same physical network link, and providing time-aware energy efficient network communication”) (consider also paragraphs 0011 and 0213 which teach various devices used with such time-sensitive network infrastructures including computing and network devices)
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of these references such that their combination includes every element as claimed. One skilled in the art could have combined the teachings by known methods such as integration of software routines with no changes to the operation of either reference such that, in combination, each element merely performs the same function as it does separately. Additionally, Examiner finds that, based on the references' analogous disclosure regarding transmission of packets using computing and network devices, further demonstrates that a combination of their features would have been known and obvious. Therefore, such a combination of the teachings of the references would have yielded nothing more than predictable results to one of ordinary skill in the art.
Regarding claim 12, the combined teachings of Chang and Kasichainula taught the packet processing system of claim 7.
Chang further taught wherein:
the network device further includes an offload accelerator (“accelerator device”); and the offload accelerator is configured to decrypt an encrypted packet received from the network to generate a decrypted packet using an encryption key and transmits the decrypted packer to the transmission module. (consider paragraph 0059, specifically “Accelerator device 1312 may be embodied as any type of device capable of performing certain computing tasks more quickly or more efficiently (e.g., lower time and/or lower power) relative to the processor 1302. For example, the accelerator device 1312 may be particularly well suited for tasks such as matrix multiplication, implementing a neural network, image processing, encryption, decryption, etc.”) (consider further paragraphs 0069-0070 regarding the “decryption” by the “accelerator device” of “received” “encrypted” “data packets” received by the “data packet processor”) (consider further paragraph 0105, specifically “The packet can include meta-data that includes an identifier of an encryption algorithm to use and a key to use (or a location of a key).”) (consider further paragraphs 0126-0127 regarding the “decryption” of at least “certain parts” of the “packet”)
Claim(s) 4, 10, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang and Kasichainula as applied to claims 1 and 7 above, and in further view of US 20230061794 A1 to Livne et al. (“Livne”).
Regarding claim 4, the combined teachings of Chang and Kasichainula taught the packet processing system of claim 1.
Chang and Kasichainula may be interpreted as not expressly teaching wherein the transmission metadata for each packet includes a transmission time of the corresponding packet determined according to a scheduling algorithm and a policy to be applied when the corresponding packet fails to be transmitted during a time range indicated by the transmission time.
However, in an analogous art relating to time sensitive packet transmission, Livne taught that packets may include, within its metadata, a transmission time of the corresponding packet determined according to a scheduling algorithm and a policy to be applied when the corresponding packet fails to be transmitted during a time range indicated by the transmission time. (consider paragraph 0014, “In some examples, offload of a timing wheel or list management to network interface device 150 is independent of whether a policer stage is offloaded to network interface device 150 or performed by processor-executed software. A policing operation can include dropping packets of a flow with rates that are greater than a traffic policing rate”) (consider further paragraph 0025, “Packet metadata can be associated with a packet and stored in a linked list. Metadata information carried through the timing wheel can include one or more of: packet transmission timestamp, port identifier (ID), host identifier (HostID), Traffic Class, Function…and so forth”) (consider further paragraph 0030, specifically “Packet metadata can be enqueued into the fine-grained timing wheel if its timestamp is less than or equal to (FG-Set.sub.N−1) time window from dequeue time. Packet metadata can be enqueued into a coarse-grained time slot wheel if an associated timestamp is greater than the end of the time window of (FG-Set.sub.N−1). Packets with associated timestamps that are farther than the horizon can be dropped or put in the last timeslot of the horizon. Packets that arrive with a timestamp that is before the current nominal time can be put in its corresponding slot of a set in enqueue fine grain pool if slot time has not expired or put into the current nominal timeslot.”)
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of these references such that their combination includes every element as claimed. One skilled in the art could have combined the teachings by known methods such as integration of software routines with no changes to the operation of either reference such that, in combination, each element merely performs the same function as it does separately. Additionally, the Examiner finds that, based on the references' analogous disclosure regarding time sensitive packet transmission, further demonstrates that a combination of their features would have been known and obvious. Therefore, such a combination of the teachings of the references would have yielded nothing more than predictable results to one of ordinary skill in the art.
Regarding claim 10, the combined teachings of Chang and Kasichainula taught the packet processing system of claim 7.
Chang taught wherein the reception metadata for each packet includes information related to the QoS of a corresponding packet. (again, consider paragraph 0107 regarding “packets” that “can be used by a compute device or an accelerator device to communicate with another device and/or each other” including a “header” containing “packet meta data” which “indicate how the network packet was processed or how the network packet is to be processed by the receiver” including “quality of service (QoS) designation, encryption parameters (e.g., algorithm to use and key), accelerator selection (e.g., address), accelerator command (e.g., actions an accelerator is to perform), next accelerator selection (e.g., address of next accelerator to select), and so forth”) (again, consider paragraph 0124, “For example, packet classifier 2020 can determine a priority or QoS of a packet received from network interface 2010 or network interface 2012 based on processing of the packet”)
Chang and Kasichainula may be interpreted as not expressly teaching wherein the reception metadata for each packet further includes a reception time of a corresponding packet, however, Livne did teach these limitations. (consider paragraph 0014, “In some examples, offload of a timing wheel or list management to network interface device 150 is independent of whether a policer stage is offloaded to network interface device 150 or performed by processor-executed software. A policing operation can include dropping packets of a flow with rates that are greater than a traffic policing rate”) (consider further paragraph 0019, “Timing wheels 158 can include one or more linked lists that store identifiers or metadata of egress packets ordered based on their transmission timestamps. In some examples, egress packets whose transmission rate is not paced may not be identified in timing wheels 158. Transmit pipeline 152 can select packets in timing wheel 158 for transmission based on a packet timestamp. The timestamp can represent an earliest departure time of the packet, and use of timing wheels 158 can help ensure that packets are not transmitted until a timer value is greater than or equal to a packet's timestamp.”) (consider further paragraph 0025, “Packet metadata can be associated with a packet and stored in a linked list. Metadata information carried through the timing wheel can include one or more of: packet transmission timestamp, port identifier (ID), host identifier (HostID), Traffic Class, Function…and so forth”) (consider further paragraph 0032, specifically “New packets received with transmit timestamps within a time range associated with a fine grain set can be enqueued into a separate enqueue (ENQ) FG-Pool”)
The motivations regarding the obviousness of claim 7 also apply to claim 10, therefore, claim 10 is rejected under 35 USC § 103 as being unpatentable over the combined teachings of Chang, Kasichainula and Livne and the same rationale supporting the conclusion of obviousness.
Regarding claim 13, the combined teachings of Chang and Kasichainula taught the packet processing system of claim 7.
Chang and Kasichainula may be interpreted as not expressly teaching wherein the reception module detects a packet to be dropped among the plurality of packets based on a policing configuration, and drops the packet to be dropped without storing the packet to be dropped in the reception queue, however, Livne did teach these limitations. (consider paragraph 0014, “In some examples, offload of a timing wheel or list management to network interface device 150 is independent of whether a policer stage is offloaded to network interface device 150 or performed by processor-executed software. A policing operation can include dropping packets of a flow with rates that are greater than a traffic policing rate”) (consider further paragraph 0025, “Packet metadata can be associated with a packet and stored in a linked list. Metadata information carried through the timing wheel can include one or more of: packet transmission timestamp, port identifier (ID), host identifier (HostID), Traffic Class, Function…and so forth”) (consider further paragraph 0030, “Packet metadata can be enqueued into the fine-grained timing wheel if its timestamp is less than or equal to (FG-Set.sub.N−1) time window from dequeue time. Packet metadata can be enqueued into a coarse-grained time slot wheel if an associated timestamp is greater than the end of the time window of (FG-Set.sub.N−1). Packets with associated timestamps that are farther than the horizon can be dropped or put in the last timeslot of the horizon. Packets that arrive with a timestamp that is before the current nominal time can be put in its corresponding slot of a set in enqueue fine grain pool if slot time has not expired or put into the current nominal timeslot.”)
The motivations regarding the obviousness of claim 7 also apply to claim 13, therefore, claim 13 is rejected under 35 USC § 103 as being unpatentable over the combined teachings of Chang, Kasichainula and Livne and the same rationale supporting the conclusion of obviousness.
Regarding claim 14, the combined teachings of Chang and Kasichainula taught the packet processing system of claim 7.
Chang and Kasichainula may be interpreted as not expressly teaching wherein the reception module generates a stream ID for the plurality of packets using predetermined packet field information; the reception metadata includes the stream ID; and the policing module drops one or more received packets or controls a bandwidth for the one or more received packets based on the stream ID of the reception metadata, however, Livne did teach these limitations. (consider paragraphs 0001-0002 regarding “shaping” the “transmission” of “packets” “for multitudes of flows at prescribed rates for various network applications” wherein “[a] known approach to precise packet shaping is to use hierarchical timing wheels to schedule packets for a flow at precise time intervals using packet timestamps along with packet shaping using single or hierarchical aggregation of rates (consider further paragraph 0014, “In some examples, offload of a timing wheel or list management to network interface device 150 is independent of whether a policer stage is offloaded to network interface device 150 or performed by processor-executed software. A policing operation can include dropping packets of a flow with rates that are greater than a traffic policing rate”) (consider further paragraph 0015 regarding “flows” which “can be identified by a set of defined tuples and, for routing purpose, a flow is identified by the two tuples that identify the endpoints, e.g., the source and destination addresses”, “can be discriminated at a finer granularity by using N-tuples (e.g., source address, destination address, IP protocol, transport layer source port, and destination port)” wherein “[a] packet in a flow is expected to have the same set of tuples in the packet header”, and “can be identified by a combination of tuples (e.g., Ethernet type field, source and/or destination IP address, source and/or destination User Datagram Protocol (UDP) ports, source/destination TCP ports, or any other header field) and a unique source and destination queue pair (QP) number or identifier”) (consider further paragraph 0025, “Packet metadata can be associated with a packet and stored in a linked list. Metadata information carried through the timing wheel can include one or more of: packet transmission timestamp, port identifier (ID), host identifier (HostID), Traffic Class, Function…and so forth”) (consider further paragraph 0030, “Packet metadata can be enqueued into the fine-grained timing wheel if its timestamp is less than or equal to (FG-Set.sub.N−1) time window from dequeue time. Packet metadata can be enqueued into a coarse-grained time slot wheel if an associated timestamp is greater than the end of the time window of (FG-Set.sub.N−1). Packets with associated timestamps that are farther than the horizon can be dropped or put in the last timeslot of the horizon. Packets that arrive with a timestamp that is before the current nominal time can be put in its corresponding slot of a set in enqueue fine grain pool if slot time has not expired or put into the current nominal timeslot.”)
The motivations regarding the obviousness of claim 7 also apply to claim 14, therefore, claim 14 is rejected under 35 USC § 103 as being unpatentable over the combined teachings of Chang, Kasichainula and Livne and the same rationale supporting the conclusion of obviousness.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4, 6, 7, 10, and 12-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Furthermore, Applicant's arguments filed in the instant response with respect to certain aspects of the teachings of Chang have been fully considered but they are not persuasive.
Applicant generally argues that “With the amendment, Applicant respectfully submits that the combined references of Chang and Livne fail to teach or suggest at least the features of "wherein the computing device includes a memory and a processor; the processor of the computing device is configured to perform a function of the scheduling module by a program stored in the memory; and the transmission module of the network device is composed of a hardware component for performing a function of the transmission module, wherein the transmission queue includes a single priority queue; a dequeuing order of the plurality of packets stored in the transmission queue is determined based on a transmission time of the transmission metadata; and the transmission module transmits the plurality of dequeued packets to the network through the transmission interface at the transmission time of the transmission metadata" in currently amended claim 1.”
Specifically, Applicant argues that “However, Applicant respectfully asserts that Chang fails to teach or suggest at least the feature of the processor of the computing device configured to perform a function of the scheduling module by a program stored in the memory, as claimed, since the reference is silent on the feature.”
Examiner respectfully disagrees.
It is well within the scope of the teachings of the disclosed embodiments of Chang that the computing and networking devices include memory and processors which perform functions by a program stored in the memory and also hardware components for performing specific functions. (again, see paragraphs 0053-0055, 0057 and 0059)
Chang also enhanced these teachings at paragraph 0067 by teaching that “The various components of the environment 1500 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1500 may be embodied as circuitry or collection of electrical devices (e.g., a network interface manager circuit 1502, an accelerator controller circuit 1504, etc.). It should be appreciated that, in such embodiments the network interface manager circuit 1502, the accelerator controller circuit 1504, etc., may form a portion of one or more of the processor 1302, the I/O subsystem 1306, the network interface controller 1310, and/or other components of the compute device 1202. Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another. Further, in some embodiments, one or more of the components of the environment 1500 may be embodied as virtualized hardware components or emulated architecture, which may be established and maintained by the processor 1302 or other components of the compute device 1202.”
Chang also enhanced these teachings at paragraph 0087 by further teaching that “FIG. 16 depicts an example environment that the accelerator sled 1204 can establish. The illustrative environment 1600 includes a network interface manager 1602 and an accelerator controller 1604. The various components of the environment 1600 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1600 may be embodied as circuitry or collection of electrical devices (e.g., a network interface manager circuit 1602, an accelerator controller circuit 1604, etc.).”
Chang also makes clear at paragraph 0142 that “The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device)”
Applicant further alleges that “fundamental differences between the claimed invention and Chang” exist by listing various alleged features of Chang and the claimed invention’s alleged advantages over Chang. However, these additional features that Applicant alleges are not taught in Chang do not appear to be claimed. While limitations are interpreted in light of the specification, it is improper to import any limitations from the specification into the claims. See MPEP § 2111.01, subsection II. Examiner has applied Chang to the limitations as presented. Again, Examiner finds that Chang reasonably teaches the processor of the computing device being configured to perform a function of the scheduling module by a program stored in the memory.
Applicant is also reminded that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. As Examiner has found, the teachings of Chang clearly meet the claim as required.
Therefore, Examiner finds that the argument that Chang does not reasonably teach such embodiments as claimed to the extent that one skilled in the art could have contemplated such a structural computerized embodiment as claimed based on the disclosures of Chang and the knowledge of one skilled in the art regarding software and hardware embodiments and structural means to perform the functions taught in Chang to be unpersuasive.
Applicant also argues that “Applicant respectfully asserts that Chang fails to teach or suggest at least the feature of "wherein the transmission queue includes a single priority queue; a dequeuing order of the plurality of packets stored in the transmission queue is determined based on a transmission time of the transmission metadata; and the transmission module transmits the plurality of dequeued packets to the network through the transmission interface at the transmission time of the transmission metadata" in currently amended claim 1.”, originally found in now cancelled claim 5.
Applicant also similarly argues that there are “fundamental differences” which, again, Examiner finds to be unpersuasive as these additional features that Applicant alleges are not taught in Chang do not appear to be claimed and that the teachings of Chang meet the claim as required. To the extent that these arguments do argue that Chang does not teach the “single priority queue”, Chang further enhances the teachings found in the rejection within paragraph 0118 which taught that:
“In some cases, if packets assigned to a QoS level are allocated whereby some packets are to be processed by one or more local accelerators and other packets are to be processed by one or more remote accelerators, selection of packets can occur whereby packets for allocation to local accelerators are selected from queues by priority order and a selection of packets from queues for transmission can occur by priority order. Selection of packets for local accelerator processing and selection of packets for transmission to remote accelerators for processing can occur in parallel. In some cases, selection of packets for local processing or transmission for remote processing from a priority level queue can occur in series according to a first-in-first-out approach”.
Therefore, Chang does teach a “single” “priority queue” as equivalently specified in the claim and as previously shown in the rejection. Chang does not otherwise preclude the use of only one “priority queue” commensurate with what is claimed.
Furthermore, Applicant’s argument that “The transmission order determination disclosed in Chang is a method of simply "selecting" packets already residing in a queue based on bandwidth allocation or priority levels. Chang's metadata merely contains information regarding which queue or accelerator to use, but does not disclose specific time-control information as to exactly "when" a packet should be released”, Examiner submits that the claims only require that the ”transmission time” dictate the “dequeuing order” and “transmi[ssion]” of packets which, as previously explained, Chang taught “a "process" that "can be used by any compute device or accelerator cluster, among others, to process received packets" wherein "An accelerator could use a command to determine how to process content and a priority of processing (e.g., priority queue allocation) could be determined based on priority" (paragraph 0112) and that “Various embodiments provide for an accelerator to set a QoS level of a packet transmitted to another device. Accelerators could communicate to a remote device to override its normal determined QoS level and apply a specified QoS level, if permitted. A QoS level can be used to specify a queue to allocate to the response packet to specify a priority level of processing content of the packet” (paragraph 0120) and that “priority levels can be assigned to packets based on designations received in the packets or based on processing of received packets” such that “packet classifier 2020 can determine a priority or QoS of a packet” such that the “transmission time of the transmission metadata” is interpreted to be the time at which the packet is dequeued and transmitted based on its QoS/priority “level” which, as Chang teaches, at least involves “a priority of processing” which one skilled in the art would understand is time-based or, as Applicant puts it, exactly when a packet should be released based on its priority. Since this “transmission time” is “of” the “transmission metadata”, Examiner finds that Chang does teach these limitations. Applicant also argues that “Independent claim 7 is also patentable for at least the same reasons as independent claim 1, as the claim includes substantially the same features as claim 1”.
However, the only claim that was commensurate with claim 1 was now cancelled claim 15. Claim 7 actually recites limitations that are not found within claim 1 at least with regards to the “network device” and its “reception” limitations. Since Applicant does not specifically argue the limitations specifically found in claim 7, Examiner submits that Chang continues to teach these limitations inasmuch as they previously were included within now cancelled claims 8, 9, and 11 and will maintain the rejection of claim 7 over Chang with respect to these limitations.
With regards to claims 6, 10 and 12-14, Examiner finds no particular argument other than relying on their amended antecedent independent claim to which Examiner has fully responded to above. Therefore, Examiner will maintain the rejections of those claims under the teachings of Chang for the same reasons previously explained.
Conclusion
An updated search did not reveal additional prior art that is relevant to the claimed invention or to the broader disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G. C. Neurauter, Jr./Primary Examiner, Art Unit 2459
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