Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 1-6, 8-13, and 15-20 are now pending in the application under examination. Claims 7 and 14 have been canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0325919 in view of US 20100110748 A1.
With respect to claims 13 and 20, BHARGAVA teaches method and non-transitory computer-readable medium having program code recorded thereon to perform the method, comprising: transmitting a first set of data to a volatile memory via a shared memory bus; and transmitting a second set of data to a non-volatile memory via the shared memory bus concurrently with the transmitting of the first set of data (an integrated circuit device comprising: at least a first non-volatile memory array (304); at least a first volatile memory array (302); at least one non-volatile memory data bus (328) to transfer data from/to the non-volatile bitcells is in read/write operations; at least one volatile memory data bus (326) to transfer data to/from the volatile bitcells is in write/read operations; a shared data bus structure (330)) [Par. 0008-0009; Par. 0038-0039].
BHARGAVA fails to specifically describe, as claimed, the non-volatile memory and the volatile memory sharing an overlapping address space, the non-volatile memory associated with a first portion of the address space and the volatile memory associated with a second portion of the address space, such that transmitting to the non-volatile memory is via the first portion of the shared address space and transmitting to the volatile memory is via the second portion of the shared address space. However, BEST teaches hybrid, composite memory device having non-volatile and volatile memories with configurable overlapping address range between the volatile storage die and non-volatile storage die featuring a start-of-overlap address (SOO) represents the lowest address within the shadowed memory space (i.e., overlapped address range), and an end-of-overlap address (EOO) represents the highest address within the shadowed memory space [Fig. 6; Par. 0026]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the instant application to feature the address overlapping features of BEST into the hybrid memory circuit of BHARGAVA, in order to provide fast access as the need to regenerate and reload data into the DRAM device at boot-up (or wake-up) delays system readiness, and Flash memory devices suffer from relatively slow access times and write-limiting degradation, as taught by BEST [Par. 0002].
With respect to claim 1, apparatus, BHARGAVA teaches comprising: a shared data bus coupled to a non-volatile memory via a non-volatile memory data bus, and coupled to a volatile memory via a volatile memory data bus, the non-volatile memory data bus is a first subset of the shared data bus and the volatile memory data bus is a second subset of the shared data bus (an integrated circuit device comprising: at least a first non-volatile memory array; at least a first volatile memory array; at least one non-volatile memory data bus to transfer data from/to the non-volatile bitcells is in read/write operations; at least one volatile memory data bus to transfer data to/from the volatile bitcells is in write/read operations; a shared data bus structure coupled to the at least one non-volatile memory data bus and the at least one volatile memory data bus to enable a data transfer between the at least one external data port and either the at least one non-volatile memory data bus or at least one volatile memory data bus) [Par. 0008-0009; Par. 0035-0038; Par. 0042-0043]; and a memory controller coupled to the shared data bus and both the non-volatile memory and the volatile memory via the shared data bus (processor/controller to provide commands detecting a memory state or configuration or to provide control signals specifying physical memory address to write values to or read values from an addressable portion of memory) [Par. 0032-0033; Par. 0040-0042]. BHARGAVA fails to specifically teach “ the non-volatile memory includes a first mode register the volatile memory includes a second mode register the first mode register and the second mode register each indicate a configuration state of a plurality of configuration states: the memory controller is configured to toggle, via a configuration command, the first mode register and the second mode register between the plurality of configuration states and the memory controller, the volatile memory, and the non-volatile memory are configured to couple based on the configuration state indicated by the first mode register and the second mode register.
However, BEST teaches hybrid, composite memory device having non-volatile and volatile memories with data control/steering circuit used to implement the data control/steering interconnection indicating the direction of data flow during a memory access operation (read or write) and whether the volatile or non-volatile storage die is the target access path of the memory access [Par. 0020-0022] where memory storage implementation features configurable overlapping address range between the volatile storage die and non-volatile storage die and the overlapping addresses or shadowed memory space may be dynamically reconfigured using a run-time or production-time programmable register to hold start-of-overlap (SOO) and end-of-overlap (EOO) address values [Par. 0028-0029], i.e., storing, within register, a value that indicates configuration overlap defining range of address values that are common to the volatile storage die and the non-volatile storage die [Par. 0029]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the instant application to feature the address overlapping features with register mode based on the configuration state of BEST into the hybrid memory circuit of BHARGAVA, in order to enable access to the dedicated volatile storage or non-volatile storage regions provide fast access as needed, as taught by BEST [Par. 0002].
With respect to claim 2, BHARGAVA and BEST, combined, teach the apparatus, in which the non-volatile memory is multi- bit flash memory and the volatile memory is random access memory (RAM) (non-volatile memory featuring memory bitcells, phase change memory (PCM) bitcells, magnetic memory bitcells; and volatile memory featuring SRAM bitcells, DRAM bitcells) [BHARGAVA’s Fig. 2; Par. 0035; Par. 0008].
With respect to claim 3, BHARGAVA and BEST, combined, teach the apparatus, in which the non-volatile memory bus overlaps the volatile memory data bus in the shared data bus (shared data bus structure to transfer input values and output values between the shared bus structure and external terminals of the integrated circuit device, wherein the shared data bus structure coupled to the at least one non-volatile memory data bus and the at least one volatile memory data bus to enable a data transfer between the at least one external data port) [BHARGAVA’s Fig. 2; Par. 0035].
With respect to claim 4, BHARGAVA and BEST, combined, teach the apparatus, further comprising a volatile memory control bus coupled to the volatile memory and a non-volatile memory control bus coupled to the non-volatile memory, the volatile memory control bus not shared with the non-volatile memory control bus (at least one volatile memory bus configurable to transfer data signals to volatile memory bitcells and at least one non-volatile memory bus configurable to transfer stored values to non-volatile bitcells, wherein the volatile memory bus and the non-volatile memory bus, combined, implement a shared memory bus) [BHARGAVA’s Fig. 3A, 3B; Par. 0039].
With respect to claim 5, BHARGAVA and BEST, combined, teach the apparatus, in which the non-volatile memory and the volatile memory share an address space, the non-volatile memory associated with a first portion of the address space and the volatile memory associated with a second portion of the address space (hybrid storage embodiment, non-overlapping address ranges apply to each of the storage dice and to form the overall addressable range of the composite memory device) [BEST’s Fig. 2; Par. 0017]; at least one non-volatile memory data bus to transfer data from/to the non-volatile bitcells is in read/write operations; at least one volatile memory data bus to transfer data to/from the volatile bitcells is in write/read operations; a shared data bus structure to transfer values between the shared bus structure and external terminals of the integrated circuit device, wherein the shared data bus structure is coupled to the at least one non-volatile memory data bus and the at least one volatile memory data bus to enable a data transfer between the at least one external data port and either the at least one non-volatile memory data bus or at least one volatile memory data bus { BHARGAV’s Par. 0035-0039].
With respect to claim 6, BHARGAVA and BEST, combined, teach the apparatus, in which: the shared data bus includes a set of data lanes; the memory controller allocates a first portion of the set of data lanes to the non-volatile memory; and the memory controller allocates a second portion of the set of data lanes to the volatile memory (the volatile memory bus and the non-volatile memory bus, combined, implement a shared memory bus where at least one volatile memory data bus configurable to transfer data signals to volatile memory and at least one non-volatile memory data bus configurable to transfer stored values to non-volatile) [BHARGAVA’s Fig. 3A, 3B; Par. 0039].
With respect to claim 8, BHARGAVA and BEST, combined, teach the apparatus, in which: in a first configuration state of the plurality of configuration states, the non-volatile memory and the volatile memory share an address space, the non-volatile memory associated with a first part of the address space and the volatile memory associated with a second part of the address space; and in a second configuration state of the plurality of configuration states: the shared data bus includes a set of data lanes; the memory controller allocates a first portion of the set of data lanes to the non- volatile memory; and the memory controller allocates a second portion of the set of data lanes to the volatile memory (memory storage implementation featuring configurable overlapping address range between the volatile storage die and non-volatile storage die and the overlapping addresses or shadowed memory space may be dynamically reconfigured using a run-time or production-time programmable register to hold start-of-overlap (SOO) and end-of-overlap (EOO) address values; storing, within register, a value that indicates configuration overlap defining range of address values that are common to the volatile storage die and the non-volatile storage die) [BEST’s Par. 0028-0029].
With respect to claim 9, BHARGAVA and BEST, combined, teach the apparatus, in which the first mode register and the second mode register indicate a third configuration state, the third configuration state enabling direct data transfer between the non-volatile memory and the volatile memory via the shared data bus (while the shared interface to address dedicate shared-interface IC where the shared interface circuitry may be disposed on either a volatile memory die or non-volatile memory die) [BEST’s Par. 0016].
With respect to claim 10, BHARGAVA and BEST, combined, teach the apparatus, further comprising a clock line coupling a host to the non-volatile memory and the volatile memory, the clock line providing clock data to the non-volatile memory and the volatile memory, while the host is in a power saving mode and synchronous direct data transfer is occurring between the non-volatile memory and the volatile memory via the shared data bus (while the computing platform may be powered down, values stored in one or more volatile memory of non-volatile memory may be transferred to one or more non-volatile memory of volatile memory without accessing an external bus device) [BHARGAVA’s Par. 0088; Par. 0068]; (dedicated address lines to receive memory accessed addresses from the processor/memory controller, or the address information may be time-multiplexed onto the control lines or data lines by source-synchronous timing signals) BEST’s Par. 0014].
With respect to claim 11, BHARGAVA and BEST, combined, teach the apparatus, in which the volatile memory includes a plurality of volatile memory components, each volatile memory component coupled to the shared data bus via a respective volatile memory bus (memory access is directed to the dedicated volatile storage, dedicated non-volatile storage, or shadowed memory space within a configurable-overlap) [BEST’s Par. 0016].
With respect to claim 12, BHARGAVA and BEST, combined, teach the apparatus, in which each volatile memory component of the plurality of volatile memory components is random access memory (RAM) and includes a mode register (storing, within register, a value that indicates configuration overlap defining range of address values that are common to the volatile storage die and the non-volatile storage die) [BEST’s Par. 0029].
With respect to claim 15, BHARGAVA and BEST, combined, teach method of the apparatus in which transmitting to the non-volatile memory is via a first set of data lanes of the shared memory bus and transmitting to the volatile memory is via a second set of data lanes of the shared memory bus, the first set of data lanes being different than the second set of data lanes (first memory array comprising a plurality of volatile memory bitcells; a second memory array comprising a plurality of non-volatile memory bitcells; applying access signals to a plurality of wordlines for accessing the volatile memory bitcells in a first portion dedicated to applying access signals to the plurality of volatile memory bitcells and applying access signals to the non-volatile memory bitcells in a second portion dedicated to applying access signals to the plurality of non-volatile memory bitcells) [BHARGAVA’s Par. 0076; Par. 0124].
With respect to claim 16, BHARGAVA and BEST, combined, teach method of the apparatus in which the transmitting the second set of data to the non-volatile memory occurs simultaneously with the transmitting of the first set of data (address space partitioned into volatile memory and non-volatile memory components with partition dedicated for accessing non-volatile memory components and other be dedicated for accessing volatile memory components; the volatile memory in array of non-volatile memory maybe simultaneously accessed) [BHARGAVA Par. 0069-0071].
With respect to claim 17, BHARGAVA and BEST, combined, teach method of the apparatus further comprising transmitting a configuration command to a mode register hosted by one of the volatile memory or the non- volatile memory, the configuration command indicating a transmission technique to transmit and receive a third set of data via the shared memory bus (total size of the shadowed memory space to be fixed so that only the end-of-overlap or start-of- overlap addresses need be explicitly provided, with the unspecified bound determinable such that addresses below the start-of-overlap defined a dedicated volatile-storage region within the hybrid memory device, and addresses above the end-of-overlap define a dedicated nonvolatile region within the hybrid memory device [Fig. 6, Par. 0026].
With respect to claim 18, BHARGAVA and BEST, combined, teach method of the apparatus further comprising transmitting, from one of the volatile memory or the non-volatile memory, a fourth set of data directly to the other of the volatile memory or the non-volatile memory, via the shared memory bus (transfer control of data between a shared internal data bus and dedicated internal data buses associated with the volatile and non-volatile storage dice, respectively, the shared internal data bus being coupled to the external data interface, with the transfer being synchronous or asynchronous) [BEST’s Par. 0020].
With respect to claim 19, BHARGAVA and BEST, combined, teach method of the apparatus further comprising transmitting clock data to the volatile memory and the non-volatile memory via a shared clock line (control to dedicated address lines to receive memory read and write addresses from the memory controller, or the address information may be time-multiplexed onto the control lines or data lines, the data lines and/or control lines accompanied by source-synchronous timing signals such as clock signals [BEST’s Par. 0014].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
WO 9809221 A1 (MCWILLIAMS et al) teaching method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator to compare an address to a plurality of address spaces; and an address size indicator to indicate an address space of the plurality of address spaces to which the address corresponds.
WO 2019168610 A1 (CHORESH et al) teaching method including transferring a first portion of the codeword to a first physical non-volatile memory device via first set of a multiple input/output (I/O) lines of a bus to be stored at an indicated address in the first physical non-volatile memory device; transferring a second portion of the codeword, in parallel with the first portion of the codeword to a second physical non-volatile memory device via a second set of the plurality of I/O lines of the bus to be stored at the indicated address in the second physical non-volatile memory device; each of non-volatile memory devices is directly connected to a controller of the data storage system via a different set of input/output (I/O) data lines, wherein, the controller is configured to transmit a different portion or subset of received data to different physical non-volatile memory devices that form the logical non-volatile memory device, in parallel, using the set of I/O data lines that directly connect a non-volatile memory device to the controller of the data storage system.
US 20180059945 A1 (HELMICK et al) teaching a storage system comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices for improved data bus transmissions; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus.
WO 2019207282 A1 (BHARGAVA et al) teaching an integrated circuit device comprising: at least a first non-volatile memory array; at least a first volatile memory array; at least one non-volatile memory data bus to transfer data from/to the non-volatile bitcells is in read/write operations; at least one volatile memory data bus to transfer data to/from the volatile bitcells is in write/read operations; a shared data bus structure.
Contact Information
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/PIERRE MICHEL BATAILLE/ Primary Examiner, Art Unit 2138