Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the communication filed on 06/12/2024.
Claims 1-20 are under examination.
The Information Disclosure Statements filed on 07/21/2024 has been entered and considered.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 12-20 are rejected under 35 U.S.C. 101 because the claimed invention is not directed to patent eligible subject matter. Based upon consideration of all of the relevant factors with respect to the claim as a whole, claim(s) 12-20 are determined to be directed to an abstract idea. The rationale for this determination is explained below: Claims 12-20 recite a cryptographic method. However, these claims do not recite a machine/hardware to execute the said method. Therefore, claim(s) 12-20 are determined to be directed to an abstract idea.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Schneider (US 2009/0220083 A1) and Lablans (US 2016/0211971 A1).
Regarding claim 1, Schneider discloses A cryptographic device, comprising: a memory enabled to store data in and to retrieve data from, including instructions; a processor configured to retrieve instructions from the memory [par. 0080, memory, par. 0056, “encryption logic component 240 is configured as a component of a stream cipher, and performs an invertible operation on the plaintext or ciphertext using the received pseudorandom bit sequences] to perform the steps:; performing by the processor of an array-vector multiplication over a finite field GF(n) of an n-state k by k array [[based on the k by k n-state base transition array in canonical form]] with a word of k n-state elements to generate an output set of k n-state elements [par. 0050, multiplicative inverse of over the field GF(2.sup.n), par. 0056, “the invertible operation may include multiplication over a finite field of even characteristic, or some other mathematical operation that intermingles the received bit sequences with the plaintext or ciphertext”, par. 0034, “A shift register is an array of single bit memory elements” (array vector)]; and transmitting by the processor of a cryptographic message based on the output set of k n-state elements, with k and integer greater than 4 and n and integer greater than 15 [par. 0025, “message source 205 generates application level messages that are encrypted by cipher 215 before they are transmitted over a network to message destination 220, par. 0054, LFSR use 5 bits (k greater than 4, and n = 32), par. 0070, “ a third bit sequence is generated by multiplying the first bit sequence with the second bit sequence over a finite field of even characteristic, modulo a fixed primitive polynomial. In one embodiment, the fixed primitive polynomial has a degree of y and generates the extension field GF(2.sup.y)”, par. 0072, “the third bit sequence includes one or more sub-keys that are combined with data by a block cipher. In another embodiment, the third bit sequence is part of a pseudorandom bit stream that is combined with data by a stream cipher. At block 430, an encrypted message is output”].
Schneider does not explicitly disclose generating by the processor of a k by k n-state base transition array in canonical form defined by a primitive polynomial of degree k, the k by k n-state base transition array in canonical form having only one row or column that is determined by n-state coefficients of the primitive polynomial of degree k or retrieving from the memory the pre-generated k by k n-state base transition array in canonical form.
However Lablans teaches generating by the processor of a k by k n-state base transition array in canonical form defined by a primitive polynomial of degree k, the k by k n-state base transition array in canonical form having only one row or column that is determined by n-state coefficients of the primitive polynomial of degree k or retrieving from the memory the pre-generated k by k n-state base transition array in canonical form [par. 0012, “activating matrix sc3=[1 2 3;2 3 1;3 1 2] or matrix sc4=[1 2 3 4;2 3 4 1;3 4 1 2;4 1 2 3] or any other n-state matrix that is used as a switching device. One dimensional matrices or vectors are used to implement inverters such as: inv2=[2 1]; inv3=[3 2 1], inv=[4 3 2 1] or any other inverter” (matrix sc4 is a 4x4 n-state transition array in canonical form), par. 0125, “Maximum length n-state generating shift registers with k register elements with feedback generating n.sup.k-1 n-state symbols are represented by primitive n-state polynomials of degree k: g(X)=g0+g1*X+g2*X.sup.2+ . . . +gk*X.sup.k. The coefficients gk are multiplications over GF(n)”, par. 0158, “a series of binary or nonbinary sequence generator configurations is created and each is provided with a unique code”].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans into the teaching of Schneider with the motivation such that one dimensional matrices or vectors are used to implement inverters as taught by Lablans [Lablans: par. 0012].
Regarding claim 2, the rejection of claim 1 is incorporated.
Schneider further teaches the cryptographic message is generated by a cryptographic operation selected from the group consisting of an encryption, a decryption and a hashing operation [par. 0072, “the third bit sequence is part of a pseudorandom bit stream that is combined with data by a stream cipher. At block 430, an encrypted message is output”].
Regarding claim 3, the rejection of claim 1 is incorporated.
Lablans further teaches the n-state k by k array is a power of the k by k n-state base transition array over GF(n) and the n-state k by k array has an inverse k by k n-state array based on a canonical k by k n-state inverse base array determined from only the n-state coefficients of the primitive polynomial of degree k [[par. 0012, “activating matrix sc3=[1 2 3;2 3 1;3 1 2] or matrix sc4=[1 2 3 4;2 3 4 1;3 4 1 2;4 1 2 3] or any other n-state matrix that is used as a switching device. One dimensional matrices or vectors are used to implement inverters such as: inv2=[2 1]; inv3=[3 2 1], inv=[4 3 2 1] or any other inverter”, par. 0125, “The coefficients gk are multiplications over GF(n)”, par. 0132, “The input of 1501 is the input to the shift register and to a 3-state detector switching function ‘det’ via an inverter inv0.sup.−1 which inverses inverter inv0 in FIG. 14. The inverse of inverter [2 1 0] is itself [2 1 0]. Applying [2 1 0] twice generates [0 1 2]”, par. 0142, “One can repeat the above construction of n-state sequence generators and corresponding sequence detectors for any n>2. The simplest way is to use n being a prime number or an extension field of a prime number such as GF(2.sup.k)”].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans into the teaching of Schneider with the motivation such that one dimensional matrices or vectors are used to implement inverters as taught by Lablans [Lablans: par. 0012].
Regarding claim 4, the rejection of claim 2 is incorporated.
Lablans further teaches the word of k n-state elements represents a sequence of at least 127 bits [[par. 0233, a 1023 bit sequence with 10 bits words].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans into the teaching of Schneider with the motivation such that one dimensional matrices or vectors are used to implement inverters as taught by Lablans [Lablans: par. 0012].
Regarding claim 5, the rejection of claim 2 is incorporated.
Schneider further teaches the n-state k by k array is applied in a one-way manner, wherein the cryptographic message is generated as part of a cryptographic operation selected from the group consisting of ChaCha20 encryption, Advanced Encryption Standard-Galois Counter Mode (AES-GCM) encryption, Secure Hashing Standard (SHS FIPS 180-4) hashing, MD5 hashing and SHA-3 (FIPS 202) defined hashing and Keccak defined hashing [par. 0061, “encryption logic component 240 is configured as a component of a block cipher. Encryption logic component 240 may receive a preset number of pseudorandom bit sequences from value randomizer 235. These pseudorandom bit sequences may then be used as sub-keys for the block cipher. The block cipher may then encrypt or decrypt data according to block cipher algorithms such as DES, AES, IDEA, etc.”, par. 0021, Galois Field].
Regarding claim 6, the rejection of claim 2 is incorporated.
Schneider further disclose wherein the cryptographic message is generated as part of a cryptographic operation selected from the group consisting of ChaCha20 encryption, Advanced Encryption Standard-Galois Counter Mode (AES-GCM) encryption [par. 0061, “encryption logic component 240 is configured as a component of a block cipher. Encryption logic component 240 may receive a preset number of pseudorandom bit sequences from value randomizer 235. These pseudorandom bit sequences may then be used as sub-keys for the block cipher. The block cipher may then encrypt or decrypt data according to block cipher algorithms such as DES, AES, IDEA, etc.”, par. 0021, Galois Field].
Lablans further teaches the n-state k by k array is applied in a reversible manner [par. 0233, “An n-state logic has n.sup.n inverters of which n! (factorial) are reversible. Binary logic has 4 inverters of which 2 are reversible”].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans into the teaching of Schneider with the motivation such that one dimensional matrices or vectors are used to implement inverters as taught by Lablans [Lablans: par. 0012].
Regarding claim 10, the rejection of claim 2 is incorporated.
Lablans further teaches the array-vector multiplication over the finite field GF(n) is applied to a series of at least 1000 bits [par. 0125, “Binary extension fields GF(n=2.sup.k) are known, wherein the n-state symbols are formed by words of k bits…”, par. 0233, a 1023 bit sequence with 10 bits words].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans into the teaching of Schneider with the motivation such that one dimensional matrices or vectors are used to implement inverters as taught by Lablans [Lablans: par. 0012].
Regarding claim 11, the rejection of claim 2 is incorporated.
Lablans further teaches the power of the k by k n-state base transition array over GF(n) is at least 50 [par. 0095, “When the LFSR has p shift register elements the maximum length is n.sup.p-1 n-state symbols”, par. 0125, “Binary extension fields GF(n=2.sup.k) are known, wherein the n-state symbols are formed by words of k bits…”, par. 0233, a 1023 bit sequence with 10 bits words].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans into the teaching of Schneider with the motivation such that one dimensional matrices or vectors are used to implement inverters as taught by Lablans [Lablans: par. 0012].
Regarding claim 12, it recites limitations like claim 1. The reason for the rejection of claim 1 is incorporated herein.
Regarding claim 13, it recites limitations like claim 2. The reason for the rejection of claim 2 is incorporated herein.
Regarding claim 14, it recites limitations like claim 3. The reason for the rejection of claim 3 is incorporated herein.
Regarding claim 15, it recites limitations like claim 4. The reason for the rejection of claim 4 is incorporated herein.
Regarding claim 16, it recites limitations like claim 5. The reason for the rejection of claim 5 is incorporated herein.
Regarding claim 17, it recites limitations like claim 6. The reason for the rejection of claim 6 is incorporated herein.
Claims 7-9 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over 1-6 and 10-17 as applied to claims Schneider (US 2009/0220083 A1) and Lablans (US 2016/0211971 A1) above, and further in view of Lablans (US 2009/0092250 A1).
Regarding claim 7, the rejection of claim 1 is incorporated
Schneider discloses the array-vector multiplication over the finite field GF(n).
They do not explicitly disclose the array-vector multiplication over the finite field GF(n) is Finite Lab-Transform (FLT) modified, with the n-state k by k array being inverted by a reversing reversible n-state inverter into an inverted n-state k by k array and one or more computer functions characterized as an operation over finite field GF(n) and applied in the array-vector multiplication are modified by the FLT, the FLT being characterized as a modification of an n-state computer operation having at least two n-state input operands and an output, each of the at least two n-state input operands being inverted by an n-state reversible inverter before being processed by the n-state computer operation and to generate an n-state signal on the output, the n-state signal on the output being inverted with the reversing reversible n-state inverter.
However Lablans (US 2009/0092250 A1) teaches the array-vector multiplication over the finite field GF(n) is Finite Lab-Transform (FLT) modified, with the n-state k by k array being inverted by a reversing reversible n-state inverter into an inverted n-state k by k array and one or more computer functions characterized as an operation over finite field GF(n) and applied in the array-vector multiplication are modified by the FLT, the FLT being characterized as a modification of an n-state computer operation having at least two n-state input operands and an output, each of the at least two n-state input operands being inverted by an n-state reversible inverter before being processed by the n-state computer operation and to generate an n-state signal on the output, the n-state signal on the output being inverted with the reversing reversible n-state inverter [par. 0316, “an n-state symbol can be represented by a plurality of k-state signals. For instance an 8-state symbol can be represented by at least 2-state symbols. The finite field GF(n=2.sup.p) may be an extension of the finite binary field GF(2). If the field GF(2) is defined in using 2-valued arithmetic, then the field GF(n=2.sup.p) may be defined using similar operations to define elements in GF(n=2.sup.p) wherein a symbol in GF(n=2.sup.p) may be represented by a word of p bits”, par. 0320, “FIG. 58 shows a 16-state LFSR based scrambler 5800 in binary form. Its 16-state form is shown in FIG. 59. The scrambler 5800 is comprised of 4 parallel LFSRs 5801, 5802, 5803 and 5804. A 16-state symbol is represented by a binary word of 4 bits. Each word can be stored in parallel in shift register elements 5805, 5806 and 5807 each able to store and shift 4 bits”, par. 0321, “One can imagine that such a scrambler can be used to scramble a symbol for a QAM-16 system. A/D and D/A converters can be used to create the actual 16 valued symbols or to create a 4 bit word in order to process the 16-state symbol in binary form”, par. 0324, “Such an optimal LFSR usually can be realized by inserting an n-state (in this case a 16-state) reversible inverter. Such a reversible inverter may be an n-valued multiplier over GF(n)”].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans (US 2009/0092250 A1) into the teaching of Schneider (US 20090220083 A1) and Lablans (US 2016/0211971 A1) with the motivation of performing a cryptographic function using the routines from the word sized finite field to which the respective finite field corresponding to said selected elliptic curve is assigned as taught by Lablans (US 2009/0092250 A1) [Lablans (US 2009/0092250 A1): col. 5, lines 32-35].
Regarding claim 8, the rejection of claim 7 is incorporated.
Schneider further disclose the array-vector multiplication over the finite field GF(n) is applied to a word of k n-state elements in at least one of a cryptographic operation selected from the group consisting of Advanced Encryption Standard (AES), Advanced Encryption Standard-Galois Counter Mode (AES-GCM NIST SP 800-38D), ChaCha20 (RFC 7539) , Secure Hashing Standard (SHS FIPS 180-4) , MD5 (RFC 1321 ), SHA-3 (FIPS 202) [par. 0061, “encryption logic component 240 is configured as a component of a block cipher. Encryption logic component 240 may receive a preset number of pseudorandom bit sequences from value randomizer 235. These pseudorandom bit sequences may then be used as sub-keys for the block cipher. The block cipher may then encrypt or decrypt data according to block cipher algorithms such as DES, AES, IDEA, etc.”].
Regarding claim 9, the rejection of claim 1 is incorporated
Schneider discloses the array-vector multiplication over the finite field GF(n).
They do not explicitly disclose the array-vector multiplication over the finite field GF(n) is applied to FLT an p-state operation with p=n^k in a cryptographic operation.
However Lablans (US 2009/0092250 A1) teaches the array-vector multiplication over the finite field GF(n) is applied to FLT an p-state operation with p=n^k in a cryptographic operation [par. 0050, multiplicative inverse of over the field GF(2.sup.n), par. 0056, “Alternatively, the invertible operation may include multiplication over a finite field of even characteristic, or some other mathematical operation that intermingles the received bit sequences with the plaintext or ciphertext”].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans (US 2009/0092250 A1) into the teaching of Schneider (US 20090220083 A1) and Lablans (US 2016/0211971 A1) with the motivation of performing a cryptographic function using the routines from the word sized finite field to which the respective finite field corresponding to said selected elliptic curve is assigned as taught by Lablans (US 2009/0092250 A1) [Lablans (US 2009/0092250 A1): col. 5, lines 32-35].
Regarding claim 18, it recites limitations like claim 7. The reason for the rejection of claim 7 is incorporated herein.
Regarding claim 19, it recites limitations like claim 8. The reason for the rejection of claim 8 is incorporated herein.
Regarding claim 20, the rejection of claim 19 is incorporated
Lablans (US 2009/0092250 A1) further teaches a result of the FLTed array-vector multiplication over the finite field GF(n) that is applied to the word of k n-state symbols is processed by an n-state commutative involution not being an operation over GF(n) [par. 0050, multiplicative inverse of over the field GF(2.sup.n), par. 0056, “the invertible operation may include multiplication over a finite field of even characteristic, or some other mathematical operation that intermingles the received bit sequences with the plaintext or ciphertext”].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Lablans (US 2009/0092250 A1) into the teaching of Schneider (US 20090220083 A1) and Lablans (US 2016/0211971 A1) with the motivation of performing a cryptographic function using the routines from the word sized finite field to which the respective finite field corresponding to said selected elliptic curve is assigned as taught by Lablans (US 2009/0092250 A1) [Lablans (US 2009/0092250 A1): col. 5, lines 32-35].
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
US 3962539 A Product block cipher system for data security
US 4165444 A Apparatus for electronic encypherment of digital data
US 5995539 A Method and apparatus for signal transmission and reception
US 6111952 A Asymmetrical cryptographic communication method and portable object therefore
US 20120121084 A1 PUBLIC KEY ENCRYPTION SYSTEM USING ERROR CORRECTING CODES
US 6052704 A Exponentiation circuit and inverter based on power-sum circuit for finite field GF(2.sup.m)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON CHIANG whose telephone number is (571)270-3393. The examiner can normally be reached on 9 AM to 6 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn Feild can be reached on (571) 272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON CHIANG/Primary Examiner, Art Unit 2431