DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 29, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6-8, 10-11, 13-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Donley et al. (Pub. No. US 2012/0159080) in view of Steely, JR. et al. (Pub. No. US 2016/0170880).
Claim 1:
Donley et al. disclose a device comprising:
a storage media [pars. 0030-0031; Table 1 – Main memory]; and
a processor comprising:
a cache hierarchy comprising a first cache, a second cache, and a third cache [fig. 1 – local cache, shared cache, high-level cache]; wherein the first cache and the third cache are organized in an inclusive cache hierarchy; and wherein the second cache is an exclusive cache to the inclusive cache hierarchy [fig. 1; par. 0018 – Local cache and high-level cache may be inclusive and shared cache may be exclusive. (“Like a shared cache 113, the high level cache 120 may be exclusive, such that it does not contain the data stored in the shared caches 113. The high level cache 120 may, alternatively, be inclusive, such that it contains the data stored in the shared caches 113 of the processing nodes 110. However, inclusiveness may limit the effectiveness of the high level cache 120, where, for instance, half of an 8 Mega Byte (MB) high level cache 120 may be dedicated to replicating the data of the shared caches 113 of the four processing nodes 110, each of a 1 MB size. In that instance, only 4 MB would be left for caching purposes in the high-level cache 120. Therefore, more of the resources of a high-level cache 120 may be available when the cache is exclusive and it does not replicate the data stored in lower-level caches.”)]; and
a cache directory [par. 0036 – “Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”].
However, Donley et al. do not specifically disclose,
wherein the cache directory comprises presence information and state information for data found in the first cache and the third cache organized in the inclusive cache hierarchy and the second cache exclusive to the inclusive cache hierarchy, wherein the presence information comprises an indication of at least one of the first cache, the second cache, and the third cache.
In the same field of endeavor, Steely, JR. et al. disclose,
wherein the cache directory comprises presence information and state information for data found in the first cache and the third cache organized in the inclusive cache hierarchy and the second cache exclusive to the inclusive cache hierarchy, wherein the presence information comprises an indication of at least one of the first cache, the second cache, and the third cache [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Donley et al. to include a cache directory, as taught by Steely, JR et al., in order to provide a central means for locating all the data across caches in the system.
Claim 2 (as applied to claim 1 above):
Donley et al. disclose,
wherein the first cache is a first level cache, the second cache is a second level cache, and the third cache is a last level cache [fig. 1 – local cache, shared cache, high-level cache].
Claim 3 (as applied to claim 1 above):
Steely, JR. et al. disclose,
wherein an entry of the cache directory comprises an indicator of a cache where data is present in the cache hierarchy [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”].
Claim 4 (as applied to claim 1 above):
Donley et al. disclose, wherein the processor performs operations comprising:
searching the first cache for data; searching the second cache for the data; and searching the cache directory for the data [par. 0036 – The cache hierarchy and directory are searched for the data. Data that is not found is returned from system memory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 6 (as applied to claim 1 above):
Donley et al. disclose, wherein the processor performs operations comprising:
requesting data [fig. 3; pars. 0020-0024 – “In the example shown in FIG. 3, a request for data in a memory address 310 is received by the cache 300. The memory address 310 is 32 bits in length, of which 19 bits are for the tag 311, 10 bits are for the index 312, and 3 bits are for the byte offset 313.”];
determining that the data is located in the cache directory [fig. 1; par. 0036 – Directory is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and
determining a location of the data in the cache hierarchy based on an entry in the cache directory [fig. 1; par. 0036 – Data is located by searching the directory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 7 (as applied to claim 1 above):
Donley et al. disclose, wherein the processor performs operations comprising:
requesting data [fig. 3; pars. 0020-0024 – “In the example shown in FIG. 3, a request for data in a memory address 310 is received by the cache 300. The memory address 310 is 32 bits in length, of which 19 bits are for the tag 311, 10 bits are for the index 312, and 3 bits are for the byte offset 313.”];
determining that the data is not found in the cache directory [fig. 1; par. 0036 – Directory is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and
retrieving the data from the storage media [fig. 1; par. 0036 – Data is returned from system memory when not present in the cache hierarchy. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 8 (as applied to claim 1 above):
Donley et al. disclose the device, further comprising
a fourth cache [fig. 1 – shared cache 113D];
wherein the first cache is a first level cache [fig. 1 – local cache 112A];
wherein the second cache and the fourth cache are second level caches [fig. 1 – shared caches 113A and 113D];
wherein the third cache is a last level cache [fig. 1 – high-level cache 120];
wherein the fourth cache is an exclusive cache [fig. 1; par. 0018 – Shared cache may be exclusive. (“Like a shared cache 113, the high level cache 120 may be exclusive, such that it does not contain the data stored in the shared caches 113. The high level cache 120 may, alternatively, be inclusive, such that it contains the data stored in the shared caches 113 of the processing nodes 110. However, inclusiveness may limit the effectiveness of the high level cache 120, where, for instance, half of an 8 Mega Byte (MB) high level cache 120 may be dedicated to replicating the data of the shared caches 113 of the four processing nodes 110, each of a 1 MB size. In that instance, only 4 MB would be left for caching purposes in the high-level cache 120. Therefore, more of the resources of a high-level cache 120 may be available when the cache is exclusive and it does not replicate the data stored in lower-level caches.”)]; and
wherein the processor performs operations comprising:
searching the cache directory for data [fig. 1; par. 0036 – Directory is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)];
determining that the data is found in a second level cache [fig. 1; par. 0036 – Directory is located. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and
searching the fourth cache for the data [fig. 1; par. 0036 – Data is returned from the cache. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 10:
Donley et al. disclose a method implemented by a processor comprising cache media; wherein the cache media comprises a cache hierarchy and a cache directory [fig. 1; par. 0036 – local cache, shared cache, high-level cache and cache directory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and wherein the method comprises:
receiving a request to access data [fig. 3; pars. 0020-0024 – “In the example shown in FIG. 3, a request for data in a memory address 310 is received by the cache 300. The memory address 310 is 32 bits in length, of which 19 bits are for the tag 311, 10 bits are for the index 312, and 3 bits are for the byte offset 313.”];
determining, using the cache directory, that the data is located in the cache hierarchy, wherein the cache hierarchy comprises one or more inclusive caches and one or more exclusive caches, wherein the cache hierarchy is organized in a hierarchy structure [fig. 1; pars. 0018, 0036 – Local cache and high-level cache may be inclusive and shared cache may be exclusive. The directory may be used to locate data in the cache hierarchy. (“Like a shared cache 113, the high level cache 120 may be exclusive, such that it does not contain the data stored in the shared caches 113. The high level cache 120 may, alternatively, be inclusive, such that it contains the data stored in the shared caches 113 of the processing nodes 110. However, inclusiveness may limit the effectiveness of the high level cache 120, where, for instance, half of an 8 Mega Byte (MB) high level cache 120 may be dedicated to replicating the data of the shared caches 113 of the four processing nodes 110, each of a 1 MB size. In that instance, only 4 MB would be left for caching purposes in the high-level cache 120. Therefore, more of the resources of a high-level cache 120 may be available when the cache is exclusive and it does not replicate the data stored in lower-level caches.” … “Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)],
wherein the one or more inclusive caches comprise a first level cache and a third level cache, wherein the one or more exclusive caches comprise a second level cache exclusive to an inclusive cache hierarchy [fig. 1; par. 0018 – Local cache and high-level cache may be inclusive and shared cache may be exclusive. (“Like a shared cache 113, the high level cache 120 may be exclusive, such that it does not contain the data stored in the shared caches 113. The high level cache 120 may, alternatively, be inclusive, such that it contains the data stored in the shared caches 113 of the processing nodes 110. However, inclusiveness may limit the effectiveness of the high level cache 120, where, for instance, half of an 8 Mega Byte (MB) high level cache 120 may be dedicated to replicating the data of the shared caches 113 of the four processing nodes 110, each of a 1 MB size. In that instance, only 4 MB would be left for caching purposes in the high-level cache 120. Therefore, more of the resources of a high-level cache 120 may be available when the cache is exclusive and it does not replicate the data stored in lower-level caches.”)]; and
retrieving the data from the cache hierarchy [par. 0036 – Data may be returned from the cache hierarchy rather than from system memory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
However, Donley et al. do not specifically disclose,
wherein the cache directory comprises presence information and state information for data found in the one or more inclusive caches and the one or more exclusive caches and wherein the presence information comprises an indication of a level of cache,
In the same field of endeavor, Steely, JR. et al. disclose,
wherein the cache directory comprises presence information and state information for data found in the one or more inclusive caches and the one or more exclusive caches and wherein the presence information comprises an indication of a level of cache [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”],
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Donley et al. to include a cache directory, as taught by Steely, JR et al., in order to provide a central means for locating all the data across caches in the system.
Claim 11 (as applied to claim 10 above):
Donley et al. disclose, wherein the cache hierarchy comprises the first level cache, the second level cache, and third level cache [fig. 1 – local cache, shared cache, high-level cache]; and
wherein determining that the data is located in the cache hierarchy comprises:
searching the first level cache for the data; searching the second level cache for the data; searching the cache directory for the data; determining, by the cache directory, that the data is located at the third level cache; and searching the third level cache for the data [par. 0036 – The cache hierarchy and directory are searched for the data. Data that is not found is returned from system memory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 13 (as applied to claim 10 above):
Donley et al. disclose, wherein the method further comprises:
determining that the data is located in the cache directory [fig. 1; par. 0036 – Directory is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and
determining a location of the data in the cache hierarchy based on the cache directory [fig. 1; par. 0036 – Data is located by searching the directory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 14 (as applied to claim 10 above):
Steely, JR. et al. disclose,
wherein the cache directory comprises an indicator of a cache where the data is present in the cache hierarchy [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”].
Claim 15 (as applied to claim 10 above):
Donley et al. disclose,
wherein the one or more inclusive caches comprises a first cache and a third cache [fig. 1 - local caches];
wherein the one or more exclusive caches comprises a second cache and a fourth cache [fig. 1 – shared caches];
wherein the first cache is the first level cache [fig. 1 – local cache];
wherein the second cache and the fourth cache are second level caches [fig. 1 – shared caches]; and
wherein determining that the data is located in the cache hierarchy comprises:
searching the first cache for the data [fig. 1; par. 0036 – Cache hierarchy is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)];
searching the second cache and the cache directory for the data [fig. 1; par. 0036 – Directory is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)];
determining, by the cache directory, that the data is located at a different cache at a second level cache [fig. 1; par. 0036 – Data is located. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and
searching the fourth cache for the data [fig. 1; par. 0036 – Data is returned from the cache. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 16 (as applied to claim 10 above):
Steely, JR. et al. disclose, wherein determining that the data is located in the cache hierarchy comprises:
searching the cache directory for the data [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”]; and
determining a location of the data based on an indicator of a cache where the data is present in the cache hierarchy [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”].
Claim 17:
Donley et al. disclose a method implemented by a processor comprising cache media; wherein the cache media comprises a cache hierarchy and a cache directory [fig. 1; par. 0036 – local cache, shared cache, high-level cache and cache directory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and wherein the method comprises:
receiving a request for data [fig. 3; pars. 0020-0024 – “In the example shown in FIG. 3, a request for data in a memory address 310 is received by the cache 300. The memory address 310 is 32 bits in length, of which 19 bits are for the tag 311, 10 bits are for the index 312, and 3 bits are for the byte offset 313.”];
determining, using the cache directory, that the data is not present in the cache hierarchy, wherein the cache hierarchy comprises one or more inclusive caches and one or more exclusive caches, and wherein the cache hierarchy is organized in a hierarchy structure, wherein the one or more inclusive caches are organized in an inclusive cache hierarchy, wherein the inclusive cache hierarchy comprises a first level cache and a third level cache, wherein the one or more exclusive caches comprises a second level cache [fig. 1; pars. 0018, 0036 – Local cache and high-level cache may be inclusive and shared cache may be exclusive. The directory may be used to locate data in the cache hierarchy. (“Like a shared cache 113, the high level cache 120 may be exclusive, such that it does not contain the data stored in the shared caches 113. The high level cache 120 may, alternatively, be inclusive, such that it contains the data stored in the shared caches 113 of the processing nodes 110. However, inclusiveness may limit the effectiveness of the high level cache 120, where, for instance, half of an 8 Mega Byte (MB) high level cache 120 may be dedicated to replicating the data of the shared caches 113 of the four processing nodes 110, each of a 1 MB size. In that instance, only 4 MB would be left for caching purposes in the high-level cache 120. Therefore, more of the resources of a high-level cache 120 may be available when the cache is exclusive and it does not replicate the data stored in lower-level caches.” … “Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)]; and
retrieving the data from storage media [par. 0036 – Data may be returned from the system memory when not present in the cache hierarchy. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
However, Donley et al. do not specifically disclose,
and the cache directory comprises presence information and state information for the one or more inclusive caches and the one or more exclusive caches and wherein the presence information comprises an indication of at least one of the first level cache, the second level cache, and the third level cache,
In the same field of endeavor, Steely, JR. et al. disclose,
and the cache directory comprises presence information and state information for the one or more inclusive caches and the one or more exclusive caches and wherein the presence information comprises an indication of at least one of the first level cache, the second level cache, and the third level cache [pars. 0028-0029 – “A plurality of processing cores 111 may be associated with a cache domain 120. A tag directory 124 may be employed to keep track of data items stored by a plurality of caches associated with domain 120. Each tag of tag directory 124 may include a bitmap comprising a plurality of bit flags.” … “Each bit flag may indicate whether the cache line associated with the cache tag may be present in a cache identified by the position of the bit flag within the bitmap. In certain implementations, a first state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has a valid copy of the cache line. Alternatively, the first state of the bit flag may indicate that that processing core identified by the position of the corresponding bit flag within the bitmap is likely, but not guaranteed, to have a valid copy of the cache line (e.g., the copy might have not been received yet or might have been deleted by a silent eviction). The second state of the bit flag may indicate that the processing core identified by the position of the corresponding bit flag within the bitmap has no valid copies of the cache line.”],
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Donley et al. to include a cache directory, as taught by Steely, JR et al., in order to provide a central means for locating all the data across caches in the system.
Claim 18 (as applied to claim 17 above):
Donley et al. disclose, wherein determining that the data is not present in the cache hierarchy comprises:
searching the first level cache for the data; searching the second level cache for the data; and searching the cache directory for the data, wherein the data does not include a corresponding entry in the cache directory [par. 0036 – The cache hierarchy and directory are searched for the data. Data that is not found is returned from system memory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim 20 (as applied to claim 18 above):
Donley et al. disclose,
wherein searching the cache directory comprises determining that the data is not located in the cache directory [par. 0036 – The data may not be located in the directory. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
Claim(s) 5, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Donley et al. (Pub. No. US 2012/0159080) in view of Steely, JR. et al. (Pub. No. US 2016/0170880) as applied to claims 4, 11, and 18 above, respectively, and further in view of DeLan (Pub. No. US 2005/0033920).
Claim 5 (as applied to claim 4 above):
Donley and Steely, JR. et al. disclose all the limitations above but do not specifically disclose,
wherein searching the second cache and searching the cache directory are performed in parallel.
In the same field of endeavor, DeLan discloses,
wherein searching the second cache and searching the cache directory are performed in parallel [par. 0069 – “Additionally, because tag arrays in the cache structure 100 are searched in parallel, latency is lower than in a traditional hierarchical cache in which cache levels are searched in series.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Donley and Steely, JR. et al. to include searching in parallel, as taught by DeLan, in order to improve performance by reducing latency.
Claim 12 (as applied to claim 11 above):
Donley and Steely, JR. et al. disclose all the limitations above but do not specifically disclose,
wherein searching the second level cache and searching the cache directory are performed in parallel.
In the same field of endeavor, DeLan disclose,
wherein searching the second level cache and searching the cache directory are performed in parallel [par. 0069 – “Additionally, because tag arrays in the cache structure 100 are searched in parallel, latency is lower than in a traditional hierarchical cache in which cache levels are searched in series.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Donley and Steely, JR. et al. to include searching in parallel, as taught by DeLan, in order to improve performance by reducing latency.
Claim 19 (as applied to claim 18 above):
Donley and Steely, JR. et al. disclose all the limitations above but do not specifically disclose,
wherein searching the second level cache and searching the cache directory are performed in parallel.
In the same field of endeavor, DeLan disclose,
wherein searching the second level cache and searching the cache directory are performed in parallel [par. 0069 – “Additionally, because tag arrays in the cache structure 100 are searched in parallel, latency is lower than in a traditional hierarchical cache in which cache levels are searched in series.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Donley and Steely, JR. et al. to include searching in parallel, as taught by DeLan, in order to improve performance by reducing latency.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Donley et al. (Pub. No. US 2012/0159080) in view of Steely, JR. et al. (Pub. No. US 2016/0170880) as applied to claim 1 above, and further in view of Buyuktosunoglu et al. (Pub. No. US 2015/0032962).
Claim 9 (as applied to claim 1 above):
Donley et al. disclose the device, further comprising
wherein the first cache is a first level cache [fig. 1 – local cache];
wherein the second cache is a second level cache [fig. 1 – shared cache cache];
wherein the third cache is a last level cache [fig. 1 – high-level cache]; and
wherein the processor performs operations comprising:
searching the cache directory for data [fig. 1; par. 0036 – Directory is searched. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)];
determining that the data is found in a last level cache [fig. 1; par. 0036 – Directory is located. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)];
However, Donley and Steely, JR. et al. do not specifically disclose,
a fourth cache, wherein the fourth cache is a last level cache.
wherein the fourth cache is organized in the inclusive cache hierarchy [fig. 1; par. 0018 – Donley et al. disclose that the high-level cache may be inclusive but do not disclose multiple high-level caches. (“Like a shared cache 113, the high level cache 120 may be exclusive, such that it does not contain the data stored in the shared caches 113. The high level cache 120 may, alternatively, be inclusive, such that it contains the data stored in the shared caches 113 of the processing nodes 110. However, inclusiveness may limit the effectiveness of the high level cache 120, where, for instance, half of an 8 Mega Byte (MB) high level cache 120 may be dedicated to replicating the data of the shared caches 113 of the four processing nodes 110, each of a 1 MB size. In that instance, only 4 MB would be left for caching purposes in the high-level cache 120. Therefore, more of the resources of a high-level cache 120 may be available when the cache is exclusive and it does not replicate the data stored in lower-level caches.”)];
searching the fourth cache for the data [fig. 1; par. 0036 – Donley et al. disclose that data is returned from the cache, however, Donley et al. do not disclose multiple high-level caches. (“Rather than wasting the tag field 531 and the state field 532 associated with the repurposed data 530 of the cache 500, these fields may be utilized in a multi-processor system for a neighbor cache directory. A neighbor cache directory provides an indication to a processor core of whether requested data may be present in another processor core's cache. Therefore, rather than obtaining data from system memory, such as RAM, data may be obtained from a neighbor core's cache.”)].
In the same field of endeavor, Buyuktosunoglu et al. disclose,
a fourth cache, wherein the fourth cache is a last level cache [fig. 48A; par. 0229 – plurality of L3 caches. (“In general, the 3-D processing system 1800 is similar to the system 1700 discussed above in that the 3-D processing system 1800 comprises a first chip layer (Layer 1) and a second chip layer (Layer 2), which are physically conjoined to form a stacked structure, wherein first chip layer comprises a plurality of processor cores 1802, 1804, 1806, and 1808, a plurality of L2 caches 1810 and 1812, and wherein the second chip layer comprises a plurality of L3 caches 1814 and 1816”)].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Donley and Steely, JR. et al. include multiple L3 caches, as taught by Buyuktosunoglu et al., in order to increase performance by providing increased cache capacity.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
28 March 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139