DETAILED ACTION
Claim(s) 1-20 have been examined and are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: WIRELESS RECEIVER DEVICE, DATA PROCESSING METHOD THEREOF, AND WIRELESS COMMUNICATION SYSTEM FOR DECODING AN AGGREGATED PACKET
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the numbers of data bits per symbol". There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites the limitation "the numbers of symbols". There is insufficient antecedent basis for this limitation in the claim.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recites the limitation "the numbers of data bits per symbol". There is insufficient antecedent basis for this limitation in the claim. Claim 8 recites the limitation "the numbers of symbols". There is insufficient antecedent basis for this limitation in the claim.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 13 recites the limitation "the numbers of data bits per symbol". There is insufficient antecedent basis for this limitation in the claim. Claim 13 recites the limitation "the numbers of symbols". There is insufficient antecedent basis for this limitation in the claim.
Double Patenting
Claim(s) 1, 8, and 13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, and 13 of copending Application No. 18/741777. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 1 of Instant Application
Claim 1 of Application No. 18/741777
1. A wireless receiver device, comprising:
1. A wireless receiver device, comprising:
a decoder configured to decode an aggregated packet to obtain raw data during a period of a plurality of symbols, the aggregated packet having a plurality of subblocks;
a decoder configured to decode a packet in a period of a plurality of symbols to obtain raw data;
a memory configured to temporarily store the raw data;
a memory configured to temporarily store the raw data;
and a processor configured to determine at least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, and a performance characteristic of the processor;
and a processor configured to determine at least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of data bits per symbol and the number of symbols corresponding to the packet;
wherein the processor accesses the memory to perform data parsing on the raw data in a period of the at least one non-idle symbol, and wherein the processor enters an idle state so as not to access the memory in a period of the at least one idle symbol.
wherein the processor accesses the memory to perform data parsing on the raw data in a period of the at least one non-idle symbol, and wherein the processor enters an idle state so as not to access the memory in a period of the at least one idle symbol.
Claim 1 of Application No. 18/741777 (App’ 777) differs from claim 1 of the Instant Application in that Claim 1 of App’ 77 is silent on the decoder decoding an aggregated packet, the aggregated packet having a plurality of subblocks. Claim 1 of App’ 777 further differs from claim 1 of the Instant Application in that Claim 1 of App’ 777 is silent on where the processor is configured to determine the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Finally, Claim 1 of App ‘777 differs from claim 1 of the Instant Application in that Claim 1 of App ‘777 is silent on the number of symbols and the number of data bits per symbol corresponding to the plurality of subblocks. Despite these differences similar features have been seen in other prior art network communications systems.
YANG (US 20200305164 A1) teaches an aggregated packet, A-MPDU, having a plurality of subblocks, MPDUs (See [Fig. 4] which illustrates a PPDU, comprising A-MPDU, the A-MPDU comprising multiple MPDUs) YANG also teaches a number of symbols and a number of data bits per symbol corresponding to a plurality of subblocks (“[0221]…For example, as part of a DL SU PPDU, the AP 102-a may identify at least a data rate field, length field, and tail field for the PPDU. Based on the identifying, the AP 102-a may calculate a number of OFDM symbols included in the data field assigned for the STA 104-a according to Equations (1), (2), and (3) below…[0222]…The variable, N.sub.DBPS may include the number of data bits for each OFDM symbol that may be indicated within a data rate field of the PPDU.)
Thus based upon the teachings of YANG it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the network communication feature of claim 1 of App’777 by applying the network communication feature to aggregated packets, A-MPDUs, as similarly seen in YANG, to thus arrive at features where the decoder is configured to decode an aggregated packet to obtain raw data during the period of a plurality of symbols, the aggregated packet having a plurality of subblocks; and the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, in order to take advantage of the benefits provided by the use of A-MPDUs.
The combined teachings of Claim 1 of App’777 in view of YANG further differ from claim 1 of the Instant Application in that the combined teachings are silent on where the processor is configured to determine the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Despite these differences similar features have been seen involving the use of processors. MILLER (US 20070288786 A1) teaches where instructions/operations executed by a processor are performed according to a characteristic of a process, clock speed (“[0002] Computer systems are often advertised according to various characteristics of the processor, particularly the internal clock frequency of the processor. Typically, the processor clock has a frequency that is an integer multiple of the bus clock frequency. Although a processor is usually capable of performing internal operations at the advertised fast clock speeds, in many cases the processor clock is too fast for the bus and peripheral devices. Therefore, the processor communicates with the peripheral devices only at the slower speed of the interface bus clock. Even in a system-on-chip (SOC) device, the processor is limited to the slower clock frequency during data transfers.”).
Thus based upon the teachings of MILLER it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the processing feature of Claim 1 of App’777 in view of YANG, by adopting features for performing instructions and operations according to a characteristic of a processor, such as a clock frequency of a processor, to thus arrive at where the processor configured to determine the least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, and a performance characteristic of the processor, to thus arrive at claim 1 of the Instant Application. A person of ordinary skill in the art would have arrived at such a feature realizing that instructions and various operations performed by computing device are constrained/limited according to a clock frequency of a processor. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 8 of Instant Application
Claim 8 of Application No. 18/741777
8. A data processing method adapted to a wireless receiver device and comprising:
8. A data processing method adapted to a wireless receiver device, the data processing method comprising:
decoding an aggregated packet to obtain raw data during a period of a plurality of symbols, the aggregated packet having a plurality of subblocks;
decoding a packet in a period of a plurality of symbols to obtain raw data;
temporarily storing the raw data to a memory of the wireless receiver device;
temporarily storing the raw data to a memory;
determine at least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, and a performance characteristic of a processor of the wireless receiver device;
and determining at least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of data bits per symbol and the number of symbols corresponding to the packet,
accessing the memory to perform data parsing on the raw data by the processor in a period of the at least one non-idle symbol; and
and accessing the memory to perform data parsing on the raw data in a period of the at least one non-idle symbol,
entering an idle state by the processor so as not to access the memory in a period of the at least one idle symbol.
and entering an idle state so as not to access the memory in a period of the at least one idle symbol.
Claim 8 of Application No. 18/741777 (App’ 777) differs from claim 8 of the Instant Application in that Claim 8 of App’ 777 is silent on decoding an aggregated packet, the aggregated packet having a plurality of subblocks. Claim 8 of App’ 777 further differs from claim 8 of the Instant Application in that Claim 8 of App’ 777 is silent on determining the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Additionally, Claim 8 of App ‘777 differs from claim 8 of the Instant Application in that Claim 8 of App ‘777 is silent on the number of symbols and the number of data bits per symbol corresponding to the plurality of subblocks. Finally, Claim 8 of App ‘777 differs from claim 8 of the Instant Application, in that with respect to temporarily storing the raw data to a memory, Claim 8 of App ’777 is silent on temporarily storing the raw data to a memory of the wireless receiver device. Despite these differences similar features have been seen in other prior art network communications systems.
First with respect to the feature of temporarily storing the raw data to a memory of the wireless receiver device, Claim 8 of App ‘777 suggests adapting the method of claim 8 to a wireless device (See where it recites, “A data processing method adapted to a wireless receiver device”). Claim 8, teaches at least storing the raw data to a memory of the wireless receiver device. Thus based upon Claim 8 of App ‘777 intention of adapting the method of claim 8 to a wireless receiver device, it would have been obvious to modify Claim 8 of App ‘777 to arrive at temporarily storing the raw data to a memory of the wireless receiver device, in order to operate the method according to intended use as suggested by App’ 777.
Claim 8 of App ‘777 further differs from claim 8 of the Instant Application in that Claim 8 of App’ 777 is silent on decoding an aggregated packet, the aggregated packet having a plurality of subblocks. Claim 8 of App’ 777 further differs from claim 8 of the Instant Application in that Claim 8 of App’ 777 is silent on determining the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Additionally, Claim 8 of App ‘777 differs from claim 8 of the Instant Application in that Claim 8 of App ‘777 is silent on the number of symbols and the number of data bits per symbol corresponding to the plurality of subblocks. Despite these differences similar features have been seen in other prior art network communications systems.
YANG (US 20200305164 A1) teaches an aggregated packet, A-MPDU, having a plurality of subblocks, MPDUs (See [Fig. 4] which illustrates a PPDU, comprising A-MPDU, the A-MPDU comprising multiple MPDUs) YANG also teaches a number of symbols and a number of data bits per symbol corresponding to a plurality of subblocks (“[0221]…For example, as part of a DL SU PPDU, the AP 102-a may identify at least a data rate field, length field, and tail field for the PPDU. Based on the identifying, the AP 102-a may calculate a number of OFDM symbols included in the data field assigned for the STA 104-a according to Equations (1), (2), and (3) below…[0222]…The variable, N.sub.DBPS may include the number of data bits for each OFDM symbol that may be indicated within a data rate field of the PPDU.)
Thus based upon the teachings of YANG it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the network communication feature of claim 8 of App’777 by applying the network communication feature to aggregated packets, A-MPDUs, as similarly seen in YANG, to thus arrive at features for decoding an aggregated packet to obtain raw data during the period of a plurality of symbols, the aggregated packet having a plurality of subblocks; and the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, in order to take advantage of the benefits provided by the use of A-MPDUs.
The combined teachings of Claim 8 of App’777 in view of YANG further differ from claim 8 of the Instant Application in that the combined teachings are silent on where the processor is configured to determine the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Despite these differences similar features have been seen involving the use of processors. MILLER (US 20070288786 A1) teaches where instructions/operations executed by a processor are performed according to a characteristic of a process, clock speed (“[0002] Computer systems are often advertised according to various characteristics of the processor, particularly the internal clock frequency of the processor. Typically, the processor clock has a frequency that is an integer multiple of the bus clock frequency. Although a processor is usually capable of performing internal operations at the advertised fast clock speeds, in many cases the processor clock is too fast for the bus and peripheral devices. Therefore, the processor communicates with the peripheral devices only at the slower speed of the interface bus clock. Even in a system-on-chip (SOC) device, the processor is limited to the slower clock frequency during data transfers.”).
Thus based upon the teachings of MILLER it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the processing feature of Claim 1 of App’777 in view of YANG, by adopting features for performing instructions and operations according to a characteristic of a processor, such as a clock frequency of a processor, to thus arrive at where the processor configured to determine the least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, and a performance characteristic of the processor, to thus arrive at claim 8 of the Instant Application. A person of ordinary skill in the art would have arrived at such a feature realizing that instructions and various operations performed by computing device are constrained/limited according to a clock frequency of a processor. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 13 of Instant Application
Claim 13 of Application No. 18/741777
13. A wireless communication system, comprising:
13. A wireless communication system, comprising:
a wireless transmitter device configured to transmit an aggregated packet, the aggregated packet having a plurality of subblocks;
a wireless transmitter device configured to transmit a packet;
and a wireless receiver device configured to receive the aggregated packet via a wireless channel, the wireless receiver device comprising:
and a wireless receiver device configured to receive the packet via a wireless channel, the wireless receiver device comprising:
a decoder configured to decode the aggregated packet to obtain raw data during a period of a plurality of symbols;
a decoder configured to decode the packet in a period of a plurality of symbols to obtain raw data;
a memory configured to temporarily store the raw data;
a memory configured to temporarily store the raw data;
and a processor configured to determine at least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, and a performance characteristic of the processor; wherein the processor accesses the memory to perform data parsing on the raw data in a period of the at least one non-idle symbol, and wherein the processor enters an idle state so as not to access the memory in a period of the at least one idle symbol.
and a processor configured to determine at least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of data bits per symbol and the number of symbols corresponding to the packet; wherein the processor accesses the memory to perform data parsing on the raw data in a period of the at least one non-idle symbol, and wherein the processor enters an idle state so as not to access the memory in a period of the at least one idle symbol.
Claim 13 of Application No. 18/741777 (App’ 777) differs from claim 13 of the Instant Application in that Claim 13 of App’ 777 is silent on the wireless transmitter transmitting an aggregated packet, the aggregated packet having a plurality of subblocks, the wireless receiver receiving the aggregated packet, and the decoder decoding the aggregated packet. Claim 13 of App’ 777 further differs from claim 13 of the Instant Application in that Claim 13 of App’ 777 is silent on where the processor is configured to determine the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Finally, Claim 13 of App ‘777 differs from claim 13 of the Instant Application in that Claim 13 of App ‘777 is silent on the number of symbols and the number of data bits per symbol corresponding to the plurality of subblocks. Despite these differences similar features have been seen in other prior art network communications systems.
YANG (US 20200305164 A1) teaches an aggregated packet, A-MPDU, having a plurality of subblocks, MPDUs (See [Fig. 4] which illustrates a PPDU, comprising A-MPDU, the A-MPDU comprising multiple MPDUs) YANG also teaches a number of symbols and a number of data bits per symbol corresponding to a plurality of subblocks (“[0221]…For example, as part of a DL SU PPDU, the AP 102-a may identify at least a data rate field, length field, and tail field for the PPDU. Based on the identifying, the AP 102-a may calculate a number of OFDM symbols included in the data field assigned for the STA 104-a according to Equations (1), (2), and (3) below…[0222]…The variable, N.sub.DBPS may include the number of data bits for each OFDM symbol that may be indicated within a data rate field of the PPDU.)
Thus based upon the teachings of YANG it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the network communication feature of claim 13 of App’777 by applying the network communication feature to aggregated packets, A-MPDUs, as similarly seen in YANG, to thus arrive at features where the wireless transmitter is configured to transmit an aggregated packet, the aggregated packet having a plurality of subblocks, the wireless receiver is configured to receive the aggregated packet, the decoder is configured to decode the aggregated packet and the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, in order to take advantage of the benefits provided by the use of A-MPDUs.
The combined teachings of Claim 13 of App’777 in view of YANG further differ from claim 13 of the Instant Application in that the combined teachings are silent on where the processor is configured to determine the at least one non-idle symbol and the at least one idle symbol from the plurality of symbols according to a performance characteristic of the processor. Despite these differences similar features have been seen involving the use of processors.
MILLER (US 20070288786 A1) teaches where instructions/operations executed by a processor are performed according to a characteristic of a process, clock speed (“[0002] Computer systems are often advertised according to various characteristics of the processor, particularly the internal clock frequency of the processor. Typically, the processor clock has a frequency that is an integer multiple of the bus clock frequency. Although a processor is usually capable of performing internal operations at the advertised fast clock speeds, in many cases the processor clock is too fast for the bus and peripheral devices. Therefore, the processor communicates with the peripheral devices only at the slower speed of the interface bus clock. Even in a system-on-chip (SOC) device, the processor is limited to the slower clock frequency during data transfers.”).
Thus based upon the teachings of MILLER it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the processing feature of Claim 13 of App’777 in view of YANG, by adopting features for performing instructions and operations according to a characteristic of a processor, such as a clock frequency of a processor, to thus arrive at where the processor configured to determine the least one non-idle symbol and at least one idle symbol from the plurality of symbols according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the plurality of subblocks, and a performance characteristic of the processor, to thus arrive at claim 13 of the Instant Application. A person of ordinary skill in the art would have arrived at such a feature realizing that instructions and various operations performed by computing device are constrained/limited according to a clock frequency of a processor. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claim(s) 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and further pending resolution of the Double Patenting Rejections set forth in this Office action.
Conclusion
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/TARELL A HAMPTON/Examiner, Art Unit 2476 /AYAZ R SHEIKH/Supervisory Patent Examiner, Art Unit 2476
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