Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Para. [0025], based on Figure 4, “Pa2” should correctly be “Pb1”.
Appropriate correction is required.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3, line 1, “the step of generating the” should be “the generating”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (7,268,624), hereafter called CHEN.
Regarding claim 1, CHEN (Fig. 1) discloses an offset control circuit comprising: obtaining a first offset voltage generated by a differential input transistor pair (123, 124) of a first amplifier (120) in the AFE circuit, and generating first information according to the first offset voltage; obtaining a second offset voltage generated by a tail current source (127, 128) of the first amplifier (120) in the AFE circuit, and generating second information according to the second offset voltage and the first information; obtaining (102) a predetermined first DC gain and a predetermined second DC gain, and generating first compensation information based on the first DC gain, the second DC gain, the first information and the second information; and correcting an output voltage (103, 104) generated by the first amplifier based on the first compensation information.
Regarding claim 2, further comprising: turning off the first amplifier and compensating an output voltage of a comparator (101), wherein the comparator is coupled after the first amplifier.
Regarding claim 7, CHEN (Fig. 1) discloses an offset control circuit comprising: a first amplifier (120) ; a first compensation circuit (103, 104) coupled to an output terminal of the first amplifier, correcting an output voltage generated by the first amplifier according to first compensation information; and a compensation information generator (102) coupled to the first compensation circuit, generating the first compensation information according to a first DC gain, a second DC gain, first information and second information, wherein the first information is generated based on a first offset voltage generated by a differential input transistor pair (123, 124) of the first amplifier, and the second information is generated based on a second offset voltage generated by a tail current source (127, 128) of the first amplifier.
Regarding claim 8, wherein the first compensation circuit comprises: a first current source (127) coupled between a first output terminal of the first amplifier and a reference ground terminal (VSS), providing a first compensation current to a first output terminal of the first amplifier according to the first compensation information; and a second current source (128) coupled between a second output terminal of the first amplifier and the reference ground terminal (VSS), providing a second compensation current to a second output terminal of the first amplifier according to the first compensation information.
Allowable Subject Matter
Claims 3-6 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, prior art(s) does not disclose the generating first compensation information based on the first DC gain, the second DC gain, the first information and the second information comprises: multiplying the first DC gain by the first information to obtain first data; multiplying the second DC gain by the second information to obtain second data; and adding the first data and the second data to obtain the first compensation information.
Regarding claim 4, prior art(s) does not disclose the first DC gain is equal to (gm x RL)/(1+gm x Rs/2), and the second DC gain is equal to (gm x Rs/2)/(1+gm x Rs/2), wherein gm is a transconductance value of the first amplifier, Rs is a source resistance value in the first amplifier, and RL is a load resistance value of the first amplifier.
Regarding clams 5 and 6, prior art(s) does not disclose obtaining a third offset voltage generated by a tail current source of a second amplifier in the AFE circuit, and generating third information based on the third offset voltage and the second information; obtaining a fourth offset voltage generated by a differential input transistor pair of the second amplifier in the AFE circuit, and generating fourth information based on the fourth offset voltage and the second information; generating second compensation information according to a predetermined third DC gain, a predetermined fourth DC gain, the third information and the fourth information; correcting an output voltage generated by the second amplifier based on the second compensation information, wherein the second amplifier is coupled before the first amplifier.
Regarding claim 9, prior art(s) does not disclose the compensation information generator comprises: a memory storing the first information and the second information; a first multiplier coupled to the memory, and multiplying the first DC gain by the first information to generate first data; a second multiplier coupled to the memory, and multiplying the second DC gain by the second information to generate second data; a first adder adding the first data and the second data to generate the first compensation information.
Regarding claims 10-12, prior art(s) does not disclose a second amplifier; a second compensation circuit coupled to an output terminal of the second amplifier, correcting an output voltage generated by the second amplifier according to second compensation information; and the compensation information generator coupled to the second compensation circuit and generating the second compensation information according to a third DC gain, a fourth DC gain, third information and fourth information, wherein the third information is generated based on a third offset voltage generated by a tail current source of the second amplifier and the second information, and the fourth information is generated based on a fourth offset voltage generated by a differential input transistor pair of the second amplifier and the second information.
Conclusion
The prior art(s) made of record and not relied upon is/are considered pertinent to applicant's disclosure.
Zhang et al. (20200403583), which is considered to be the closest prior art to the claimed invention. Zhang et al. (Fig. 2) disclose a DC offset cancellation circuit comprising: a first amplifier (input stage), D/A converter, microprocessor and a comparator for canceling DC offset, which can be used in combination with a secondary reference.
NAKAMURA (20210288618) discloses circuit having DC offset cancellation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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