DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, and 13, 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2022/0321135.
Regarding claim 1, Chen discloses an ADC architecture in figure 1A that teaches: a plurality of channel circuitries (110) configured to sample an input signal (Sin) to generate a plurality of first digital codes (Q0 … Q1) according to the input signal (Sin); an output circuit (120) configured to output a second digital code (CQ0…CQ1) according to the plurality of first digital codes (Q0..Q1); and a calibration circuitry (130)(skew adjusting CKT function same as calibration CKT) configured to adjust a sampling sequence of the plurality of channel circuitries (T0…T1) for the input signal during an initial period, and control the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figure 1A and its descriptions).
Regarding claim 2, Chen teaches in figure 1B describes sampling sample (S1..S2) the input signal (Sin) to a corresponding one of the a plurality clocks (CLK0…CLK1) signals to generate a first signal (Q0) and an ADC (110) to convert the first signal to generate a plurality digital codes (Q0…Q1) (see figure 1A and 1B and their descriptions).
Regarding claim 5, Chen teaches in figure 2 (the detail of CKT 130) that teaches wherein the calibration circuitry (130) is configured to determine a performance indicator (131 is equivalent to indicator CKT) according to the second digital code (CQ0) during the initial period, and determine the adjusted sampling sequence (133) according to the performance indicator (131) (see figure 2 and its descriptions).
Regarding claim 6, Chen teaches in figures 1A and 2 CKT comprises at least a skew error (130).
Regarding claim 13, claim 13 is similar to claim 1 in method format. Therefore claim 13 is rejected as well as rejected in claim 1, such as: Chen discloses an ADC architecture in figure 1A that teaches: a plurality of channel circuitries (110) configured to sample an input signal (Sin) to generate a plurality of first digital codes (Q0 … Q1) according to the input signal (Sin); an output circuit (120) configured to output a second digital code (CQ0…CQ1) according to the plurality of first digital codes (Q0..Q1); and a calibration circuitry (130)(skew adjusting CKT function same as calibration CKT) configured to adjust a sampling sequence of the plurality of channel circuitries (T0…T1) for the input signal during an initial period, and control the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figure 1A and its descriptions).
Regarding claim 15, claim 15 is similar to claim 5 in method format. Therefore claim 15 is rejected as well as rejected in claim 5, such as: Chen teaches in figure 2 (the detail of CKT 130) that teaches wherein the calibration circuitry (130) is configured to determine a performance indicator (131 is equivalent to indicator CKT) according to the second digital code (CQ0) during the initial period, and determine the adjusted sampling sequence (133) according to the performance indicator (131) (see figure 2 and its descriptions).
Regarding claim 16, claim 16 is similar to claim 6 in method format. Therefore claim 16 is rejected as well as rejected in claim 6 such as: Chen teaches in figures 1A and 2 CKT comprises at least a skew error (130).
Regarding claim 17, claim 17 is similar to claim 2 in method format. Therefore claim 17 is rejected as well as rejected in claim 2 such as: Chen teaches in figure 1B describes sampling sample (S1..S2) the input signal (Sin) to a corresponding one of the a plurality clocks (CLK0…CLK1) signals to generate a first signal (Q0) and an ADC (110) to convert the first signal to generate a plurality digital codes (Q0…Q1) (see figure 1A and 1B and their descriptions).
Claims 1-2,13, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lok (USP 11,646,747).
Regarding claim 1, Lok discloses a multi-channel interleaved ADC architecture in figure 4 that teaches: a plurality of channel circuitries (T1…T4)) configured to sample an input signal (Ain) to generate a plurality of first digital codes (D1…D4) according to the input signal (Ain); an output circuit (97) configured to output a second digital code (Y1….Y4)) according to the plurality of first digital codes (D1…D4); and a calibration circuitry (55) configured to adjust a sampling sequence of the plurality of channel circuitries (T22….24) for the input signal during an initial period, and control the plurality of channel circuitries (44) to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figure 4 and its descriptions).
Regarding claim 2, Lok teaches in figure 4 describes sampling sample ((40,42,43,44) the input signal (Ain) to a corresponding one of the a plurality clocks (CK, figure 8) signals to generate a first signal (D1) and an ADC (10) to convert the first signal to generate a plurality digital codes (D1…D4 (see figures 4 and 8 and their descriptions).
Regarding claim 13, claim 13 is similar to claim 1 in method format. Therefore claim 13 is rejected as well as rejected in claim 1, such as: Lok discloses a multi-channel interleaved ADC architecture in figure 4 that teaches: a plurality of channel circuitries (T1…T4)) configured to sample an input signal (Ain) to generate a plurality of first digital codes (D1…D4) according to the input signal (Ain); an output circuit (97) configured to output a second digital code (Y1….Y4)) according to the plurality of first digital codes (D1…D4); and a calibration circuitry (55) configured to adjust a sampling sequence of the plurality of channel circuitries (T22….24) for the input signal during an initial period, and control the plurality of channel circuitries (44) to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figure 4 and its descriptions).
Regarding claim 17, claim 17 is similar to claim 2 in method format. Therefore claim 17 is rejected as well as rejected in claim 2 such as: Regarding claim 2, Lok teaches in figure 4 describes sampling sample ((40,42,43,44) the input signal (Ain) to a corresponding one of the a plurality clocks (CK, figure 8) signals to generate a first signal (D1) and an ADC (10) to convert the first signal to generate a plurality digital codes (D1…D4 (see figures 4 and 8 and their descriptions).
Claims 1-2,13, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lok (USP 11,641,210).
Regarding claim 1, Lok discloses a multi-channel interleaved ADC architecture in figures 4, 11,12 that teach: a plurality of channel circuitries (T1…T4)) configured to sample an input signal (Ain) to generate a plurality of first digital codes (D1…D4) according to the input signal (Ain); an output circuit (17) configured to output a second digital code (Y1….Y4)) according to the plurality of first digital codes (D1…D4); and a calibration circuitry (55) configured to adjust a sampling sequence of the plurality of channel circuitries (T1….T4) for the input signal during an initial period, and control the plurality of channel circuitries (40….44) to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figures 4, 11-12 and their descriptions).
Regarding claim 2, Lok teaches in figure 4 describes sampling sample ((40,42,43,44) the input signal (Ain) to a corresponding one of the a plurality clocks (CK, figure 8) signals to generate a first signal (D1) and an ADC (10) to convert the first signal to generate a plurality digital codes (D1…D4 (see figures 4 and 8 and their descriptions).
Regarding claim 13, claim 13 is similar to claim 1 in method format. Therefore claim 13 is rejected as well as rejected in claim 1, such as: Lok discloses a multi-channel interleaved ADC architecture in figure 4 that teaches: a plurality of channel circuitries (T1…T4)) configured to sample an input signal (Ain) to generate a plurality of first digital codes (D1…D4) according to the input signal (Ain); an output circuit (17) configured to output a second digital code (Y1….Y4)) according to the plurality of first digital codes (D1…D4); and a calibration circuitry (55) configured to adjust a sampling sequence of the plurality of channel circuitries (T20….T24) for the input signal during an initial period, and control the plurality of channel circuitries (40…44) to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figures 4,11-12 and their descriptions).
Regarding claim 17, claim 17 is similar to claim 2 in method format. Therefore claim 17 is rejected as well as rejected in claim 2 such as: Regarding claim 2, Lok teaches in figure 4 describes sampling sample ((40,42,43,44) the input signal (Ain) to a corresponding one of the a plurality clocks (CK, figure 8) signals to generate a first signal (D1) and an ADC (10) to convert the first signal to generate a plurality digital codes (D1…D4 (see figures 4 and 8 and their descriptions).
Claims 1-2, 5-6, and 13, 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 2022/0321135.
Regarding claim 1, Han et al. discloses an ADC architecture in figure 1A that teaches: a plurality of channel circuitries (110) configured to sample an input signal (Sin) to generate a plurality of first digital codes (Q0 … Q1) according to the input signal (Sin); an output circuit (121) configured to output a second digital code (CQ10…CQ11) according to the plurality of first digital codes (Q0..Q1); and a calibration circuitry (123)(skew adjusting CKT function same as calibration CKT) configured to adjust a sampling sequence of the plurality of channel circuitries (T0…T1) for the input signal during an initial period, and control the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figure 1A and its descriptions).
Regarding claim 2, Han teaches in figure 1B describes sampling sample (S1..S2) the input signal (Sin) to a corresponding one of the a plurality clocks (CLK0…CLK1) signals to generate a first signal (Q0) and an ADC (110) to convert the first signal to generate a plurality digital codes (Q0…Q1) (see figure 1A and 1B and their descriptions).
Regarding claim 5, Han teaches in figure 2 (the detail of CKT 130) that teaches wherein the calibration circuitry (123) is configured to determine a performance indicator (125) is equivalent to indicator CKT) according to the second digital code (CQ20…CQ21) during the initial period, and determine the adjusted sampling sequence (130) according to the performance indicator (125) (see figure 1A and its descriptions).
Regarding claim 6, Han teaches in figures 1A and 2 CKT comprises at least a skew error (125).
Regarding claim 13, claim 13 is similar to claim 1 in method format. Therefore claim 13 is rejected as well as rejected in claim 1, such as: Han et al. discloses an ADC architecture in figure 1A that teaches: a plurality of channel circuitries (110) configured to sample an input signal (Sin) to generate a plurality of first digital codes (Q0 … Q1) according to the input signal (Sin); an output circuit (121) configured to output a second digital code (CQ10…CQ11) according to the plurality of first digital codes (Q0..Q1); and a calibration circuitry (123)(skew adjusting CKT function same as calibration CKT) configured to adjust a sampling sequence of the plurality of channel circuitries (T0…T1) for the input signal during an initial period, and control the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period (see figure 1A and its descriptions).
Regarding claim 15, claim 15 is similar to claim 5 in method format. Therefore claim 15 is rejected as well as rejected in claim 5, such as: Han teaches in figure 2 (the detail of CKT 130) that teaches wherein the calibration circuitry (123) is configured to determine a performance indicator (125) is equivalent to indicator CKT) according to the second digital code (CQ20…CQ21) during the initial period, and determine the adjusted sampling sequence (130) according to the performance indicator (125) (see figure 1A and its descriptions).
Regarding claim 16, claim 16 is similar to claim 6 in method format. Therefore claim 16 is rejected as well as rejected in claim 6 such as: Han teaches in figures 1A and 2 CKT comprises at least a skew error (125).
Regarding claim 17, claim 17 is similar to claim 2 in method format. Therefore claim 17 is rejected as well as rejected in claim 2 such as: Han teaches in figure 1B describes sampling sample (S1..S2) the input signal (Sin) to a corresponding one of the a plurality clocks (CLK0…CLK1) signals to generate a first signal (Q0) and an ADC (110) to convert the first signal to generate a plurality digital codes (Q0…Q1) (see figure 1A and 1B and their descriptions).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration circuitry comprises: a control logic circuit configured to output a control signal according to the second digital code during the initial period; a clock generator circuit configured to generate a plurality of second clock signals; and a clock multiplexer circuit configured to output the plurality of second clock signals in different sequences as the plurality of first clock signals according to the control signal during the initial period.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration circuitry is configured to output a plurality of second clock signals in different sequences as a plurality of first clock signals, and the plurality of channel circuitries are configured to sequentially sample the input signal according to the plurality of first clock signals.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein each of the plurality of channel circuitries comprises: a first sampling circuit configured to be selectively turned on according to a corresponding clock signal in a plurality of first clock signals, in order to transmit the input signal; a plurality of second sampling circuits configured to sample the input signal transmitted from the first sampling signal according to a plurality of second clock signals, in order to generate a plurality of first signals; and a plurality of analog-to-digital converter circuits configured to convert the plurality of first signals to generate a part of the plurality of first digital codes.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration circuitry is further configured to divide a frequency of the corresponding clock signal to generate the plurality of second clock signals.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the first sampling circuit comprises: a switch configured be selectively turned on according to the corresponding clock signal, in order to transmit the input signal to the plurality of second sampling circuits.
Claim 10 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the first sampling circuit comprises: a capacitor; and a switch configured to be selectively turned on according to the corresponding clock signal, in order to transmit the input signal to the capacitor to generate a second signal, wherein the plurality of second sampling circuits are configured to sample the second signal according to the plurality of second clock signals to generate the plurality of first signals.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration circuitry comprises: a control logic circuit configured to output a control signal according to the second digital code during the initial period; a clock generator circuit configured to generate a plurality of third clock signals; a clock multiplexer circuit configured to output the plurality of third clock signals in different sequences as the plurality of first clock signals according to the control signal during the initial period; and a frequency divider circuit configured to divide frequencies of the plurality of first clock signals to generate the plurality of second clock signals.
Claim 12 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the calibration circuitry is configured to provide the plurality of first clock signals in different sequences to the plurality of channel circuitries, in order to adjust the sampling sequence.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein adjusting the sampling sequence of the plurality of channel circuitries for the input signal according to the second digital code during the initial period, and controlling the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during the analog-to-digital conversion period comprises: outputting a plurality of second clock signals in different sequences as a plurality of first clock signals during the initial period, in order to adjust the sampling sequence wherein the plurality of channel circuitries are configured to sequentially sample the input signal according to the plurality of first clock signals.
Claim 18 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein each of the plurality of channel circuitries comprise a first sampling circuit, a plurality of second sampling circuits, and an analog-to-digital converter circuit, and sampling, by the plurality of channel circuitries, the input signal and generating the plurality of first digital codes according to the sampled input signal comprises: selectively turning on the first sampling circuit according to a corresponding clock signal in a plurality of first clock signals, in order to transmit the input signal; sampling, by the plurality of second sampling circuits, the input signal transmitted from the first sampling circuit according to a plurality of second clock signals to generate a plurality of first signals; and converting, by the analog-to-digital converter circuit, the plurality of first signals to generate a part of the plurality of first digital codes.
Claim 19 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein adjusting the sampling sequence of the plurality of channel circuitries for the input signal according to the second digital code during the initial period, and controlling the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during the analog-to-digital conversion period comprises: providing the plurality of first clock signals in different sequences to the plurality of channel circuitries during the initial period to adjust the sampling sequence.
Claim 20 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest of prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: dividing a frequency of the corresponding clock signal to generate the plurality of second clock signals.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845