Prosecution Insights
Last updated: April 19, 2026
Application No. 18/741,867

TIME INTERLEAVED ANALOG TO DIGITAL CONVERTER AND SIGNAL CONVERSION METHOD

Non-Final OA §102
Filed
Jun 13, 2024
Examiner
JEAN PIERRE, PEGUY
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Realtek Semiconductor Corporation
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
94%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
971 granted / 1031 resolved
+26.2% vs TC avg
Minimal -1% lift
Without
With
+-0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
14 currently pending
Career history
1045
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
41.1%
+1.1% vs TC avg
§102
37.4%
-2.6% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1031 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 6/13/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 9,065,464). With regard to claim 1, Zhang discloses: A time-interleaved analog-to-digital converter (100 Fig. 1), comprising: a plurality of sampling circuits (SH1, SH2 Fig. 1) configured to sequentially sample an input signal to generate a plurality of first signals, wherein a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal in a plurality of control signals (fine control, coarse control; Fig 1); a plurality of analog-to-digital converter circuits (ADC1, ADC2; Fig. 1) configured to generate a plurality of first digital codes (outputs ADC1, ADC 2 Fig. 1) according to the plurality of first signals; an output circuit configured to output a second digital code (ADC output) according to the plurality of first digital codes; and a calibration circuit (130 Fig. 1) configured to generate the plurality of control signals (coarse control, Fine control; Fig. 1) and adjust the plurality of control signals according to the second digital code ( col. 3 lines 30-34). With regard to claim 13, Zhang discloses: 13. A signal conversion method, comprising: sequentially sampling, by a plurality of sampling circuits, (SH1, SH2 Fig. 1) an input signal to generate a plurality of first signals, wherein a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal in a plurality of control signals; (fine control, coarse control; Fig 1); generating a plurality of first digital codes (outputs ADC1, ADC 2 Fig. 1) according to the plurality of first signals; outputting a second digital code (ADC output) according to the plurality of first digital codes (coarse control, Fine control; Fig. 1) and adjusting the plurality of control signals according to the second digital code ( col. 3 lines 30-34). Allowable Subject Matter Claims 2-12 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. O’sullivan discloses interleaved analog to digital converter with calibration scheme. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105. /PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Jun 13, 2024
Application Filed
Dec 10, 2025
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603662
ENCODER
2y 5m to grant Granted Apr 14, 2026
Patent 12597943
RAMP CIRCUIT
2y 5m to grant Granted Apr 07, 2026
Patent 12592710
CIRCUITRY FOR MEASUREMENT OF ELECTROCHEMICAL CELLS
2y 5m to grant Granted Mar 31, 2026
Patent 12592715
POST-SAMPLING SELECTABLE GAIN IN SAMPLE AND HOLD ANALOG-TO-DIGITAL CONVERTERS
2y 5m to grant Granted Mar 31, 2026
Patent 12592712
SUPERCONDUCTING ANALOG-TO-DIGITAL CONVERTER (ADC) SYSTEM
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
94%
With Interview (-0.7%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 1031 resolved cases by this examiner. Grant probability derived from career allow rate.

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