DETAILED ACTION
This action is responsive to the application filed 13 Jun 2024. Claims 1-20 are pending. Claims 1, 10, and 20 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 12, 13, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 4, 6, 8 – 11, 14, 15, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Houston, et al, U.S. Patent Application Publication 2008/0175068 (“Houston”).
Regarding claim 1, Houston teaches:
An apparatus, comprising: one or more memory arrays of a semiconductor component; (Houston, fig 1, “[0021] The integrated circuit 100 includes a memory array, which is an SRAM array in the illustrated embodiment. The SRAM array has a plurality of SRAM memory cells, wherein a SRAM memory cell 110 is typical, [0038] Additionally, the temperatures of switching may be adjusted at test depending on the process corner ( e.g., switching to a lower n-well bias at a relatively higher temperature for strong NMOS/weak PMOS (SNWP) than for weak NMOS/ strong PMOS (WNSP)).”; an SRAM device with testing devices and an initial testing phase; that different results can be derived from test to include different bias voltages applied to different wells of the device).
one or more temperature sensors of the semiconductor component; and circuitry of the semiconductor component coupled with the one or more memory arrays and with the one or more temperature sensors, the circuitry operable to cause the apparatus to: receive an indication to operate in an evaluation mode; (Houston, fig 1, 7, “[0022] The integrated circuit 100 also includes a thermostatic bias controller 135 having a temperature sensing circuit 140 and a voltage control circuit 145. The temperature sensing circuit 140 employs a temperature contact 140a to sense a temperature of the SRAM array. [0044] FIG. 7 illustrates a flow diagram of an embodiment of a method of operating a thermostatic bias controller, [0046] Then, an initial bias voltage setting for the memory array is determined in a step 715, a temperature sensing mode is established in a step 720 and bias voltage selections are provided in a step 725. [0047] The temperature sensing mode established in the step 720 may be selected from several possibilities. These include a continuous mode, a periodic mode,”; a thermistor bias controller 135 can be activated, the thermostat from each typical SRAM cell can be read based on a desired mode in step 720, and then a bias voltage selected in step 725; the system in step 720 creates an indication of time passed, and then the system receives an input from the thermometer 720, then the system evaluates the temperature to enter a new mode; initially the SRAM operates in a mode 0 as a default mode using the “initial bias voltage” of step 730).
configure the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; perform one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; (Houston, fig 1, 7, 5, “[0050] An initial bias voltage is applied to at least one back-gate in the memory array in a step 730. [0050] Then, a decisional step 735 determines if temperature sensing of the memory array is currently activated. If temperature sensing is activated, the temperature is sensed in a step 740. Then, in a step 745 the bias voltage is set based on the temperature sensed in the step 740 employing either a single temperature transition or temperature hysteresis transitions for increasing and decreasing temperatures.”; an SRAM can be configured to test the temperature based on multiple modes; when the temperature sensing is activated in 735, then according to the sensed temperature, an operational is selected with any one of the three operating modes; the modes include different bias voltages for the semiconductor well; a mode zero may be selected initially, and a mode 1 may be selected based on an updated temperature which has risen above ts1. Note: the “configuring the semiconductor” in this rejection is based on the periodic or continuous sampling of the temperature sensor).
configure the semiconductor component to operate in a second evaluation mode based at least in part on a temperature indicated by at least one of the one or more temperature sensors satisfying a temperature threshold in response to performing the one or more first operations, the second evaluation mode associated with a lower heat generation than the first evaluation mode; and perform one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered).
Regarding claim 2, Houston teaches The apparatus of claim 1, wherein, to configure the semiconductor component to operate in the second evaluation mode, the circuitry is operable to: increase a threshold voltage characteristic for one or more transistors of the circuitry during the second evaluation mode. (Houston, fig 5, 7, “[0036] For increasing SRAM temperatures below the first and second specified temperatures ts1, ts2 , a bias voltage of about 1.5 volts is applied to a back-gate such as then-wells 116, 121 discussed with respect to FIG. 1. A bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown”; the semiconductor controller applies a different bias voltage to the wells based on the temperature sensed as shown in fig 5).
Regarding claim 3, Houston teaches The apparatus of claim 2, further comprising: one or more voltage sources of the semiconductor component, wherein, to increase the threshold voltage characteristic for the one or more transistors, the circuitry is operable to: increase a bias, from the one or more voltage sources, that is applied to one or more wells of the semiconductor component associated with the one or more transistors. (Houston, fig 1, 5, 7, “[0022] The integrated circuit 100 also includes a thermostatic bias controller 135 having a temperature sensing circuit 140 and a voltage control circuit 145. [0036] For increasing SRAM temperatures below the first and second specified temperatures ts1, ts2 , a bias voltage of about 1.5 volts is applied to a back-gate such as then-wells 116, 121 discussed with respect to FIG. 1. A bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown”; the semiconductor controller takes the voltage from the voltage control circuit and then applies the appropriate bias voltage to the wells associated with the memory SRAM cell based on the temperature sensed as shown in fig 5).
Regarding claim 4, Houston teaches:
The apparatus of claim 3, wherein the circuitry is further operable to: increase the bias based at least in part on the temperature indicated by the at least one of the one or more temperature sensors; and (Houston, fig 1, 5, “[0036] bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown. [0023] In the illustrated embodiment, separate n-wells are employed, as shown. However, alternative embodiments may employ a common n-well for the first and second PMOS transistors 115b, 120b. Of course, alternative embodiments of the present invention may employ separate p-wells or a common p-well that operates as a back-gate to first and second NMOS transistors.”; a first bias path can be the dark line 505-506-510-511-515 of figure 5; that separate wells can have different bias voltages applied, that the n-wells 116 and 121, the n-wells can be biased together; additionally, the p-wells can be biased separately or together).
maintain a second bias that is applied to one or more second wells of the semiconductor component associated with one or more second transistors of the semiconductor component based at least in part on a second temperature indicated by at least one second temperature sensor of the one or more temperature sensors. (Houston, fig 1, 5, “[0038] Additionally, the temperatures of switching may be adjusted at test depending on the process corner ( e.g., switching to a lower n-well bias at a relatively higher temperature for strong NMOS/weak PMOS (SNWP) than for weak NMOS/ strong PMOS (WNSP)). For example, alternative bias voltage paths 505-506a-510 or 510-511a-515 for increasing SRAM temperatures and 515-514a-510 or 510-509a-505 for decreasing SRAM temperatures may be employed using temperature hysteresis for alternative first and second specified temperatures ts1a, ts2a, as shown in FIG. 5.”; a second, additional path can be the dotted line 505-506a-510 or 510-511a-515 to bias).
Regarding claim 6, Houston teaches The apparatus of claim 1, wherein the circuitry is operable to: compare temperatures indicated by the at least one of the one or more temperature sensors with the temperature threshold according to a periodicity; and determine that the temperature indicated by the at least one of the one or more temperature sensors satisfies the temperature threshold based at least in part on the comparing. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage. [0047] The temperature sensing mode established in the step 720 may be selected from several possibilities. These include a continuous mode, a periodic mode,”; a first and second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above the threshold ts1, or ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered).
Regarding claim 8, Houston teaches The apparatus of claim 1, wherein the one or more first operations, the one or more second operations, or both are associated with the circuitry accessing the one or more memory arrays. (Houston, fig 5, 7, “[0036] For increasing SRAM temperatures below the first and second specified temperatures ts1, ts2 , a bias voltage of about 1.5 volts is applied to a back-gate such as then-wells 116, 121 discussed with respect to FIG. 1. A bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown”; the semiconductor controller applies a different bias voltage to the wells based on the temperature sensed as shown in fig 5; the signal is processed and the voltage regulator applied different voltages to the associated well based on the temperature and the at least two threshold ts1 and ts2).
Regarding claim 9, Houston teaches The apparatus of claim 1, wherein the circuitry is further operable to: transmit a first indication that the semiconductor component is configured to operate in the second evaluation mode, a second indication that the semiconductor component is configured to cease evaluation operations, or both. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered. Note: only one condition is required for claim 9. If both had been required, then Lin cited above in claim 5 would have been combined to reject the claim).
Regarding claim 10, Houston teaches:
A method, comprising: receiving, at a semiconductor component, (Houston, fig 1, “[0021] The integrated circuit 100 includes a memory array, which is an SRAM array in the illustrated embodiment. The SRAM array has a plurality of SRAM memory cells, wherein a SRAM memory cell 110 is typical, [0038] Additionally, the temperatures of switching may be adjusted at test depending on the process corner ( e.g., switching to a lower n-well bias at a relatively higher temperature for strong NMOS/weak PMOS (SNWP) than for weak NMOS/ strong PMOS (WNSP)).”; an SRAM device with testing devices and an initial testing phase; that different results can be derived from test to include different bias voltages applied to different wells of the device).
an indication to operate in an evaluation mode; configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; (Houston, fig 1, 7, “[0022] The integrated circuit 100 also includes a thermostatic bias controller 135 having a temperature sensing circuit 140 and a voltage control circuit 145. The temperature sensing circuit 140 employs a temperature contact 140a to sense a temperature of the SRAM array. [0044] FIG. 7 illustrates a flow diagram of an embodiment of a method of operating a thermostatic bias controller, [0046] Then, an initial bias voltage setting for the memory array is determined in a step 715, a temperature sensing mode is established in a step 720 and bias voltage selections are provided in a step 725. [0047] The temperature sensing mode established in the step 720 may be selected from several possibilities. These include a continuous mode, a periodic mode,”; a thermistor bias controller 135 can be activated, the thermostat from each typical SRAM cell can be read based on a desired mode in step 720, and then a bias voltage selected in step 725; the system in step 720 creates an indication of time passed, and then the system receives an input from the thermometer 720, then the system evaluates the temperature to enter a new mode; initially the SRAM operates in a mode 0 as a default mode using the “initial bias voltage” of step 730).
performing one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; (Houston, fig 1, 7, 5, “[0050] An initial bias voltage is applied to at least one back-gate in the memory array in a step 730. [0050] Then, a decisional step 735 determines if temperature sensing of the memory array is currently activated. If temperature sensing is activated, the temperature is sensed in a step 740. Then, in a step 745 the bias voltage is set based on the temperature sensed in the step 740 employing either a single temperature transition or temperature hysteresis transitions for increasing and decreasing temperatures.”; an SRAM can be configured to test the temperature based on multiple modes; when the temperature sensing is activated in 735, then according to the sensed temperature, an operational is selected with any one of the three operating modes; the modes include different bias voltages for the semiconductor well; a mode zero may be selected initially, and a mode 1 may be selected based on an updated temperature which has risen above ts1. Note: the “configuring the semiconductor” in this rejection is based on the periodic or continuous sampling of the temperature sensor).
configuring the semiconductor component to operate in a second evaluation mode based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold in response to performing the one or more first operations, the second evaluation mode associated with a lower heat generation than the first evaluation mode; and performing one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to below ts2, after raising above ts2, then a mode x of operation is triggered and the bias voltage is reduced; at least four transitions can be made between the three operation modes using the ts1-ts2 threshold up and down).
Regarding claim 11, Houston teaches The method of claim 10, wherein configuring the semiconductor component to operate in the second evaluation mode further comprises: increasing a threshold voltage characteristic for one or more transistors of the semiconductor component during the second evaluation mode. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to below ts2, after raising above ts2, then a mode x of operation is triggered and the bias voltage is reduced; at least four transitions can be made between the three operation modes using the ts1-ts2 threshold up and down. Note: “increasing a threshold voltage characteristic” can be almost any relationship between the bias voltage, the transistor drain, source or gate. Clearly if the bias changes, then some relative voltage differences increase while others decrease assuming that the other voltages are held constant).
Regarding claim 14, Houston teaches The method of claim 10, wherein the temperature threshold is higher than a target temperature associated with evaluation of the semiconductor component. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered. Note: the “target temperature” has been interpreted as the temperature range below ts1; ts1 and ts2 are both higher than the desired/targeted temperature range for normal operation).
Regarding claim 15, Houston teaches The method of claim 10, further comprising: comparing temperatures indicated by the at least one temperature sensor with the temperature threshold according to a periodicity; and determining that the temperature indicated by the at least one temperature sensor satisfies the temperature threshold based at least in part on the comparing. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage. [0047] The temperature sensing mode established in the step 720 may be selected from several possibilities. These include a continuous mode, a periodic mode,”; a first and second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above the threshold ts1, or ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered).
Regarding claim 17, Houston teaches The method of claim 10, wherein the one or more first operations, the one or more second operations, or both are associated with circuitry of the semiconductor component accessing one or more memory arrays of the semiconductor component. (Houston, fig 5, 7, “[0036] For increasing SRAM temperatures below the first and second specified temperatures ts1, ts2 , a bias voltage of about 1.5 volts is applied to a back-gate such as then-wells 116, 121 discussed with respect to FIG. 1. A bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown”; the semiconductor controller applies a different bias voltage to the wells based on the temperature sensed as shown in fig 5; the signal is processed and the voltage regulator applied different voltages to the associated well based on the temperature and the at least two threshold ts1 and ts2).
Regarding claim 18, Houston teaches The method of claim 10, further comprising: transmitting a first indication that the semiconductor component is configured to operate in the second evaluation mode, a second indication that the semiconductor component is configured to cease evaluation operations, or both. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered. Note: only one condition is required for claim 9. If both had been required, then LIN cited above in claim 5 would have been combined to reject the claim).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Houston in view of LIN, et al, U.S. Patent Application Publication 20210281215 (“LIN”).
Houston teaches the apparatus of claim 1.
Houston does not explicitly teach wherein the circuitry is further operable to: configure the semiconductor component to cease evaluation operations based at least in part on a second temperature indicated by the one or more temperature sensors satisfying a second temperature threshold that is greater than the temperature threshold..
LIN teaches wherein the circuitry is further operable to: configure the semiconductor component to cease evaluation operations based at least in part on a second temperature indicated by the one or more temperature sensors satisfying a second temperature threshold that is greater than the temperature threshold. (LIN, paragraph 0040, “[0040] If the test poses a safety risk, as detected by samples reaching an ultimate max temperature, smoke sensors sensing smoke, the interface becoming unresponsive, a test administrator hitting a manual emergency stop, or other threshold being crossed, the output from the power supplies may be turned off or reduced and the test may be halted or truncated or otherwise altered.”; that during test operations, the process can be halted or ceased when an “ultimate max” temperatures is exceeded).
In view of the teachings of LIN it would have been obvious for a person of ordinary skill in the art to apply the teachings of LIN to Houston before the effective filing date of the claimed invention in order to teach computer operations in temperature dependent environment. The teachings of LIN, in the same or in a similar field of endeavor with Houston, can combine LIN’s explicit “ultimate max” temperature with Houston’s processes in increasing temperatures. The two temperature sensitive operations merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Houston in view of HWANG, et al, U.S. Patent Application Publication 20200265889 (“HWANG”).
Regarding claim 7, Houston teaches the apparatus of claim 1.
Houston teaches wherein configuring the semiconductor component to operate in the second evaluation mode is based at least in part on the value of the flag. (Houston, fig 5, 7, “[0036] For increasing SRAM temperatures below the first and second specified temperatures ts1, ts2 , a bias voltage of about 1.5 volts is applied to a back-gate such as then-wells 116, 121 discussed with respect to FIG. 1. A bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown”; the semiconductor controller applies a different bias voltage to the wells based on the temperature sensed as shown in fig 5).
Houston does not explicitly teach wherein the circuitry is further operable to: set a value of a flag of the semiconductor component based at least in part on the temperature satisfying the temperature threshold,.
HWANG teaches wherein the circuitry is further operable to: set a value of a flag of the semiconductor component based at least in part on the temperature satisfying the temperature threshold, (HWANG, fig 1, “[0018] The semiconductor memory device may further include a temperature sensor suitable for sensing the first and second temperature ranges, and generating a temperature flag signal corresponding to the sense result, and the controller may generate the first to third control signals based on the temperature flag signal, an active signal and a precharge signal.”; that a temperature sensor can pass the information to a controller using one of several means; one method is to use a flag associated with a first or second temperature threshold).
In view of the teachings of HWANG it would have been obvious for a person of ordinary skill in the art to apply the teachings of HWANG to Houston before the effective filing date of the claimed invention in order to teach computer operations in temperature dependent environment. The teachings of HWANG, in the same or in a similar field of endeavor with Houston, can combine HWANG’s explicit “flag” based on a temperature threshold with Houston’s implied communication between the sensor and controller. “The two communication methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Houston teaches the method of claim 10.
Houston teaches wherein configuring the semiconductor component to operate in the second evaluation mode is based at least in part on the value of the flag. (Houston, fig 5, 7, “[0036] For increasing SRAM temperatures below the first and second specified temperatures ts1, ts2 , a bias voltage of about 1.5 volts is applied to a back-gate such as then-wells 116, 121 discussed with respect to FIG. 1. A bias voltage path 505-506-510-511-515 using temperature hysteresis is employed to provide first and second bias voltage steps to about 1.7 volts and 1.9 volts, as shown”; the semiconductor controller applies a different bias voltage to the wells based on the temperature sensed as shown in fig 5).
Houston does not explicitly teach further comprising: setting a value of a flag of the semiconductor component based at least in part on the temperature satisfying the temperature threshold,.
HWANG teaches further comprising: setting a value of a flag of the semiconductor component based at least in part on the temperature satisfying the temperature threshold, (HWANG, fig 1, “[0018] The semiconductor memory device may further include a temperature sensor suitable for sensing the first and second temperature ranges, and generating a temperature flag signal corresponding to the sense result, and the controller may generate the first to third control signals based on the temperature flag signal, an active signal and a precharge signal.”; that a temperature sensor can pass the information to a controller using one of several means; one method is to use a flag associated with a first or second temperature threshold).
In view of the teachings of HWANG it would have been obvious for a person of ordinary skill in the art to apply the teachings of HWANG to Houston before the effective filing date of the claimed invention in order to teach computer operations in temperature dependent environment. The teachings of HWANG, in the same or in a similar field of endeavor with Houston, can combine HWANG’s explicit “flag” based on a temperature threshold with Houston’s implied communication between the sensor and controller. “The two communication methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Houston in view of ZOBEL, et al, U.S. Patent Application Publication 20150276851 (“ZOBEL”).
Houston teaches:
receive, at a semiconductor component, an indication to operate in an evaluation mode; (Houston, fig 1, “[0021] The integrated circuit 100 includes a memory array, which is an SRAM array in the illustrated embodiment. The SRAM array has a plurality of SRAM memory cells, wherein a SRAM memory cell 110 is typical, [0038] Additionally, the temperatures of switching may be adjusted at test depending on the process corner ( e.g., switching to a lower n-well bias at a relatively higher temperature for strong NMOS/weak PMOS (SNWP) than for weak NMOS/ strong PMOS (WNSP)).”; an SRAM device with testing devices and an initial testing phase; that different results can be derived from test to include different bias voltages applied to different wells of the device).
configure the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; (Houston, fig 1, 7, “[0022] The integrated circuit 100 also includes a thermostatic bias controller 135 having a temperature sensing circuit 140 and a voltage control circuit 145. The temperature sensing circuit 140 employs a temperature contact 140a to sense a temperature of the SRAM array. [0044] FIG. 7 illustrates a flow diagram of an embodiment of a method of operating a thermostatic bias controller, [0046] Then, an initial bias voltage setting for the memory array is determined in a step 715, a temperature sensing mode is established in a step 720 and bias voltage selections are provided in a step 725. [0047] The temperature sensing mode established in the step 720 may be selected from several possibilities. These include a continuous mode, a periodic mode,”; a thermistor bias controller 135 can be activated, the thermostat from each typical SRAM cell can be read based on a desired mode in step 720, and then a bias voltage selected in step 725; the system in step 720 creates an indication of time passed, and then the system receives an input from the thermometer 720, then the system evaluates the temperature to enter a new mode; initially the SRAM operates in a mode 0 as a default mode using the “initial bias voltage” of step 730).
perform one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; (Houston, fig 1, 7, 5, “[0050] An initial bias voltage is applied to at least one back-gate in the memory array in a step 730. [0050] Then, a decisional step 735 determines if temperature sensing of the memory array is currently activated. If temperature sensing is activated, the temperature is sensed in a step 740. Then, in a step 745 the bias voltage is set based on the temperature sensed in the step 740 employing either a single temperature transition or temperature hysteresis transitions for increasing and decreasing temperatures.”; an SRAM can be configured to test the temperature based on multiple modes; when the temperature sensing is activated in 735, then according to the sensed temperature, an operational is selected with any one of the three operating modes; the modes include different bias voltages for the semiconductor well; a mode zero may be selected initially, and a mode 1 may be selected based on an updated temperature which has risen above ts1. Note: the “configuring the semiconductor” in this rejection is based on the periodic or continuous sampling of the temperature sensor).
configure the semiconductor component to operate in a second evaluation mode based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold in response to performing the one or more first operations, the second evaluation mode associated with a lower heat generation than the first evaluation mode; and perform one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode. (Houston, fig 7, 5, “[0050] The method 700 then reverts to the decisional step 735 for further determination as it also does if the decisional step 735 determines that temperature sensing is not activated. [0035] FIG. 5 illustrates a graph of an embodiment of a multiple-level bias voltage, generally designated 500, employing temperature hysteresis as a function of SRAM temperature… In the illustrated embodiment, first and second specified temperatures ts1, ts2 are employed corresponding to three steps in bias voltage.”; a second evaluation mode is entered based on the step 720, the subsequent modes are sensed either continuously, periodically, or intermittently; during this second evaluation, IF the temperature changes to above ts2, then a mode 2 of operation is triggered; if below ts1, then the original mode 0 is triggered).
Houston does not explicitly teach A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:.
ZOBEL teaches A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: (ZOBEL, paragraph 0081, “[0081] Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.”; that instructions in a controller can be non-transitory and stored on a computer readable medium).
In view of the teachings of ZOBEL it would have been obvious for a person of ordinary skill in the art to apply the teachings of ZOBEL to Houston before the effective filing date of the claimed invention in order to teach computer operations in temperature dependent environment. The teachings of ZOBEL, in the same or in a similar field of endeavor with Houston, can combine ZOBEL’s explicit computer readable medium to execute temperature thresholds with Houston’s implied software executed by the controller. “The two controlling methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825