Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ladhani et al. (US 20230128387 A1) in view of Noori et al. (US 20140312976 A1), hereafter referred to as “Ladhani” and “Noori”, respectively.
Regarding claims 1-5, 8-12, and 15-18 in the embodiment of Figs. 1 and 2, Ladhani discloses:
An integrated circuit (Figs. 1 and 2) comprising:
a plurality of antennas (Fig. 5, antenna 608, load 104 in Fig. 1 and 2 may also be an antenna per paragraph [0027] lines 1-4, per claims 8 and 15);
a plurality of receiver channels configured to process signals being received by the plurality of antennas (paragraph [0037], lines 23-28 per claim 15);
a plurality of transmission channels, wherein a transmission channel (per paragraph [0002] lines 3-6 per claims 8 and 15) comprises an amplifier module comprising:
a pre-driver stage (Fig. 2, predriver 202, as per claims 5 and 12) configured to amplify an input signal (RF_in) to generate a first amplified signal;
a driver stage (Fig. 2, driver 204) configured to amplify the first amplified signal to generate a second amplified signal (per paragraph [0028]); and
a final stage (Figs. 1 and 2, elements 121, 122, 123, 101, 102, 103, and 130 form the final stage) configured to amplify the second amplified signal to generate an output amplified signal (output RF signal RF_out, shown in Fig. 1), wherein
the final stage is implemented by a Doherty amplifier comprising:
a peak amplifier (peaking amplifier stages 102/103);
a main amplifier (carrier (or main) amplifier stage 101), wherein a first GaN device configured as the peak amplifier and a second GaN device configured as the main amplifier (paragraph [0020] lines 21-23, carrier and peaking amplifier stages 101-103 a may be Gallium Nitride (GaN) transistors per claims 2, 9, and 16);
a peak input matching network (input matching network 122 and/or 123 for peaking amplifier stages 102 and 103);
a peak output matching network (Fig. 1, resonator circuits 125 and 126, resonator circuits are known in the art to function as matching circuits) comprising a first matching section (Fig. 1, impedance matching circuitry 108);
a main input matching network (Figs. 1 and 2, input matching networks 121) comprising a harmonic trapping section (Fig. 2, harmonic trap 211) configured to trap a second harmonic of the second amplified signal (paragraph [0040], harmonics traps reduce harmonics of the first split RF signal, the second split RF signal, and the third split RF signal), wherein
the harmonic trapping section of the main input matching network is implemented by a LC circuit in a shunt arrangement (harmonic trap 211 is an LC circuit in a shunt arrangement, as shown in Fig. 2 per claims 4, 11, and 18); and
a main output matching network (resonator circuits 124), wherein
the first matching section of the peak output matching network are implemented by at least one of microstrip lines and lump elements (paragraph [0025] lines 18-20, the resonator circuits 124, 125, 126 can be used for realizing lumped equivalents of quarter wave transmission lines per claims 3, 10, and 17).
However, Ladhani is silent in teaching a second matching section, wherein the first matching section and the second matching section perform different impedance matching and the pre-driver stage is implemented by a Gallium Arsenide (GaAs) device.
Noori teaches:
a second matching section (impedance matching circuitry 108 and impedance matching element 180 form two separate matching sections), wherein the first matching section and the second matching section perform different impedance matching (matching element 180 matches the impedances at the inputs to the power combiner 160, per paragraph [0017] lines 23-27, and matching circuitry 108 is configured to provide a desired output impedance at the output 132 of the integrated circuit 114 per paragraph [0010] lines 14-19).
It would then have been obvious to have replaced output matching network in Ladhani (Fig. 1) with output match network taught by Noori (Fig. 1) with two match sections to match impedances at the power combiner (per paragraph [0017] lines 23-27), thereby suggesting the obviousness of such a combination. It would have been further obvious to modify the pre-driver stage as stage taught by Ladhani to be implemented by a Gallium Arsenide (GaAs) device as taught by Ladhani (paragraph [0004] lines 1-11, GaAs devices are a commonly used material for power amplifiers), thereby suggesting the obviousness of such a modification.
Claims 6, 7, 13, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ladhani et al. (US 20230128387 A1) and Noori et al. (US 20140312976 A1) in further view of Brewer (US 20230140451 A1), hereafter referred to as “Ladhani”, “Noori”, and “Brewer”, respectively.
Regarding claims 6, 7, 13, 14, 19, and 20, Ladhani and Noori teaches:
the driver stage (Ladhani, Fig. 2, driver 204) comprises:
a first amplifier (driver 204 is an amplifier, as shown in Fig. 2) configured to amplify the first intermediate signal to generate a first amplified intermediate signal;
However, Ladhani and Noori does not teach:
a first hybrid coupler configured to:
split the first amplified signal into a first intermediate signal and a second intermediate signal;
absorb reflections resulted from mismatches between the first intermediate signal and the second intermediate signal;
a second amplifier configured to amplify the second intermediate signal to generate a second amplified intermediate signal;
a second hybrid coupler configured to:
absorb reflections resulted from mismatches between the first amplified intermediate signal and the second amplified intermediate signal; and
combine the first amplified intermediate signal and the second intermediate amplified signal to generate the second amplified signal, and wherein the first hybrid coupler and the second hybrid coupler are quadrature couplers.
Brewer teaches:
a first hybrid coupler (Fig. 1C, quadrature couplers 18_1) configured to:
split the first amplified signal into a first intermediate signal and a second intermediate signal (per paragraph [0011] for RF input 11);
absorb reflections resulted from mismatches between the first intermediate signal and the second intermediate signal (hybrid couplers inherently absorb reflections when one end is connected to a load, (i.e. the element 17), as taught in paragraph [0010] where all reflections are directed to port 4);
a second amplifier (second amplifier 15 of transistor amplifier configuration 10) configured to amplify the second intermediate signal to generate a second amplified intermediate signal;
a second hybrid coupler (quadrature hybrid coupler 18_2) configured to:
absorb reflections resulted from mismatches between the first amplified intermediate signal and the second amplified intermediate signal (port 1 of 18_2 acts as an isolated port wherein outputs reflections or differences between other ports per paragraph [0010]); and
combine the first amplified intermediate signal and the second intermediate amplified signal to generate the second amplified signal (quadrature hybrid coupler 18_2 may act as a combiner to combine the output from the first and second amplifiers 14, 15 to provide the output signal 19 per paragraph [0012]), and wherein the first hybrid coupler and the second hybrid coupler are quadrature couplers (as shown in Fig. 1C, quadrature hybrid coupler 18_1 and 18_2 per paragraph [0011]).
It would then have been obvious to have replaced the driver stage amplifier in Ladhani (Fig. 2) with the amplifier circuit taught by Brewer (Fig. 1C or 1D), to direct all reflections to the isolated ports in input and output impedance mismatches (per paragraph [0010]), thereby suggesting the obviousness of such a combination.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
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