DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain et al (US 6498360).
Regarding Claim 1, Jain et al discloses a flash memory device (MODFET/MOSFET [column 3, lines 1-11] Fig 2a), comprising:
a substrate (10 [column 3, lines 20-42] Fig 2a);
a semiconductor quantum well layer (11 and 20 [column 3, lines 20-42] Fig 2a) formed of a first semiconductor material (InGaAs/InAlA coupled-well layer 20 [column 3, lines 20-42]) and disposed over the substrate (10 Fig 2a);
a semiconductor spacer (spacer 12 [column 3, lines 20-42] Fig 2a) formed of a second semiconductor material (undoped InAlAs spacer layer 12 [column 3, lines 20-42]) and disposed over the semiconductor quantum well layer (11 and 20 [column 3, lines 20-42] Fig 2a);
a semiconductor channel layer (supply layer 13 [column 3, lines 20-42] Fig 2a) formed of the first semiconductor material and disposed over the semiconductor spacer (12 Fig 2a);
a gate structure (gate 17 [column 3, lines 20-42] Fig 2a) over the semiconductor channel layer (13 Fig 2a); and
source/drain regions (source 14 and drain 15 [column 3, lines 20-42] Fig 2a) over the substrate (10 Fig 2a) and on opposite sides of the gate structure (17 Fig 2a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Tan et al (US 2004/0213312).
Regarding Claim 2, Jain et al discloses the limitations of claim 1 as explained above. Jain et al does not disclose
wherein the semiconductor spacer is thicker than the semiconductor quantum well layer and the semiconductor channel layer.
Tan et al, in the related art of semiconductor devices that include quantum well layers, discloses
wherein the semiconductor spacer (spacer layer 27 [0016] Fig 2) is thicker than the semiconductor quantum well layer (quantum well layer 25 [0016] Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al to include wherein the semiconductor spacer is thicker than the semiconductor quantum well layer as taught by Tan et al in order to optimize wavelength of light in an optical mode while optimizing the location so that the active region can be placed close enough to the electric field maximum [0029] and because it would have been an obvious matter of design choice to optimize the size of the spacer layer relative to the quantum well layer since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Jain et al and Tan et al now discloses
wherein the semiconductor spacer (spacer layer 27 [0016] Fig 2) is thicker than the semiconductor quantum well layer (quantum well layer 25 [0016] Fig 2/11 and 20 Fig 2a Jain et al) and the semiconductor channel layer (13 Fig 2a Jain et al).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Pillarisetty et al (US 2011/0156005).
Regarding Claim 3, Jain et al discloses the limitations of claim 1 as explained above. Jain et al does not disclose
wherein a germanium atomic percentage of the semiconductor spacer is higher than a germanium atomic percentage of the semiconductor quantum well layer and a germanium atomic percentage of the semiconductor channel layer.
Pillarisetty et al, in the related art of semiconductor devices that include FET devices, discloses
wherein there being a higher percentage of silicon in a portion of the spacer region further from the quantum well region and a lower percentage of silicon in the spacer region closer to the quantum well region (claim 35).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al to include a spacer layer that has the highest germanium content as taught by Pillarisetty et al in order to improve performance (abstract). Further, a person of ordinary skill in the art would have recognized that having a higher germanium content than the silicon content in the spacer layer would improve the electrical functioning of the device (see MPEP 2143.I(D)).
The combination of Jain et al and Pillarisetty et al now discloses
wherein a germanium atomic percentage of the semiconductor spacer (spacer 12 [column 3, lines 20-42] Fig 2a Jain et al) is higher than a germanium atomic percentage (germanium concentration (abstract) Pillarisetty et al) of the semiconductor quantum well layer (11 and 20 [column 3, lines 20-42] Fig 2a Jain et al) and a germanium atomic percentage (germanium concentration (abstract) Pillarisetty et al) of the semiconductor channel layer (13 Fig 2a Jain et al).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Takazawa et al (JPH09298293).
Regarding Claim 4, Jain et al discloses the limitations of claim 1 as explained above. Jain et al does not disclose
further comprising a strain relaxed buffer layer between the semiconductor quantum well layer and the substrate.
Takazawa et al, in the related art of semiconductor devices that include transistors, discloses
further comprising a strain relaxed buffer layer (non-doped InAlAs 2 serving as a buffer layer the relaxes strain [page 4, lines 12-14] Fig 3) on the substrate (substrate 1 [page 5, lines 1-5] Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al ton include a strain relaxed buffer layer as taught by Takazawa et al in order to enhance crystal growth [page 4, lines 12-14]. Further, a person of ordinary skill in the art would have recognized that having a strain relaxed buffer layer would help avoid undesirable damage and would improve the crystal quality of the layers of the device (see MPEP 2143.I(D)).
The combination of Jain et al and Takazawa et al now dislcoses
further comprising a strain relaxed buffer layer (non-doped InAlAs 2 serving as a buffer layer the relaxes strain [page 4, lines 12-14] Fig 3) between the semiconductor quantum well layer (11 and 20 [column 3, lines 20-42] Fig 2a Jain et al) and the substrate (1 Fig 3).
Regarding Claim 5, the combination of Jain et al and Takazawa et al discloses the limitations of claim 4 as explained above. The combination of Jain et al and Takazawa et al further discloses
wherein the strain relaxed buffer layer (2 Fig 3 Takazawa et al) is formed of the second semiconductor material (non-doped InAlAs 2 serving as a buffer layer the relaxes strain [page 4, lines 12-14] Fig 3 Takazawa et al).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Ando et al (US 5920231).
Regarding Claim 3, Jain et al discloses the limitations of claim 1 as explained above. Jain et al does not disclose
wherein the semiconductor quantum well layer, the semiconductor spacer, and the semiconductor channel layer are un-doped.
Ando et al, in the related art of semiconductor devices that include quantum well layers, discloses
wherein the semiconductor quantum well layer (undoped quantum well layer 25A [column 7, lines 1-41 Fig 3A-B), the semiconductor spacer (undoped spacer layer 25C-1 [column 7, lines 1-41] Fig 3A-B), and the semiconductor channel layer (undoped channel layer 22 [column 7, lines 1-41] Fig 3A) are un-doped.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al to include where the quantum well layer, the spacer, and the channel layer are undoped as taught by Ando et al in order to reduce ionized impurity scattering and electrical noise. Further, a person of ordinary skill in the art would have recognized that avoiding electrical noise would be advantageous in optimizing electron mobility and electrical functioning of the device (see MPEP 2143.I(D)).
Claim 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Torii (US 7079423).
Regarding Claim 8, Jain et al discloses the limitations of claim 1 as explained above. Jain et al does not disclose
wherein a voltage for programming the flash memory device is a positive voltage, and a voltage for erasing the flash memory device is a negative voltage.
Torii, in the related art of semiconductor devices that include memory devices, discloses
wherein a voltage for programming (programming [column 7, lines 45-67]) the flash memory device (dual bit flash memory [column 7, lines 35-46]) is a positive voltage (positive voltage [column 7, lines 45-67]), and a voltage for erasing the flash memory device is a negative voltage (applying a negative voltage to the erase process [column 8, lines 15-25]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed in invention to modify Jain et al to include applying a positive voltage to the programming process and a negative voltage to the erasing process as taught by Torii in order to have electrons that are trapped in the in the film removed which is part of the data erase operation [column 4, lines 55-65]. Further, a person of ordinary skill in the art would have recognized that a process that repels trapped electrons out of the floating gate would be advantageous in reducing power consumption and reducing stress which would improve the functioning, reliability, and durability of the device (see MPEP 2143.I(D)).
Regarding Claim 9, Jain et al discloses the limitations of claim 1 as explained above. Jain et al does not disclose
wherein an absolute value of a minimum voltage for programming the flash memory device is lower than an absolute value of a maximum voltage for erasing the flash memory device.
Torii, in the related art of semiconductor devices that include memory devices, discloses
wherein an absolute value of a minimum voltage (5V [column 7, lines 45-67]) for programming (programming [column 7, lines 45-67]) the flash memory device (dual bit flash memory [column 7, lines 35-46]) is lower than an absolute value of a maximum voltage (-6V [column 8, lines 15-25]) for erasing (applying a negative voltage to the erase process [column 8, lines 15-25]) the flash memory device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al to include wherein an absolute value of a minimum voltage for programming the flash memory device is lower than an absolute value of a maximum voltage for erasing the flash memory device as taught by Torii in order to have electrons that are trapped in the in the film removed which is part of the data erase operation [column 4, lines 55-65], which may require a strong electric field across a larger area. Further, a person of ordinary skill in the art would have recognized that having a larger absolute value of voltage during the erasing process would allow for more removal of the trapped electrons, which would help in having an improved erasing process (see MPEP 2143.I(D)).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912).
Regarding Claim 10, Jain et al discloses an integrated circuit (semiconductor field effect transistor device MODFET/MOSFET [column 3, lines 1-11] Fig 2a), comprising:
a substrate (10 [column 3, lines 20-42] Fig 2a);
a flash memory device (MODFET/MOSFET [column 3, lines 1-11] Fig 2a) over a first region of the substrate (10 Fig 2a), comprising:
a first portion of a first semiconductor layer (11 and 20 [column 3, lines 20-42] Fig 2a) over the substrate (10 Fig 2a);
a first portion of a semiconductor spacer (spacer 12 [column 3, lines 20-42] Fig 2a) over the first semiconductor layer (20 Fig 2a);
a first portion of a second semiconductor layer (supply layer 13 [column 3, lines 20-42] Fig 2a) over the semiconductor spacer (12 Fig 2a);
first source/drain regions (source 14 and drain 15 [column 3, lines 20-42] Fig 2a) over the substrate (10 Fig 2a); and
a first gate structure (gate 17 [column 3, lines 20-42] Fig 2a) over the second semiconductor layer (13 Fig 2a) and between the first source/drain regions (source 14 and drain 15 [column 3, lines 20-42] Fig 2a).
Jain et al does not disclose
a gate-defined quantum dot device over a second region of the substrate, comprising:
a second portion of the first semiconductor layer over the substrate;
a second portion of the semiconductor spacer over the first semiconductor layer;
a second portion of the second semiconductor layer over the semiconductor spacer;
second source/drain regions over the substrate; and
a second gate structure and
a third gate structure over the second semiconductor layer, wherein the second gate structure and the third gate structure are between the second source/drain regions.
Gendrier et al, in the related art of semiconductor devices that include memory devices, discloses
a first device (shown in annotated Fig 3, Fig 3a, Fig 3b) over a first region (shown in annotated Fig 3, Fig 3a, Fig 3b) of the substrate (substrate SB [0035] Fig 3, Fig 3a, Fig 3b);
first source/drain regions (source S and drain D [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) over the substrate (SB Fig 3, Fig 3a, Fig 3b); and
a first gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) over the second semiconductor layer (channel regions [0039]) and between the first source/drain regions (S and D shown in annotated Fig 3, Fig 3a, Fig 3b); and
a gate-defined device over a second region (shown in annotated Fig 3, Fig 3a, Fig 3b) of the substrate (SB Fig 3, Fig 3a, Fig 3b), comprising:
second source/drain regions (shown in annotated Fig 3, Fig 3a, Fig 3b) over the substrate (SB Fig 3, Fig 3a, Fig 3b); and
a second gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) and
a third gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b), wherein the second gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) and the third gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) are between the second source/drain regions (shown in annotated Fig 3, Fig 3a, Fig 3b).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al to include a gate-defined quantum dot device as taught by Gendrier et al in order to help preserve the device from the aging process when electrons are stored in the floating gate and are extracted and sent to the source, drain, and channel regions of the transistor [0003]-[0004]. Further, a person of ordinary skill in the art would have recognized that having a second device expand the functioning capability of the integrated circuit device (see MPEP 2143.I(D)).
The combination of Jain et al and Grendrier et al now discloses
a gate-defined quantum dot device (gate-defined device shown above in annotated Fig 3, Fig 3a, Fig 3b Gendrier et al/a semiconductor quantum well layer (11 and 20 [column 3, lines 20-42] Fig 2a Jain et al)).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and in further view of Takazawa et al (JPH09298293).
Regarding Claim 11, the combination of Jain et al and Gendrier et al discloses the limitations of claim 10 as explained above. The combination of Jain et al and Gendrier et al does not disclose
further comprising: a strain relaxed buffer layer between the substrate and the first semiconductor layer.
Takazawa et al, in the related art of semiconductor devices that include transistors, discloses
further comprising a strain relaxed buffer layer (non-doped InAlAs 2 serving as a buffer layer the relaxes strain [page 4, lines 12-14] Fig 3) on the substrate (substrate 1 [page 5, lines 1-5] Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al and Gendrier et al to include a strain relaxed buffer layer as taught by Takazawa et al in order to enhance crystal growth [page 4, lines 12-14]. Further, a person of ordinary skill in the art would have recognized that having a strain relaxed buffer layer would help avoid undesirable damage and would improve the crystal quality of the layers of the device (see MPEP 2143.I(D)).
The combination of Jain et al, Gendrier et al, and Takazawa et al now discloses
further comprising: a strain relaxed buffer layer (non-doped InAlAs 2 serving as a buffer layer the relaxes strain [page 4, lines 12-14] Fig 3 Takazawa et al) between the substrate (1 Fig 3 Takazawa et al) and the first semiconductor layer (11 and 20 [column 3, lines 20-42] Fig 2a Jain et al).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and in further view of Tassig et al (US 2012/0113087).
Regarding Claim 13, the combination of Jain et al and Gendrier et al discloses the limitations of claim 10 as explained above. The combination of Jain et al and Gendrier et al does not disclose
wherein the second and third gate structures have separated gate metals but a shared gate dielectric.
Tassig et al, in the related art of semiconductor devices that include transistors, discloses
wherein the second (metal layer 222D and microcrystalline silicon layer 220D [0043] Fig 4) and third gate structures (metal layer 222E and microcrystalline silicon layer 220E [0043] Fig 4) have separated gate metals but a shared gate dielectric (gate dielectric 216D [0043] Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al and Gendrier et al to include wherein the second and third gate structures have separated gate metals but a shared gate dielectric as taught by Tassig et al in order to allow independent electrical control while maintaining a uniform high-quality interface with the semiconductor substrate which allows for precise threshold voltage tuning and suppressed leakage currents. Further, a person of ordinary skill in the art would have recognized that having suppressed leakage currents would improve the reliability and durability of the device (see MPEP 2143.I(D)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and in further view of Pillarisetty et al (US 2011/0156005).
Regarding Claim 14, the combination of Jain et al and Gendrier et al discloses the limitations of claim 1 as explained above. The combination of Jain et al and Gendrier et al does not disclose
wherein a germanium atomic percentage of the semiconductor spacer is higher than a germanium atomic percentage of the first semiconductor layer and a germanium atomic percentage of the second semiconductor layer.
Pillarisetty et al, in the related art of semiconductor devices that include FET devices, discloses
wherein there being a higher percentage of silicon in a portion of the spacer region further from the quantum well region and a lower percentage of silicon in the spacer region closer to the quantum well region (claim 35).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al and Gendrier et al to include a spacer layer that has the highest germanium content as taught by Pillarisetty et al in order to improve performance (abstract). Further, a person of ordinary skill in the art would have recognized that having a higher germanium content than the silicon content in the spacer layer would improve the electrical functioning of the device (see MPEP 2143.I(D)).
The combination of Jain et al and Pillarisetty et al now discloses
wherein a germanium atomic percentage of the semiconductor spacer (spacer 12 [column 3, lines 20-42] Fig 2a Jain et al) is higher than a germanium atomic percentage (germanium concentration (abstract) Pillarisetty et al) of the first semiconductor layer (11 and 20 [column 3, lines 20-42] Fig 2a Jain et al) and a germanium atomic percentage (germanium concentration (abstract) Pillarisetty et al) of the second semiconductor layer (13 Fig 2a Jain et al).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and in further view of Tan et al (US 2004/0213312).
Regarding Claim 15, the combination of Jain et al and Gendrier et al discloses the limitations of claim 10 as explained above. The combination of Jain et al and Gendrier et al does not disclose
wherein the semiconductor spacer is thicker than the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is thicker than the second semiconductor layer.
Tan et al, in the related art of semiconductor devices that include quantum well layers, discloses
wherein the semiconductor spacer (spacer layer 27 [0016] Fig 2) is thicker than the semiconductor quantum well layer (quantum well layer 25 [0016] Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al and Gendrier et al to include wherein the semiconductor spacer is thicker than the semiconductor quantum well layer as taught by Tan et al in order to optimize wavelength of light in an optical mode while optimizing the location so that the active region can be placed close enough to the electric field maximum [0029] and because it would have been an obvious matter of design choice to optimize the size of the spacer layer relative to the quantum well layer since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Jain et al, Gendrier et al, and Tan et al now discloses
wherein the semiconductor spacer (spacer layer 27 [0016] Fig 2) is thicker than the first semiconductor layer (quantum well layer 25 [0016] Fig 2/11 and 20 Fig 2a Jain et al) and the second semiconductor layer (13 Fig 2a Jain et al); and
the first semiconductor layer (11 and 20 Fig 2a Jain et al) is thicker than the second semiconductor layer (13 Fig 2a Jain et al).
Claims 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and in further view of Pillarisetty et al (US 2011/0156005).
Regarding Claim 16, Jain et al discloses
a flash memory device (MODFET/MOSFET [column 3, lines 1-11] Fig 9) over a first region of the substrate (10 [column 3, lines 20-42] Fig 9), comprising:
a first portion of a first silicon layer (first p-doped Si layer 11 and ND well 20 having at least two SiGe coupled sub-wells 23 and 25 separated via a thin Si barrier 24 [column 6, lines 36-67] Fig 9) over the substrate (10 Fig 9);
a first portion of a silicon spacer (spacer Si layer 12 [column 6, lines 21-36] Fig 9) over the first silicon layer (11, 20, 23, 24, 25 Fig 9);
a first portion of a second silicon layer (electron supply Si layer 13 [column 6, lines 1-36] Fig 9) over the silicon spacer (12 Fig 9);
first source/drain regions (source 14 and drain 15 [column 3, lines 20-42] Fig 9) over the substrate (10 Fig 9); and
a first gate structure (gate 17 [column 3, lines 20-42] Fig 9) over the second silicon layer (13 Fig 9) and between the first source/drain regions (14 and 15 Fig 9).
Jain et al does not disclose
an integrated circuit, comprising:
a first portion of a silicon germanium spacer over the first silicon layer;
a first portion of a second silicon layer over the silicon germanium spacer;
a gate-defined quantum dot device over a second region of the substrate, comprising: a
second portion of the first silicon layer over the substrate;
a second portion of the silicon germanium spacer over the first silicon layer;
a second portion of the second silicon layer over the silicon germanium spacer;
second source/drain regions over the substrate; and
a second gate structure and a third gate structure over second silicon layer, wherein the second gate structure and the third gate structure are between the second source/drain regions.
Gendrier et al, in the related art of semiconductor devices that include memory devices, discloses
an integrated circuit (integrated circuit [0035]), comprising:
a gate-defined quantum dot device (device with wells RG1, RG2, and RG3 [0035] shown in annotated Fig 3, Fig 3a, Fig 3b) over a second region (shown in annotated Fig 3, Fig 3a, Fig 3b) of the substrate (substrate SB [0035] Fig 3, Fig 3a, Fig 3b), comprising:
a second portion of the first silicon layer (wells RG1, RG2, RG3 shown in annotated Fig 3, Fig 3a, Fig 3b) over the substrate (SB Fig 3, Fig 3a, Fig 3b);
second source/drain regions (shown in annotated Fig 3, Fig 3a, Fig 3b) over the substrate (SB Fig 3, Fig 3a, Fig 3b); and
a second gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) and a third gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) over second silicon layer (channel regions [0039]), wherein the second gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) and the third gate structure (gate FG [0038] shown in annotated Fig 3, Fig 3a, Fig 3b) are between the second source/drain regions (shown in annotated Fig 3, Fig 3a, Fig 3b).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jain et al to include a gate-defined quantum dot device as taught by Gendrier et al in order to help preserve the device from the aging process when electrons are stored in the floating gate and are extracted and sent to the source, drain, and channel regions of the transistor [0003]-[0004]. Further, a person of ordinary skill in the art would have recognized that having a second device expand the functioning capability of the integrated circuit device (see MPEP 2143.I(D)).
The combination of Jain et al and Gendrier et al does not disclose
a first portion of a silicon germanium spacer over the first silicon layer;
a first portion of a second silicon layer over the silicon germanium spacer;
a second portion of the silicon germanium spacer over the first silicon layer; and
a second portion of the second silicon layer over the silicon germanium spacer.
Pillarisetty et al, in the related art of semiconductor devices that include FET devices, discloses
a silicon germanium spacer (spacer region 110 comprises SiGe [0030] Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al and Gendrier et al to include a silicon germanium spacer as taught by Pillarisetty et al in order to optimize the electron mobility of the device. Further, a person of ordinary skill in the art would have recognized that optimizing the electron mobility of the device would improve the electrical functioning capability of the device (see MPEP 2143.I(D)). Additionally, a person of ordinary skill in the art would have recognized that having a SiGe spacer would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate)).
The combination of Jain et al, Gendrier et al, and Pillarisetty et al now discloses
a first portion of a silicon germanium spacer (110 Fig 1 Pillarisetty et al) over the first silicon layer (first p-doped Si layer 11 and ND well 20 having at least two SiGe coupled sub-wells 23 and 25 separated via a thin Si barrier 24 [column 6, lines 36-67] Fig 9 Jain et al);
a first portion of a second silicon layer (channel layers [0039] Fig 3, Fig 3a, Fig 3b Gendrier et al) over the silicon germanium spacer (110 Fig 1 Pillarisetty et al);
a second portion of the silicon germanium spacer (110 Fig 1 Pillarisetty et al) over the first silicon layer (first p-doped Si layer 11 and ND well 20 having at least two SiGe coupled sub-wells 23 and 25 separated via a thin Si barrier 24 [column 6, lines 36-67] Fig 9 Jain et al); and
a second portion of the second silicon layer (channel region [0039] Fig 3, Fig 3a, Fig 3b Gendrier et al) over the silicon germanium spacer (110 Fig 1 Pillarisetty et al).
Regarding Claim 17, the combination of Jain et al, Gendrier et al, and Pillarisetty et al discloses the limitations of claim 16 as explained above. The combination of Jain et al, Gendrier et al, and Pillarisetty et al further discloses
wherein, the second gate structure (gate FG [0038] shown above in annotated Fig 3, Fig 3a, Fig 3b Gendrier) comprises a first gate dielectric layer (gate oxide OX [0037] Fig 3, Fig 3a, Fig 3b Gendrier et al) and a first gate metal (gate electrode portion of FG shown above in annotated Fig 3, Fig 3a, and Fig 3b Gendrier et al), the third gate structure (gate FG [0038] shown above in annotated Fig 3, Fig 3a, Fig 3b Gendrier et al) comprises a second gate dielectric layer (gate oxide OX [0037] Fig 3, Fig 3a, Fig 3b Gendrier et al) and a second gate metal (gate electrode portion of FG shown above in annotated Fig 3, Fig 3a, and Fig 3b Gendrier et al), and the first gate metal (gate electrode portion of FG shown above in annotated Fig 3, Fig 3a, and Fig 3b Gendrier et al) is spaced apart from the second gate metal (gate electrode portion of FG shown above in annotated Fig 3, Fig 3a, and Fig 3b Gendrier et al).
Regarding Claim 19, the combination of Jain et al, Gendrier et al, and Pillarisetty et al discloses the limitations of claim 16 as explained above. The combination of Jain et al, Gendrier et al, and Pillarisetty et al further discloses
wherein the second gate structure (gate FG [0038] shown above in annotated Fig 3, Fig 3a, Fig 3b Gendrier et al) and the third gate structure (gate FG [0038] shown above in annotated Fig 3, Fig 3a, Fig 3b Gendrier et al) are laterally between the second source/drain regions (shown above in annotated Fig 3, Fig 3a, Fig 3b Gendrier et al).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and Pillarisetty et al (US 2011/0156005), and in further view of Tassig et al (US 2012/0113087).
Regarding Claim 18, the combination of Jain et al, Gendrier et al, and Pillarisetty et al discloses the limitations of claim 17 as explained above. The combination of Jain et al, Gendrier et al, and Pillarisetty et al does not disclose
wherein the first gate dielectric layer is in contact with the second gate dielectric layer.
Tassig et al, in the related art of semiconductor devices that include transistors, discloses
wherein the second (metal layer 222D and microcrystalline silicon layer 220D [0043] Fig 4) and third gate structures (metal layer 222E and microcrystalline silicon layer 220E [0043] Fig 4) have separated gate metals but a shared gate dielectric (gate dielectric 216D [0043] Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al, Gendrier et al, and Pillarisetty et al to include wherein the second and third gate structures have separated gate metals but a shared gate dielectric as taught by Tassig et al in order to allow independent electrical control while maintaining a uniform high-quality interface with the semiconductor substrate which allows for precise threshold voltage tuning and suppressed leakage currents. Further, a person of ordinary skill in the art would have recognized that having suppressed leakage currents would improve the reliability and durability of the device (see MPEP 2143.I(D)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 6498360) in view of Gendrier et al (US 2005/0219912), and Pillarisetty et al (US 2011/0156005), and in further view of Tan et al (US 2004/0213312).
Regarding Claim 20, the combination of Jain et al, Gendrier et al, and Pillarisetty et al discloses the limitations of claim 16 as explained above. The combination of Jain et al, Gendrier et al, and Pillarisetty et al does not disclose
wherein the silicon germanium spacer is thicker than the first silicon layer and the second silicon layer, and the first silicon layer is thicker than the second silicon layer.
Tan et al, in the related art of semiconductor devices that include quantum well layers, discloses
wherein the semiconductor spacer (spacer layer 27 [0016] Fig 2) is thicker than the semiconductor quantum well layer (quantum well layer 25 [0016] Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jain et al, Gendrier et al, and Pillarisetty et al to include wherein the semiconductor spacer is thicker than the semiconductor quantum well layer as taught by Tan et al in order to optimize wavelength of light in an optical mode while optimizing the location so that the active region can be placed close enough to the electric field maximum [0029] and because it would have been an obvious matter of design choice to optimize the size of the spacer layer relative to the quantum well layer since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Jain et al, Gendrier et al, Pillarisetty et al, and Tan et al now discloses
wherein the silicon germanium spacer (110 Fig 1 Pillarisetty et al) is thicker than the first silicon layer (quantum well layer 25 [0016] Fig 2 Tan et al) and the second silicon layer (13 Fig 9 Jain et al), and the first silicon layer (11 and 20 Fig 9 Jain et al) is thicker than the second silicon layer (13 Fig 9 Jain et al).
Allowable Subject Matter
Claims 7 and 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7: The prior art does not anticipate or render obvious, alone or in combination, that “wherein in a program operation of the flash memory device, a drain current increases when a gate voltage applied to the gate structure increases from a first level to a second level, the drain current is saturated when the gate voltage applied to the gate structure increases from the second level to a third level, and the drain current decreases when the gate voltage applied to the gate structure increases from the third level to a fourth level,” in the combination required by the claim.
Claim 12: The prior art does not anticipate or render obvious, alone or in combination, that “wherein bottom surfaces of the first source/drain regions are lower than a top surface of the strain relaxed buffer layer and are higher than a bottom surface of the strain relaxed buffer layer,” in the combination required by the claim.
Specifically, in the prior art reference Jain et al, the bottom surfaces of the first source/drain regions are below the top surface of the quantum well layer 11 (Fig 2a Jain et al) but not below the bottom surface of quantum well layer 11 (Fig 2a Jain et al). The prior art reference Gendrier et al does not remedy this issue, which means that when the buffer layer (non-doped InAlAs 2 serving as a buffer layer the relaxes strain [page 4, lines 12-14] Fig 3 Takazawa et al) is applied from the prior art reference Takazawa et al, the top surface of the buffer layer would be below the bottom surface of the quantum well layer and would therefore be below the bottom surfaces of the first source/drain regions, which would not meet the limitations of the claim. Further, should another prior art reference be found that discloses this feature, it would not be obvious to a person of ordinary skill in the art to combine the references to modify the combination of Jain et al, Gendrier et al, and Takazawa et al in this manner.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al (US 2020/0363662) which discloses a stack that includes spacer layers, multiple quantum well layers, and barrier layers [0007], and Rogers et al (US 2008/0151590) which discloses and insulated gate field effect transistor [0002].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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