DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. US 12,052,048. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – see table below for comparison.
Claim No.: __ of U.S. Patent 12,052,048
Claim No.: __ of application 18/742,280
1. Oscillator driver circuitry comprising:
a first buffer circuit configured to receive an oscillating signal;
a second buffer circuit configured to receive the oscillating signal from the first buffer circuit and configured to output the oscillating signal to a radio-frequency mixer;
a first bias adjustment circuit coupled to a first input terminal of the second buffer and configured to apply a first direct current (DC) offset voltage to the first input terminal of the second buffer; and
a second bias adjustment circuit coupled to a second input terminal of the second buffer and configured to apply a second direct current (DC) offset voltage to the second input terminal of the second buffer.
1. Oscillator driver circuitry comprising:
a first buffer circuit configured to receive an oscillating signal;
a second buffer circuit configured to receive the oscillating signal from the first buffer circuit; and
a first bias adjustment circuit coupled to a first input of the second buffer and configured to apply a first direct current (DC) offset voltage to the first input of the second buffer.
Claim 1 recites “a second bias adjustment circuit coupled to a second input terminal of the second buffer and configured to apply a second direct current (DC) offset voltage to the second input terminal of the second buffer”.
2. The oscillator driver circuitry of claim 1, further comprising: a second bias adjustment circuit coupled to a second input of the second buffer and configured to apply a second direct current (DC) offset voltage to the second input of the second buffer.
2. The oscillator driver circuitry of claim 1, wherein the first bias adjustment circuit comprises a first digital-to-analog converter (DAC) and wherein the second bias adjustment circuit comprises a second digital-to-analog converter (DAC).
3. The oscillator driver circuitry of claim 2, wherein the first bias adjustment circuit comprises a first digital-to-analog converter (DAC) and wherein the second bias adjustment circuit comprises a second digital-to-analog converter (DAC).
3. The oscillator driver circuitry of claim 2, wherein the second buffer circuit comprises: a first input transistor having a gate terminal coupled to the first input terminal and having a source-drain terminal coupled to a first output terminal of the second buffer circuit; and a second input transistor having a gate terminal coupled to the second input terminal and having a source-drain terminal coupled to a second output terminal of the second buffer circuit.
4. The oscillator driver circuitry of claim 3, wherein the second buffer circuit comprises: a first input transistor having a gate terminal coupled to the first input and having a source-drain terminal coupled to a first output of the second buffer circuit; and a second input transistor having a gate terminal coupled to the second input and having a source-drain terminal coupled to a second output of the second buffer circuit.
4. The oscillator driver circuitry of claim 3, wherein the second buffer circuit comprises a tail transistor having a first source-drain terminal coupled to the first and second input transistors, a second source-drain terminal coupled to a power supply line, and a gate terminal configured to receive a bias voltage.
5. The oscillator driver circuitry of claim 4, wherein the second buffer circuit further comprises a tail transistor having a first source-drain terminal coupled to the first and second input transistors, a second source-drain terminal coupled to a power supply line, and a gate terminal configured to receive a bias voltage.
5. The oscillator driver circuitry of claim 3, wherein the second buffer circuit comprises: a first capacitance neutralization transistor having a gate terminal coupled to the gate terminal of the first input transistor, a first source-drain terminal coupled to the second output terminal, and a second source-drain terminal coupled to a power supply terminal via a first resistor; and a second capacitance neutralization transistor having a gate terminal coupled to the gate terminal of the second input transistor, a first source-drain terminal coupled to the first output terminal, and a second source-drain terminal coupled to the power supply terminal via a second resistor.
6. The oscillator driver circuitry of claim 4, wherein the second buffer circuit comprises: a first capacitance neutralization transistor having a gate terminal coupled to the gate terminal of the first input transistor, a first source-drain terminal coupled to the second output, and a second source-drain terminal coupled to a power supply terminal via a first resistor; and a second capacitance neutralization transistor having a gate terminal coupled to the gate terminal of the second input transistor, a first source-drain terminal coupled to the first output, and a second source-drain terminal coupled to the power supply terminal via a second resistor.
6. The oscillator driver circuitry of claim 3, wherein the first digital-to-analog converter comprises: a first resistor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a power supply line; a second resistor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a first current source; and a first capacitor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to the first input terminal of the second buffer circuit.
7. The oscillator driver circuitry of claim 4, wherein the first digital-to-analog converter comprises: a first resistor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a power supply line; a second resistor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a first current source; and a first capacitor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to the first input of the second buffer circuit.
7. The oscillator driver circuitry of claim 6, wherein the second digital-to-analog converter comprises: a third resistor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to the power supply line; a fourth resistor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to a second current source; and a second capacitor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to the second input terminal of the second buffer circuit.
8. The oscillator driver circuitry of claim 7, wherein the second digital-to-analog converter comprises: a third resistor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to the power supply line; a fourth resistor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to a second current source; and a second capacitor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to the second input of the second buffer circuit.
8. The oscillator driver circuitry of claim 7, wherein the first, second, third, and fourth resistors comprise tunable resistances.
9. The oscillator driver circuitry of claim 8, wherein the first, second, third, and fourth resistors comprise tunable resistances.
11. The oscillator driver circuitry of claim 1, wherein the first DC offset voltage has a first magnitude and a first polarity and wherein the second DC offset voltage has a second magnitude equal to the first magnitude and a second polarity opposite the first polarity.
10. The oscillator driver circuitry of claim 2, wherein the first DC offset voltage has a first magnitude and a first polarity and wherein the second DC offset voltage has a second magnitude equal to the first magnitude and a second polarity opposite the first polarity.
9. The oscillator driver circuitry of claim 1, further comprising: a first transformer coupled at an input of the first buffer circuit; a second transformer coupled between the first and second buffer circuits; and a third transformer coupled at an output of the second buffer circuit.
11. The oscillator driver circuitry of claim 1, further comprising: a first transformer coupled at an input of the first buffer circuit; a second transformer coupled between the first and second buffer circuits; and a third transformer coupled at an output of the second buffer circuit.
10. The oscillator driver circuitry of claim 1, further comprising a third buffer circuit configured to receive the oscillating signal from the second buffer circuit and configured to output the oscillating signal to the radio- frequency mixer.
12. The oscillator driver circuitry of claim 1, further comprising: a third buffer circuit configured to receive the oscillating signal from the second buffer circuit and configured to output the oscillating signal to a radio-frequency mixer.
12. A buffer circuit comprising: a first input transistor having a gate terminal configured to receive an oscillating signal and having a source- drain terminal coupled to a first output terminal of the buffer circuit; a second input transistor having a gate terminal configured to receive the oscillating signal and having a source-drain terminal coupled to a second output terminal of the buffer circuit; a first biasing circuit coupled to the gate terminal of the first input transistor and configured to apply a first offset voltage on the gate terminal of the first input transistor; and a second biasing circuit coupled to the gate terminal of the second input transistor and configured to apply a second offset voltage on the gate terminal of the second input transistor.
13. A buffer circuit comprising: a first input transistor having a gate terminal configured to receive an oscillating signal and having a source-drain terminal coupled to a first output of the buffer circuit; a second input transistor having a gate terminal configured to receive the oscillating signal and having a source-drain terminal coupled to a second output of the buffer circuit; and a first biasing circuit coupled to the gate terminal of the first input transistor and configured to apply a first offset voltage on the gate terminal of the first input transistor.
Claim 12 recites “a second biasing circuit coupled to the gate terminal of the second input transistor and configured to apply a second offset voltage on the gate terminal of the second input transistor”.
14. The buffer circuit of claim 13, further comprising: a second biasing circuit coupled to the gate terminal of the second input transistor and configured to apply a second offset voltage on the gate terminal of the second input transistor.
13. The buffer circuit of The buffer circuit of claim 12, wherein the first offset voltage has a positive direct current (DC) value and wherein the second offset voltage has a negative direct current (DC) value.
15. The buffer circuit of claim 14, wherein the first offset voltage has a positive direct current (DC) value and wherein the second offset voltage has a negative direct current (DC) value.
14. The buffer circuit of claim 12, wherein the first biasing circuit and the second biasing circuit comprise digital-to-analog converters.
16. The buffer circuit of claim 14, wherein the first biasing circuit and the second biasing circuit comprise digital-to-analog converters.
15. The buffer circuit of claim 12, wherein the first biasing circuit comprises: a first tunable resistance having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a power supply line; a second tunable resistance having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a first current source; and a first capacitor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal configured to receive the oscillating signal.
17. The buffer circuit of claim 14, wherein the first biasing circuit comprises: a first tunable resistance having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a power supply line; and a second tunable resistance having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal coupled to a first current source.
Claim 15 recites “a first capacitor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal configured to receive the oscillating signal.”.
18. The buffer circuit of claim 14, wherein the first biasing circuit further comprises: a first capacitor having a first terminal coupled to the gate terminal of the first input transistor and having a second terminal configured to receive the oscillating signal.
16. The buffer circuit of claim 15, wherein the second biasing circuit comprises: a third tunable resistance having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to the power supply line; a fourth tunable resistance having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to a second current source; and a second capacitor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal configured to receive the oscillating signal.
19. The buffer circuit of claim 18, wherein the second biasing circuit comprises: a third tunable resistance having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to the power supply line; a fourth tunable resistance having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal coupled to a second current source; and a second capacitor having a first terminal coupled to the gate terminal of the second input transistor and having a second terminal configured to receive the oscillating signal.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 2, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zerbe et al. (US 8,198,930).
Regarding claim 1, Zerbe et al. (Fig. 8A) discloses an oscillator driver circuitry comprising: a first buffer circuit (a first buffer 810 of buffer chain 800) configured to receive an oscillating signal (input clock 806); a second buffer circuit (a second buffer 810 of the buffer chain 800) configured to receive the oscillating signal from the first buffer circuit; and a first bias adjustment circuit (Bias-generator circuit 804) coupled to a first input of the second buffer and configured to apply a first direct current (DC) offset voltage to the first input of the second buffer (“bias-generator circuit 804 is configured to convert the power supply voltage Vdd from power supply 802 into one or more bias voltages, and then use the one or more bias voltages to control the clock delay through buffer chain 800”; col. 8, lines 41-62; and Fig. 8B).
Regarding claim 2, Zerbe et al. (Fig. 8A) discloses the oscillator driver circuitry of claim 1, further comprising: a second bias adjustment circuit (804) coupled to a second input (V_biasP or V_biasN of buffer 810) of the second buffer and configured to apply a second direct current (DC) offset voltage to the second input of the second buffer (“bias-generator circuit 804 is configured to convert the power supply voltage Vdd from power supply 802 into one or more bias voltages, and then use the one or more bias voltages to control the clock delay through buffer chain 800”; col. 8, lines 41-62; and Fig. 8B).
Regarding claim 20, Zerbe et al. (Fig. 8A) discloses circuitry comprising: a chain of buffer circuits (buffer chain 810) configured to propagate an oscillating signal (input clock signal 806); and one or more biasing circuits (804) configured to apply an offset voltage to an input of at least one buffer circuit in the chain of buffer circuits (“bias-generator circuit 804 is configured to convert the power supply voltage Vdd from power supply 802 into one or more bias voltages, and then use the one or more bias voltages to control the clock delay through buffer chain 800”; col. 8, lines 41-62; and Fig. 8B).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845