DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thiery (US 2004/0227539 A1 hereinafter Thiery).
As to claim 1, Thiery discloses in Figs. 1-3, an electronic circuit for sensing a current through a pass Field-Effect Transistor (FET) (an electronic circuit for sensing the current through a power MOSFET 20 as shown in Fig. 1, equivalent to the claimed pass FET for current conduction, ¶ [0011]-[0012]), comprising:
a first sense circuit configured to pass a first sense current (I_Sens) should there be a difference between a supply voltage (drain voltage) and a source voltage (source voltage) of the pass FET that is small (a saturated region sensing circuit 10 as shown in Fig. 2, passing I_Sens through sense cell 20B when V_DS difference is small/≤ ~3-4 V, ¶ [0012]-[0014]);
a second sense circuit configured to pass a second sense current (I_DG) should the difference between the supply voltage (drain voltage) and the source voltage (source voltage) of the pass FET be large (a linear region sensing circuit 100 as shown in Fig. 3, passing I_1/I_2 mirrored and amplified as I_DG when V_DS difference is large/> ~3-4 V, ¶ [0015]-[0020]);
wherein the first sense circuit comprises a first switch that is configured to turn off when the difference between the supply voltage and the source voltage of the pass FET is large and turn on when the difference between the supply voltage and the source voltage of the pass FET is small (wherein the saturated region sensing circuit 10 comprises a P-channel MOSFET 24 as shown in Fig. 2, controlled by amplifier 22 to turn off in large V_DS/linear region and turn on in small V_DS/saturated region, ¶ [0013]-[0014], [0021]);
wherein the second sense circuit comprises a second switch that is configured to turn off when the difference between the supply voltage and the source voltage of the pass FET is small and turn on when the difference between the supply voltage and the source voltage of the pass FET is large (wherein the linear region sensing circuit 100 comprises a P-channel MOSFET 128 as shown in Fig. 3, controlled via amplifier 122 and current mirror to turn off in small V_DS/saturated region and turn on in large V_DS/linear region, ¶ [0017]-[0020], [0022]-[0023]); and
wherein the first sense current and the second sense current are representative of the current through the pass FET (wherein I_Sens and I_DG are proportionally scaled from I_Load/I_DS via sense cell 20B, converted to voltage across R_DG, ¶ [0011], [0013], [0019]-[0020], [0023]).
As to claim 10, Thiery discloses the electronic circuit according to claim 1 (as discussed above), wherein the pass FET is an NMOS pass FET (wherein the power MOSFET 20 is an N-channel MOSFET, as shown in Fig. 1 with source at ground potential and drain at higher supply, ¶ [0011]-[0012]).
As to claim 11, Thiery discloses an electronic device comprising an electronic circuit according to claim 1 (an electronic device comprising an electronic circuit for sensing current in power supplies or load switches, as shown in Fig. 1 with load connected, ¶ [0002], [0011], [0023]).As to claim 11, Thiery discloses an electronic device comprising an electronic circuit according to claim 1 (circuit integrated into electronic devices such as power supplies or load switches, as shown in Fig. 1 with load connected, ¶ [0002], [0011], [0023]).
Allowable Subject Matter
Claims 2-9, 12-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 2-9, 12-18, the prior art does not disclose wherein the first sense FET has a gate that is connected to the charge pump; and wherein the first sense amplifier has a positive input that is connected to the source voltage (Vout), and wherein the first sense amplifier has an output that is connected to a gate of the switch for switching the first switch and enabling the first sense current to flow when the first switch is switched on, as recited in the claims 2-5; 12-18; and wherein the second sense FET has a gate that is connected to the charge pump; and wherein the second sense amplifier has a negative input that is connected to the supply voltage (Vcc) via a further resistor, and wherein the second sense amplifier has an output that is connected to a gate of the second switch for switching the second switch and enabling the second sense current to flow when the second switch is on, as recited in the claims 6-9,
Conclusion
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 1/9/26