Prosecution Insights
Last updated: August 18, 2026
Application No. 18/742,634

Controlling Usage-Based Disturbance Mitigation

Non-Final OA §103
Filed
Jun 13, 2024
Priority
Aug 02, 2023 — provisional 63/517,293
Examiner
HO, HOAI V
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
3 (Non-Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1030 granted / 1112 resolved
+24.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
23 currently pending
Career history
1125
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
30.1%
-9.9% vs TC avg
§102
45.0%
+5.0% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1112 resolved cases

Office Action

§103
Response to Amendment 1. This office action is responsive to communication(s) filed on 7/13/2026. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 7/13/2026 has been entered. 2. Claims 1-18 and 24-27 are presented for examination. Claims 19-23 are withdrawn from further consideration. See a previous Office action dated 1/23/2026. Claim Rejections - 35 U.S.C. § 103 3. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. 4. Claims 1-4 and 24-25 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Oh US Pub. No. 20230326511 (previous cited) in view of Wang et al. UP Pub. No. 20210158853 (previous cited). As per claims 1-2 and 24-25, Fig. 1 and 3 of Oh are directed to an apparatus comprising: a memory device (200) comprising: at least one bank (bank 310, Fig. 3, par. 73) comprising multiple rows (Fig. 4) of memory cells, each row of the multiple rows configured to store an activation count within a subset of the memory cells (abstract); circuitry (Fig. 3) configured to perform an array counter update procedure to update the activation count corresponding to an activated row within the at least one bank (par. 72); and control circuitry (210), configured to: receive an external precharge command (by CMD) from a memory controller; and initiate precharging (IPRE, form 210) of the activated row after a time interval (tACU and tCCD_L_WR, Fig. 23, par. 228) has elapsed since the reception of the external precharge command, the time interval being sufficient to enable the array counter update procedure (read-update-write, par, 228, Fig. 23) to complete prior to initiating the precharging (IPRE, Fig. 23) the activated row. Oh fails to disclose receive an external precharge command from a memory controller; cause the circuitry to perform the array counter update procedure responsive to reception of the external precharge command. However, Fig. 3 and paragraphs 9 and 34 of Wang disclose receive an external precharge command (PRE, S42, par. 34) from a memory controller (113, par. 17); cause the circuitry to perform the array counter update procedure responsive to reception of the external precharge command. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Oh’s memory device which utilizes the extern precharge command before the array counter update as taught by Wang in order to precharge the memory bank as required (par. 34). Also see Fig. 5A or 5C of Wand for precharging all banks before the ACT issues. As per claim 3, Fig. 23 of Oh discloses wherein the control circuitry is configured to determine that the time interval has elapsed based on a clock signal (CK_t). As per claim 4, a paragraph of Oh discloses wherein the control circuitry is configured to determine that the time interval has elapsed based on a delay that is independent of a clock signal. Allowable Subject matter 5. Claims 5-18 and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 8. The following is a statement of reasons for the indication of allowable subject matter: Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants' disclosure, taken individually or in combination, does not teach or suggest the claimed invention having wherein the control circuitry comprises: at least one local bank control circuit coupled to the at least one bank; and a multi-bank control circuit coupled to the at least one local bank control circuit and configured to initiate the precharging of the activated row after the time interval has elapsed in claim 5; wherein the control circuitry comprises: a multi-bank control circuit configured to : receive the external precharge command from the memory controller; and generate an internal precharge command based on the external precharge command; and at least one local bank control circuit coupled to the multi-bank control circuit and the at least one local bank, the at least one local bank control circuit configured to initiate the precharging of the activated row after the time interval has elapsed since the receiving of the internal precharge command in claim 15; wherein: the initiating of the array counter update procedure comprises generating, by a multi-bank control circuit of the memory device, a flag that causes a local bank control circuit coupled to the bank to perform operations associated with the array counter update procedure; and the initiating of the precharging comprises determining, by the multi-bank control circuit, that the time interval has elapsed in claim 26; and wherein: the initiating of the array counter update procedure comprises receiving, by a local bank control circuit of the memory device that is coupled to the bank, an internal precharge command from a multi-bank control circuit of the memory device; and the initiating the precharging comprises determining, by the local bank control circuit, that the time interval has elapsed in claim 27. 7. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs. 8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)). 9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HOAI V HO/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Show 3 earlier events
Mar 03, 2026
Applicant Interview (Telephonic)
Mar 03, 2026
Examiner Interview Summary
Mar 06, 2026
Response Filed
Apr 27, 2026
Final Rejection mailed — §103
Jul 02, 2026
Response after Non-Final Action
Jul 13, 2026
Request for Continued Examination
Jul 17, 2026
Response after Non-Final Action
Jul 31, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12700436
COMPACT DATA LATCHES
2y 4m to grant Granted Aug 04, 2026
Patent 12700437
LOW POWER INTERMEDIATE PRE-CHARGE OPERATIONS IN MEMORY
2y 3m to grant Granted Aug 04, 2026
Patent 12694912
MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ
2y 2m to grant Granted Jul 28, 2026
Patent 12677412
MEMORY, STORAGE APPARATUS, AND ELECTRONIC DEVICE
2y 1m to grant Granted Jul 07, 2026
Patent 12676197
DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY
2y 0m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
98%
With Interview (+5.5%)
1y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1112 resolved cases by this examiner. Grant probability derived from career allowance rate.

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