Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim 1 recites the limitation “each contained in two separate storage memories of a microprocessor wherein an option register, read first during a resetting of the microprocessor, conditions the selection of one of the plurality of boot programs.” However, it is unclear what “each contained in two separate storage memories of a microprocessor” refers to. For the purpose of the examination, examiner interprets the limitation as each of the plurality of boot programs is contained in two separate storage memories of a microprocessor.
Furthermore, the claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors. The claim 1 recites the limitation “each contained in two separate storage memories of a microprocessor wherein an option register, read first during a resetting of the microprocessor, conditions the selection of one of the plurality of boot programs.” For the purpose of the examination, as discussed above, examiner interprets the limitation as each of the plurality of boot programs is contained in two separate storage memories of a microprocessor; wherein an option register is read first during a resetting of the microprocessor; the option register indicates a condition of the selection of one of the plurality of boot programs.
Regarding claim 17, the claim 17 is an apparatus claim the method claim 1. The claim 17 does not further teach or define the limitation over the limitations recited in the method claim 1. Therefore, the claim 17 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, as discussed above.
Regarding claim 2-16, the claims 2-16 inherit the deficiency of the claim 1, as discussed above. Therefore, the claims 2-16 are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, as discussed above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 13, 15-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHOI et al. (United States Patent Application Publication US 2019/0324761), hereinafter CHOI.
Regarding claim 1, CHOI teaches a method of a selection of a boot program of a plurality of boot programs, each contained in two separate storage memories of a microprocessor (([0046] “the SOC 2000 may store the first bootset BootSet_1 and the second bootset BootSet_2 respectively in the first region 2522 and the second region 2524 of the non-volatile memory 2520.” [0067] “the first region 522 and the second region 524 may be two different memory blocks.”) wherein an option register, read first during a resetting of the microprocessor, conditions the selection of one of the plurality of boot programs ([0050] “The booting controller 220 may perform bootloaders BLs or bootsets BSs by consecutively receiving instructions of boatloads BLs or bootsets BSs loaded in the working memory, in response to the bootloader request signal REQ_BL.” [0056] “by checking the indication parameter, the device may determine one of the first bootset BootSet_l stored in the first region of the non-volatile memory and the second bootset BootSet_2 stored in the second region of the non-volatile memory 520 as a current bootset, and use the current bootset in the following booting operations.” [0131] “flag information FI stored in the register in the booting device,” CHOI teaches a booting process to load bootsets based on flag information FI stored in the register.).
Regarding claim 2, CHOI teaches wherein a first boot program is contained in a user memory and a second boot program is contained in a system memory ([0067] “A first region 522 in which the first bootset BootSet_1 is stored and the second region 524 in which the second bootset BootSet_2 is stored may be physically separated regions in the non-volatile memory 520.”).
Regarding claim 3, CHOI teaches wherein at an initialization of a system comprising the microprocessor, when the option register has a first value, a first boot program is selected ([0034] “the indication parameter IP may be a parameter selectively indicating one of a first boot mode in which a booting operation is performed by using the first bootset BootSet_1, and a second boot mode in which a booting operation is performed by using the second bootset BootSet_2.” [0131] “flag information FI stored in the register in the booting device,” Based on the information in the register, the bootset is selected between BootSet_1 and BootSet_2.).
Regarding claim 4, CHOI teaches wherein at the initialization of the system, when the option register has a value other than the first value, a second boot program is selected ([0034] “the indication parameter IP may be a parameter selectively indicating one of a first boot mode in which a booting operation is performed by using the first bootset BootSet_l, and a second boot mode in which a booting operation is performed by using the second bootset BootSet_2.”).
Regarding claim 15, CHOI teaches wherein the option register is external to the microprocessor (FIG. 1 “1540 REGISTER” “1200 PROCESSOR (CPU)”).
Regarding claim 16, CHOI teaches wherein the option register is in a computer coupled to the microprocessor (FIG. 1 “1540 REGISTER” “1200 PROCESSOR (CPU)” “1100”).
Regarding claim(s) 17, the claim(s) 17 is the apparatus claims of the method claim(s) 17. CHOI further teaches a microprocessor comprising a system memory and a user memory (FIG. 2 “2800”). The claim(s) 17 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, CHOI teaches all the limitations of the claim(s) 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of Seok (United States Patent Application Publication US 2007/0083744), hereinafter Seok.
Regarding claim 9, CHOI teaches all the limitations of the method of claim 2, as discussed above.
However, CHOI does not explicitly teach wherein at least one application is executable from user memory after the selection of the first boot program.
Seok teaches wherein at least one application is executable from user memory after the selection of the first boot program ([0020] “The first memory 100 includes a boot loader sector 110 storing a boot loader, and an application program sector 120 storing an application program.” [0026] “The application program sector 120 stores diverse application programs required to operate the digital broadcast processing apparatus.” The first memory stores boot loader and application programs. Since the application programs is to operate the digital broadcast processing apparatus, the apparatus must be booted using the boot loader before executing the application programs.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHOI by incorporating the teaching of Seok of wherein at least one application is executable from user memory after the selection of the first boot program. They are all directed toward booting process. As well known in the art before the effective filing date of the claimed invention, the application programs can be stored in a memory device with other codes or data, which includes a boot loader. Furthermore, it is well known that the application programs to operate devices must be executed after being booted using the bootloader. Therefore, it is obvious to combine two well-known techniques to yield predictable results.
Regarding claim 14, CHOI in view of Seok teaches all the limitations of the method of claim 9, as discussed above.
Seok further teaches wherein a plurality of applications are executable from the user memory after use of the first boot program and wherein each of these applications is in a same security mode ([0026] “The application program sector 120 stores diverse application programs required to operate the digital broadcast processing apparatus.” [0030] “the boot loader code 15 is inserted into the application program and then downloaded to the application program sector 120, rather than writing the boot loader code 15 directly in the boot loader storage area 111 or 113.” Application programs are interpreted as a plurality of applications. Since the boot loader code is inserted into the application programs for the download, Seok suggests that the boot loader code and the application program are in a same security mode.).
Claim(s) 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of Wu et al. (United States Patent Application Publication US 2018/0189496), hereinafter Wu.
Regarding claim 10, CHOI teaches all the limitations of the method of claim 2, as discussed above.
However, CHOI does not explicitly teach wherein the first boot program, when it is selected, implements a configuration of the microprocessor so that it is in a secure mode where, when a non-secure transaction requires access to a secure resource of the microprocessor, then an error is returned.
Wu teaches wherein the first boot program, when it is selected, implements a configuration of the microprocessor so that it is in a secure mode where, when a non-secure transaction requires access to a secure resource of the microprocessor, then an error is returned ([0020] “If a fault-injection attack happens when the processor 212 is at branch point 270, the processor may read an SB bit value of 0 instead of 1, meaning that the processor selects the wrong branch, the non-secure branch 272-276. So a hacker could use a glitch attack to bypass the secure boot process defined by the bootrom code and could cause a malicious image to be loaded into the SoC without the image being authenticated.” [0024] “The SB circuitry 340 includes hardware that triggers the interrupt/reset circuitry 330 to interrupt the processor when the SB bit value is 1 in the SB register 245, which means that the processor is executing non-secure boot instructions in error.” Based on SB bit value, the secure boot process is executed. Then, access from a non-secure branch is not allowed, which is in error.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHOI by incorporating the teaching of Wu of wherein the first boot program, when it is selected, implements a configuration of the microprocessor so that it is in a secure mode where, when a non-secure transaction requires access to a secure resource of the microprocessor, then an error is returned. They are all directed toward booting process. As recognized by Wu, an attacker can cause a chip to boot in a wrong boot mode, which cause the chip to malfunction ([0003]). By disabling the access from different modes, the malicious access can be prevented, which enhance a security of the system. Therefore, it would be advantageous to incorporate the teaching of Wu of wherein the first boot program, when it is selected, implements a configuration of the microprocessor so that it is in a secure mode where, when a non-secure transaction requires access to a secure resource of the microprocessor, then an error is returned in order to improve the security.
Regarding claim 11, CHOI teaches all the limitations of the method of claim 2, as discussed above.
Wu further teaches wherein the first boot program, when it is selected, implements a configuration of the microprocessor so that it is in a secure mode where, when a secure transaction requires access to a non-secure resource of the microprocessor, then an error is returned ([0020] “If a fault-injection attack happens when the processor 212 is at branch point 270, the processor may read an SB bit value of 0 instead of 1, meaning that the processor selects the wrong branch, the non-secure branch 272-276. So a hacker could use a glitch attack to bypass the secure boot process defined by the bootrom code and could cause a malicious image to be loaded into the SoC without the image being authenticated.” [0024] “The SB circuitry 340 includes hardware that, when accessed by the processor executing boot instructions, does not trigger the interrupt/reset circuitry to generate an interrupt when the processor is not executing non-secure boot instructions in error (e.g., when the SB bit value is 0).”).
Allowable Subject Matter
Claims 5-8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
CHOI teaches selecting one of bootsets based on an indication. However, CHOI does not teach “wherein the first boot program, when it is selected, is configured to modify a value of a second register representative of a size of a forbidden access region of a system memory containing a second boot program so that the second boot program is not accessible.”
Wu teaches a secure boot circuity and an anti-fault injection controller to detect access from non-secure boot instructions in a secure boot operation. Wu further teaches not to allow the access. However, Wu does not teach “wherein the first boot program, when it is selected, is configured to modify a value of a second register representative of a size of a forbidden access region of a system memory containing a second boot program so that the second boot program is not accessible.”
Seok teaches a boot loader and application programs in a memory. However, Seok does not teach “wherein the first boot program, when it is selected, is configured to modify a value of a second register representative of a size of a forbidden access region of a system memory containing a second boot program so that the second boot program is not accessible.”
Galbi et al. (United States Patent Application Publication US 2023/0185658) teaches to configure cache line sizes for respective regions of memory with associated protection levels. However, Galbi does not teach “wherein the first boot program, when it is selected, is configured to modify a value of a second register representative of a size of a forbidden access region of a system memory containing a second boot program so that the second boot program is not accessible.”
LIN (United States Patent Application Publication US 2022/0253393) teaches to set register according to virtual memory address, size of predetermined memory, locked value and enabled value in the setting formation of the predetermined memory. However, LIN does not teach “wherein the first boot program, when it is selected, is configured to modify a value of a second register representative of a size of a forbidden access region of a system memory containing a second boot program so that the second boot program is not accessible.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SHIN (United States Patent Application Publication US 2025/0165054) teaches a system on chip including a ROM to store a first boot loader and SRAM to receive a second boot loader from a booting device.
Yu et al. (United States Patent Application Publication US 2007/0028084) teaches a self-booting Ethernet controller chip to determine fast boot, a legacy boot, or a ROM Boot.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HYUN SOO KIM whose telephone number is (571)270-1768. The examiner can normally be reached Monday - Friday 8:30 am - 5:30 pm.
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/HYUN SOO KIM/Examiner, Art Unit 2176