DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered. The amendment has overcome the rejection. However, upon further consideration, a new ground(s) of rejection is made.
Applicant's arguments with respect to claim 3 have been fully considered but they are not persuasive. The test for obviousness is not that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. Prior art Burns explicitly teaches the origin, the offsets, the scale factors, and the floating-point representation (see [0095] and [0103]) corresponding to the claimed “anchor position”, “offset”, “scale factor”, and “floating point number”, respectively. The combined teachings of the references would have suggested the process of summing the origin coordinate with the offset to obtain an intermediate value, converting the value into floating-point representation and applying the scale factor to obtain the final output, or at least render such process obvious, as this is a very common mathematical process.
Applicant’s arguments with respect to claim 4 have been fully considered and are persuasive. Claims 11 and 18 recite similar features of claim 4. Claims 5, 12 and 19 are dependent from claim 4, 11 or 18. Therefore, the rejections to claims 4, 5, 11, 12, 18 and 19 have been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “generating, by the ray tracing circuitry, low-precision vertex data based on the bounding box”, while parent claim 8 also recites “low-precision vertex data”. It’s unclear whether they are referring to the same data or not. Clarification is needed. Claim 12 is dependent from claim 11 and is therefore rejected.
As a side note, claim 4 and claim 18 properly recite “the low-precision vertex data”, and are therefore clear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-10, 13-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Burns (US 20220207690 A1, cited on IDS 12/4/2024), in view of MUTHLER (US 20240095995 A1) and KRIVOKUCA (US 20260113444 A1).
Regarding Claim 1, Burns discloses an apparatus comprising: circuitry configured to:
generate low-precision vertex data (Fig. 3, “Quantized triangle”) for the set of primitives ([0103] “The quantization may have generated reduced-precision representations of the primitive and ray. In some embodiments, the method includes quantizing the ray, the primitive, or both. In some embodiments, the reduced-precision representations are fixed-point representations and the first representation is a floating-point representation.”);
perform, using the low-precision vertex data, a first ray intersection test for a ray against each primitive in the set of primitives ([0102] “At 720, in the illustrated embodiment, ray intersection circuitry performs a reduced-precision intersection test.”); and
responsive to the first ray intersection test being inconclusive for one or more primitives of the set of primitives ([0111] “in response to a hit indicated by the initial intersection result…”):
generate high-precision vertex data for each of the one or more primitives (Fig. 3, “Object space triangle”.); and
perform a second ray intersection test for the ray against each of the one or more primitives using the high-precision vertex data ([0111] “At 750, in the illustrated embodiment, shader circuitry executes, in response to a hit indicated by the initial intersection result, a shader program to perform an intersection test using the first representation of the primitive to determine whether the ray intersects the primitive. For example, RIA 190 may dynamically form a SIMD group to perform an original-precision intersection test for a set of one or more rays that are indicated as hits by the reduced-precision intersection test.”).
Laine does not expressly disclose the first ray intersection test is performed simultaneously. Laine also fails to teach decode encoded primitive data representing a set of primitives, and further decode the encoded primitive data to generate high-precision vertex data for each of the one or more primitives.
However, in the same field of endeavor, MUTHLER discloses simultaneously perform a first ray intersection test for a ray against each primitive using the low-precision vertex data ([0134] “In example embodiments herein, a complet may define a plurality of “child” bounding volumes that (whether or not they represent leaf nodes) that don't necessarily each have descendants but which the TTU will test in parallel for ray-bounding volume intersection to determine whether geometric primitives associated with the plurality of bounding volumes need to be tested for intersection”).
KRIVOKUCA discloses decode encoded primitive data representing a set of primitives ([0004] “Aspects disclosed in the present disclosure describe methods for progressively encoding a mesh… Further aspects disclosed in the present disclosure describe methods for progressively decoding the mesh…”) and further decode the encoded primitive data to generate high-precision vertex data for each of the one or more primitives ([0081] “As mentioned above, the decoder can stop the decoding process at any point where the quality of the already reconstructed coefficient values is sufficient, the bitrate limit of the decoder has been reached, and/or some predefined number of dominant and refinement passes has been reached. Because the received bitstream is “embedded” (that is, upon decoding of bits from a new set of a dominant pass and a subordinate pass, the whole mesh surface is reconstructed at a certain level of detail or quality) the reconstruction of the mesh becomes progressively more accurate as more bits are decoded.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the apparatus of Burns with the feature of performing the reduced-precision intersection test simultaneously, and progressively decoding the encoded primitive data. Simultaneously performing the reduced-precision intersection test could improve the performance efficiency, as taught by MUTHLER. Progressively decoding the encoded primitive data could generate progressively more accurate vertex data for further processing purpose, as taught by
Regarding Claim 2, Burns-MUTHLER-KRIVOKUCA discloses the apparatus as claimed in claim 1, wherein the encoded primitive data comprises, for each primitive of the set of primitives: an anchor position (Burns [0095] “a common origin”) per coordinate of each vertex in a three-dimensional space; and an offset for each vertex relative to the anchor position (Burns [0095] “As discussed above, a set of quantized values (e.g., for multiple primitives) may share a “quantization frame” that defines parameters for the values. In some embodiments, quantized values are represented as fixed-point offsets relative to a common origin and scale factor.”).
Regarding Claim 3, Burns-MUTHLER-KRIVOKUCA discloses the apparatus as claimed in claim 2, wherein to generate the high-precision vertex data, the circuitry is configured to, for each vertex of each primitive of the one or more primitives: compute a sum of the offset and the anchor position (Burns [0097] “In some embodiments, the processor stores both quantized primitive data and original-precision primitive data in the same region of memory so that a single offset value encoded in a parent node of the BVH is sufficient to indicate all of the corresponding the primitive data.”); convert the sum to a floating point number (Burns [0103] “In some embodiments, the reduced-precision representations are fixed-point representations and the first representation is a floating-point representation.”); and apply a scale factor to the converted sum to generate a scaled sum that represents high-precision vertex data for a given vertex (Burns [0095] “As discussed above, a set of quantized values (e.g., for multiple primitives) may share a “quantization frame” that defines parameters for the values. In some embodiments, quantized values are represented as fixed-point offsets relative to a common origin and scale factor. Therefore, the quantization frame may specify the origin (e.g., in x, y, and z coordinates) and scale factors (e.g., as power-of-2 scale factors for each of the z, y, and z dimensions).”).
Regarding Claim 6, Burns-MUTHLER-KRIVOKUCA discloses the apparatus as claimed in claim 1, further comprising graphics processing circuitry configured to render an image based on one or more primitives from the set of primitives, identified by one of the first ray intersection test and the second ray intersection test as being intersected by the ray (Burns [0022] “Image write unit (IWU) 170, in some embodiments, is configured to store processed tiles of an image and may perform operations to a rendered image before it is transferred for display or to memory for storage.” MUTHLER [0019] “This basic ray tracing visibility test is the fundamental primitive underlying a variety of rendering algorithms and techniques in computer graphics. Generally, ray tracing is a rendering method in which rays are used to determine the visibility of various elements in the scene.”).
Regarding Claim 7, Burns-MUTHLER-KRIVOKUCA discloses the apparatus as claimed in claim 1, wherein the circuitry is configured to perform the second ray intersection test for the one or more primitives individually (Burns [0039] “In example embodiments discussed below, the low precision ray triangle intersector rejects triangles by performing low precision fixed-point edge tests. The endpoints of the ray are not considered, and a successful test indicates that a full precision test is needed.” [0111] “For example, RIA 190 may dynamically form a SIMD group to perform an original-precision intersection test for a set of one or more rays that are indicated as hits by the reduced-precision intersection test.”).
Regarding Claim 8, it recites similar limitations of claim 1. The rationale of claim 1 rejection is applied to reject claim 8.
Regarding Claim 9, it recites similar limitations of claim 2. The rationale of claim 2 rejection is applied to reject claim 9.
Regarding Claim 10, it recites similar limitations of claim 3. The rationale of claim 3 rejection is applied to reject claim 10.
Regarding Claim 13, it recites similar limitations of claim 6. The rationale of claim 6 rejection is applied to reject claim 13.
Regarding Claim 14, it recites similar limitations of claim 7. The rationale of claim 7 rejection is applied to reject claim 14.
Regarding Claim 15, it recites similar limitations of claim 1. The rationale of claim 1 rejection is applied to reject claim 15.
Regarding Claim 16, it recites similar limitations of claim 2. The rationale of claim 2 rejection is applied to reject claim 16.
Regarding Claim 17, it recites similar limitations of claim 3. The rationale of claim 3 rejection is applied to reject claim 17.
Regarding Claim 20, it recites similar limitations of claim 7. The rationale of claim 7 rejection is applied to reject claim 20.
Allowable Subject Matter
Claims 4, 5, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11 and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHONG WU whose telephone number is (571)270-5207. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Wu can be reached at 571-272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHONG WU/Primary Examiner, Art Unit 2613
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