Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20120193779 A1), in further view of Montgomery (US 20030193105 A1) and Yu (US 20180158749 A1).
Regarding independent claim 1, Lee teaches a semiconductor package ([0092], “Referring to FIG. 12, the semiconductor device 305 includes stacked semiconductor packages”), comprising: a substrate (Fig. 23, 200; [0129], “Referring to FIG. 22, second semiconductor chips 50 are placed on a carrier substrate 200…”); a first semiconductor chip on the substrate (Fig. 23, 50; [0129], “…second semiconductor chips 50 are placed on a carrier substrate 200…”); a second semiconductor chip on the first semiconductor chip (Fig. 23, 70; [0129], “…third semiconductor chips 70 are respectively flip-chip bonded onto the second semiconductor chips 50.”); a third semiconductor chip on the substrate and horizontally spaced apart from the first semiconductor chip (Fig. 23, 50, (There are two adjacent stacks of chips. While both bottom chips are here referred to as element 50, in the present application these are labeled as distinct)); a first molding layer disposed on the substrate and surrounding the first semiconductor chip and the third semiconductor chip, the first molding layer formed of a first molding material (Fig. 19, 28, 29; [0121], “…underfill portions 28 and molding portions 29 described above…”); wherein a top surface of the first semiconductor chip, a top surface of the third semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other (Fig. 19, 28, 29, 20; (These are all obviously coplanar according to the diagram)), wherein the second molding layer contacts the top surface of the third semiconductor chip (Fig. 11, 220, 21a; (While there is only one molding layer, it contacts the top, and a later source will teach a second molding layer)), wherein the first semiconductor chip comprises: a first integrated circuit adjacent to a bottom surface of the first semiconductor chip (Fig. 3, 111; [0050], “In one embodiment, the first surface 11a may be an active surface on which an integrated circuit 111 is placed…”); a first chip pad on the bottom surface of the first semiconductor chip (Fig. 3, 15; [0052], “The integrated circuit 111 may be connected to each of chip pads 15…”); and a first through-electrode vertically penetrating the first semiconductor chip so as to be connected to the first chip pad (Fig. 3, 15; [0052], “…may be connected to each of chip pads 15 and each of the through vias 12…”), wherein the second semiconductor chip comprises: a second integrated circuit adjacent to a bottom surface of the second semiconductor chip (Fig. 3, 111; [0050], “In one embodiment, the first surface 11a may be an active surface on which an integrated circuit 111 is placed…”; (In this document, all chips are substantially the same)); and a second chip pad on the bottom surface of the second semiconductor chip (Fig. 3, 15; [0052], “The integrated circuit 111 may be connected to each of chip pads 15…”; (In this document, all chips are substantially the same)). However, Lee does not teach and a second molding layer on the first molding layer and surrounding the second semiconductor chip, the second molding layer formed of a second molding material different from the first molding material, or wherein the first through-electrode and the second chip pad are bonded by hybrid bonding and constitute a single body formed of the same material at an interface of the first semiconductor chip and the second semiconductor chip.
However, in the same field of endeavor, Montgomery teaches a second molding layer on the first molding layer ([0038], “…to support electroplating of the second molding layer onto the first molding layer.”), the second molding layer formed of a second molding material different from the first molding material ([0044], “…and a second molding layer comprising a second material…), and Yu teaches wherein the first through-electrode and the second chip pad are bonded by hybrid bonding and constitute a single body formed of the same material at an interface (Fig. 17, 313, 333; [0064], “The bonding of the contact pad of 313 to the via 333 is representative of a via-to-pad or pad-to-via hybrid bonding.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of Lee with the second molding layer of Montgomery so as to have molding layers with different material properties, and the hybrid bonding of Yu, as it “has a benefit of not needing solder materials” (Yu, [0040]).
Regarding dependent claim 2, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1. However, as previously combined they do not teach wherein a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.
However, Montgomery further teaches wherein a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1 ([0014], “The substrate preferably has a coefficient of thermal expansion of about 4 to about 15 micrometer/(meter-.degree. C.) at 20.degree. C.”, [0040], “In one embodiment, the first molding layer has a coefficient of thermal expansion of about 4 to about 13 micrometers/(meter-.degree. C.) at 20.degree. C., [0048], “In one embodiment, the second molding layer has a coefficient of thermal expansion of about 4 to about 13 micrometers/(meter-.degree. C.) at 20.degree. C.”; (Within each of these ranges there are several values of the coefficient for each that can be set to achieve a ratio that is in the described range)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor package as described by the combination of Lee, Montgomery, and Yu with the ratio of thermal coefficients of Montgomery so as to “provide- rapid cycling between a higher temperature for filling the mold and a lower temperature for solidifying the article would be of great benefit.” (Montgomery, [0006]).
Regarding dependent claim 3, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 2. However, as previously combined, they do not teach wherein the first molding material is polyimide, and the second molding material is an epoxy molding compound with higher hardness than polyimide.
However, Montgomery further teaches wherein the first molding material is polyimide ([0055], “Another embodiment of the invention is polymer composition molding method…”, [0056], “These may comprise, for example…polyetherimide…”), and the second molding material is an epoxy molding compound with higher hardness than polyimide ([0056], “…epoxy thermoset resins…”, [0044], “In some instances, it may be desirable to have a first molding layer comprising a first material that facilitates construction (e.g., by machining) of the molded article contours, and a second molding layer comprising a second material that is hard and polishable to a very smooth surface (e.g., a so-called Class A surface).”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor package as described by the combination of Lee, Montgomery, and Yu with the materials of Montgomery so as to make a mold “of higher quality” (Montgomery, [0061]).
Regarding dependent claim 4, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches wherein the first semiconductor chip is vertically between the second semiconductor chip and the substrate (Fig. 23, 50, 70, 200; (This is obvious from looking at the diagram – the first chip 50 is between the second chip 70 and the substrate 200.)), and Montgomery further teaches wherein the first molding layer is vertically between the second molding layer and the substrate ([0010], “…wherein the first insulating layer is interposed between the substrate and the heating element, and the second insulating layer is interposed between the heating element and the first molding layer, and, optionally, a second molding layer, which, if present, the first molding layer is interdisposed between the second insulating layer and the second molding layer.”).
Regarding dependent claim 5, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches (with support from Montgomery), wherein the first molding layer is adjacent to the substrate and is adjacent to opposite sidewalls of the first semiconductor chip and opposite sidewalls of the third semiconductor chip (Fig. 11, 220, 21a; [0156], “The overmold 220 may then be formed to surround semiconductor device 300.”), and wherein the second molding layer is adjacent to opposite sidewalls of the second semiconductor chip (Fig. 11, 220, 21a; [0156], “The overmold 220 may then be formed to surround semiconductor device 300.”; (In this, there is just one molding layer around all of the chips, however, when combined with Montgomery, this molding layer can be split into two layers)).
Regarding dependent claim 6, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches wherein the second molding layer covers a top surface of the second semiconductor chip (Fig. 34, 220, 30; (Once again there is only one layer in this source, but since it has been combined with Montgomery, it can be assumed that the molding layer is split into two layers now)).
Regarding dependent claim 7, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches wherein the first semiconductor chip further comprises a first conductive pattern connecting the first chip pad to the first integrated circuit (Fig. 3, 112; [0052], “The integrated circuit 111 may be connected to each of chip pads 15 and each of the through vias 12 by a conductive material pattern such as internal wiring pattern 112.”), and wherein the third semiconductor chip further comprises a second conductive pattern connecting the second chip pad to the second integrated circuit (Fig. 3, 112; [0052], “The integrated circuit 111 may be connected to each of chip pads 15 and each of the through vias 12 by a conductive material pattern such as internal wiring pattern 112.”; (Every chip in this source is substantially identical)).
Regarding dependent claim 8, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches wherein the third semiconductor chip comprises: a third integrated circuit adjacent to a bottom surface of the first semiconductor chip (Fig. 3, 111; [0050], “In one embodiment, the first surface 11a may be an active surface on which an integrated circuit 111 is placed…”; (In this document, all chips are substantially the same); and a third chip pad on the bottom surface of the first semiconductor chip (Fig. 3, 15; [0052], “The integrated circuit 111 may be connected to each of chip pads 15…”; (In this document, all chips are substantially the same)).
Regarding dependent claim 9, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 8, and further teaches wherein the substrate comprises: a first substrate pad and a second substrate pad disposed at a top surface of the substrate (Fig. 9, 101; [0083], “The package substrate 100 may include bonding pads 101…”), wherein the first substrate pad contacts the bottom surface of the first semiconductor chip (Fig. 9, 101, 20); and wherein the second substrate pad contacts the bottom surface of the third semiconductor chip (Fig. 9, 101, 20; (All chips are substantially the same)). However, as previously combined, they do not teach and the first substrate pad and the first chip pad of the first semiconductor chip are formed of the same material and constitute a single body, and the second substrate pad and the third chip pad of the third semiconductor chip are formed of the same material and constitute a single body.
However, Yu further teaches the first substrate pad and the first chip pad of the first semiconductor chip are formed of the same material and constitute a single body, and the second substrate pad and the third chip pad of the third semiconductor chip are formed of the same material and constitute a single body (Fig. 17, 313, 332; [0064], “The bonding of the contact pad of 312 to the contact pad of 332 is representative of a pad-to-pad hybrid bonding.”; (Since this applies to any pad, it can apply to both pads in the device)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Lee, Montgomery, and Yu with the single-body bonded pads of Yu as it “has a benefit of not needing solder materials” (Yu, [0040]).
Regarding dependent claim 10, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches wherein the third semiconductor chip is disposed at the same vertical level as the first semiconductor chip (Fig. 23, 50; (Both chips 50 correspond to the first and third chips of the present application)).
Regarding dependent claim 11, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches wherein the third semiconductor chip is a logic chip, and wherein the first and second semiconductor chips are memory chips ([0097], “…the first semiconductor chip 10 may be a logic chip such as a mobile CPU, and the second and third semiconductor chips 50 and 60 may be memory chips…”).
Regarding dependent claim 12, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 1, and further teaches further comprising: a fourth semiconductor chip on the third semiconductor chip (Fig. 23, 70; (Both chips 70 correspond to the second and fourth chips in the present application)), wherein the first molding layer is disposed on the substrate horizontally between the first semiconductor chip and the third semiconductor chip (Fig. 32, 161), and Montgomery further teaches and wherein the second molding layer is adjacent to the first molding layer ([0010], “…the first molding layer is interdisposed between the second insulating layer and the second molding layer.”).
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20120193779 A1), in further view of Montgomery (US 20030193105 A1), Yu (US 20180158749 A1), and Choi (US 20150091168 A1).
Regarding dependent claim 13, Lee, as previously modified by Montgomery and Yu, teaches the semiconductor package of claim 12. Montgomery further teaches a contact surface where the first and second molding layers meet are flat and are coplanar with respect to each other ([0038], “…the first molding layer has an electrical conductivity sufficient to support electroplating of the second molding layer onto the first molding layer.”). However, as previously combined, they do not teach wherein a contact surface where the first and second semiconductor chips meet, a contact surface where the third and fourth semiconductor chips meet are flat and are coplanar with respect to each other.
However, in the same field of endeavor, Choi teaches wherein a contact surface where the first and second semiconductor chips meet, a contact surface where the third and fourth semiconductor chips meet are flat and are coplanar with respect to each other (Fig. 1, 140, 150; [0050], “Therefore, the first semiconductor chip 140 may have a side surface substantially coplanar with the side surface of the second semiconductor chip 150.”; (Only two chips are given, but this can be applied to both pairs of chips in the application)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor package as described by the combination of Lee, Montgomery, and Yu with the contacted semiconductors of Choi “In order to increase storage capacity of the semiconductor package” (Choi, [0006]).
Regarding independent claim 14, Lee teaches a semiconductor package comprising: a substrate (Fig. 23, 200; [0129], “Referring to FIG. 22, second semiconductor chips 50 are placed on a carrier substrate 200…”); a first semiconductor chip mounted on the substrate at a first vertical level (Fig. 23, 50; [0129], “…second semiconductor chips 50 are placed on a carrier substrate 200…”); a second semiconductor chip mounted on the first semiconductor chip at a second vertical level (Fig. 23, 70; [0129], “…third semiconductor chips 70 are respectively flip-chip bonded onto the second semiconductor chips 50.”), the first semiconductor chip being disposed between the substrate and the second semiconductor chip (Fig. 23, 70; [0129], “…third semiconductor chips 70 are respectively flip-chip bonded onto the second semiconductor chips 50.”); a third semiconductor chip mounted on the substrate at the first vertical level and horizontally spaced apart from the first semiconductor chip (Fig. 23, 50, (There are two adjacent stacks of chips. While both bottom chips are here referred to as element 50, in the present application these are labeled as distinct)); a first molding layer surrounding the first semiconductor chip and the third semiconductor chip on the substrate (Fig. 19, 28, 29; [0121], “…underfill portions 28 and molding portions 29 described above…”); (and a second molding layer) covering a top surface of the third semiconductor chip (Fig. 32, 161, 151; (While there is only one molding layer, it covers the third chip, and a later source will teach a second molding layer)), , and wherein an active surface of the first semiconductor chip, an active surface of the second semiconductor chip, and an active surface of the third semiconductor chip face the substrate (). However, Lee does not teach wherein the first and second semiconductor chips contact each other at a first planar interface, and a second molding layer surrounding the second semiconductor chip on the first molding layer, wherein a hardness of the first molding layer and a hardness of the second molding layer are different from each other.
However, in the same field of endeavor, Montgomery teaches a second molding layer on the first molding layer ([0038], “…the first molding layer has an electrical conductivity sufficient to support electroplating of the second molding layer onto the first molding layer.”), wherein a hardness of the first molding layer and a hardness of the second molding layer are different from each other ([0037], “In one embodiment, the first molding layer has a Rockwell hardness of at least about 10, preferably at least about 30, more preferably at least about 40.”, [0045], “The second molding layer may have a Rockwell hardness of at least about 30, preferably at least about 40, more preferably at least about 50.”), and Choi teaches wherein the first and second semiconductor chips contact each other at a first planar interface (Fig. 1, 140, 150; [0050], “Therefore, the first semiconductor chip 140 may have a side surface substantially coplanar with the side surface of the second semiconductor chip 150.”; (Only two chips are given, but this can be applied to both pairs of chips in the application)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of Lee with the second molding layer of Montgomery so as to have molding layers with different material properties, and to combine it with the contact of Choi “In order to increase storage capacity of the semiconductor package” (Choi, [0006]).
Regarding dependent claim 15, Lee, as previously modified by Montgomery and Choi, teaches the semiconductor package of claim 14. Montgomery further teaches wherein the first and second molding layers contact each other at a second planar interface, and the first planar interface is on the same plane as the second planar interface ([0054], “The optional second molding layer 90 is disposed on the opposite face of the first molding layer 80.”).
Regarding dependent claim 16, Lee, as previously modified by Montgomery and Choi, teaches the semiconductor package of claim 14. Montgomery further teaches wherein the hardness of the second molding layer is higher than the hardness of the first molding layer ([0037], “In one embodiment, the first molding layer has a Rockwell hardness of at least about 10, preferably at least about 30, more preferably at least about 40.”, [0045], “The second molding layer may have a Rockwell hardness of at least about 30, preferably at least about 40, more preferably at least about 50.”).
Regarding dependent claim 17, Lee, as previously modified by Montgomery and Choi, teaches the semiconductor package of claim 14. However, as previously combined, they do not teach wherein the first molding layer is formed of a first molding material, and the second molding layer is formed of a second molding material different from the first molding material.
However, Montgomery further teaches wherein the first molding layer is formed of a first molding material, and the second molding layer is formed of a second molding material different from the first molding material ([0044], “…and a second molding layer comprising a second material…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Lee, Montgomery, and Choi with the second molding layer of Montgomery so as to have molding layers with different material properties.
Regarding dependent claim 18, Lee, as previously modified by Montgomery and Choi, teaches the semiconductor package of claim 14, and further teaches wherein the first semiconductor chip comprises: a first integrated circuit adjacent to the active surface of the first semiconductor chip (Fig. 3, 111; [0050], “In one embodiment, the first surface 11a may be an active surface on which an integrated circuit 111 is placed…”); a first chip pad on the active surface of the first semiconductor chip (Fig. 3, 15; [0052], “The integrated circuit 111 may be connected to each of chip pads 15…”); and a first through-electrode vertically penetrating the first semiconductor chip so as to be connected to the first chip pad (Fig. 3, 15; [0052], “…may be connected to each of chip pads 15 and each of the through vias 12…”), wherein the second semiconductor chip comprises: a second integrated circuit adjacent to the active surface of the second semiconductor chip (Fig. 3, 111; [0050], “In one embodiment, the first surface 11a may be an active surface on which an integrated circuit 111 is placed…”; (In this document, all chips are substantially the same)); and a second chip pad on the active surface of the second semiconductor chip (Fig. 3, 15; [0052], “The integrated circuit 111 may be connected to each of chip pads 15…”; (In this document, all chips are substantially the same)). However, as previously combined, they do not teach and wherein the first through-electrode and the second chip pad are bonded by hybrid bonding and constitute a single body formed of the same material the first planar interface of the first semiconductor chip and the second semiconductor chip.
However, in the same field of endeavor, Yu teaches and wherein the first through-electrode and the second chip pad are bonded by hybrid bonding and constitute a single body formed of the same material the first planar interface of the first semiconductor chip and the second semiconductor chip (Fig. 17, 313, 333; [0064], “The bonding of the contact pad of 313 to the via 333 is representative of a via-to-pad or pad-to-via hybrid bonding.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package as described by the combination of Lee, Montgomery, and Choi with the hybrid bonding of Yu, as it “has a benefit of not needing solder materials” (Yu, [0040]).
Regarding dependent claim 19, Lee, as previously modified by Montgomery, Choi, and Yu, teaches the semiconductor package of claim 14. However, as previously combined, they do not teach wherein a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.
However, Montgomery further teaches wherein a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1 ([0014], “The substrate preferably has a coefficient of thermal expansion of about 4 to about 15 micrometer/(meter-.degree. C.) at 20.degree. C.”, [0040], “In one embodiment, the first molding layer has a coefficient of thermal expansion of about 4 to about 13 micrometers/(meter-.degree. C.) at 20.degree. C., [0048], “In one embodiment, the second molding layer has a coefficient of thermal expansion of about 4 to about 13 micrometers/(meter-.degree. C.) at 20.degree. C.”; (Within each of these ranges there are several values of the coefficient for each that can be set to achieve a ratio that is in the described range)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor package as described by the combination of Lee, Montgomery, Choi, and Yu with the ratio of thermal coefficients of Montgomery so as to “provide- rapid cycling between a higher temperature for filling the mold and a lower temperature for solidifying the article would be of great benefit.” (Montgomery, [0006]).
Regarding dependent claim 20, Lee, as previously modified by Montgomery, Choi, and Yu, teaches the semiconductor package of claim 14, and further teaches wherein the second molding layer contacts the top surface of the third semiconductor chip (Fig. 11, 220, 21a; (While there is only one molding layer, it contacts the top, and a later source will teach a second molding layer)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20110147911 A1, pertaining to a semiconductor package made of stacked semiconductors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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