DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
This Office Action is FINAL.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/26/2025, 12/04/2025, 12/12/2025, 04/29/2026, 06/02/2026, 07/22/2026, and 09/23/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2, 10, 16 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claims 2, 10, 16 do not further limit the subject matter of Claims 1, 9, 15, respectively, as described below:
Claim 1, last limitation: “storing the first user data, the first parity data, the second user data, and the second parity data in a same memory block of the memory device.”
Claim 2: “The method of claim 1, wherein the second user data and the second parity data are stored in a same memory block as the first user data and the first parity data.”
Claim 9, last limitation: “storing the first user data, the first parity data, the second user data: and the second parity data in a same memory block.”
Claim 10: “The memory system of claim 9, wherein the second user data and the second parity data are stored in a same memory block as the first user data and the second parity data.”
Claim 15, first and last limitations: “A memory controller comprising: at least one processor; a memory coupled to the at least one processor and storing instructions for execution by the at least one processor to… cause the first user data, the first parity data, the second user data, and the second parity data to be stored in a same memory block of the memory device.”
Claim 16: “The memory controller of claim 15, wherein the memory controller is configured to control the memory device to store the second user data and the second parity data in a same memory block as the first user data and the first parity data.”
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10, 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over D'ABREU et al. (US 20150324251 A1, hereinafter “D’Abreu”) in view of HSU (US 20200401508 A1) and NVM Express (NPL: “NVM Express Base Specification 1.4”), hereinafter “Hsu-NVMe”*.
*Note: Hsu relies on Non-Volatile Memory Express (NVMe) 1.4 in [0004] and is considered as part of the original disclosure.
Regarding Claim 1, D’Abreu discloses a method of operating a memory system, comprising:
receiving a first write command to store first user data in a memory device of the memory system (D’Abreu: Paragraph [0116], “The method 1200 may include receiving a first request for write access from a host device to write first data to a memory having a three-dimensional memory configuration and including multiple layers formed upon a substrate, at 1204”);
generating, based on a first encoding algorithm, first parity data corresponding to the first user data (D’Abreu: Paragraph [0038], “For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique. In an illustrative embodiment, the first encoding technique is associated with a lower complexity and/or a higher code rate than the second encoding technique”)
receiving a second write command to store second user data in the memory device (D’Abreu: Paragraph [0122], “The method 1200 may further include receiving a second request for write access from the host device to write second data to the memory, at 1228. The second data may correspond to the data 112”);
generating, based on a second encoding algorithm, second parity data corresponding to the second user data, wherein the second encoding algorithm is different from the first encoding algorithm (D’Abreu: Paragraph [0038], “For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique. In an illustrative embodiment, the first encoding technique is associated with a lower complexity and/or a higher code rate than the second encoding technique”); and
storing the first user data, the first parity data, the second user data, and the second parity data in a same memory block of the memory device (D’Abreu: Paragraph [0043], “The ECC codeword 120 may include data 122 (e.g., the first data), ECC bits 124, and a portion 126. The ECC codeword 110 may include data 112 (e.g., the second data) and ECC bits 114. The ECC codeword 120 may be stored at the physical page 118, and the ECC codeword 110 may be stored at the physical page 108. The ECC bits 114, 124 may include parity bits to enable the ECC engine 132 to correct one or more bit errors in the data 112, 122”; wherein memory block is being interpreted broadly and as seen in fig. 1).
D’Abreu does not disclose:
first user data of a first logical block address (LBA) format;
second user data of a second LBA format
However, Hsu-NVMe teaches:
first user data of a first logical block address (LBA) format (Hsu: [0029]: SSD controller 130 [can] create more than one namespace, for example, two namespaces, each namespace has independent LBA range to store individual user data and the namespaces use different LBA formats to manage their user data)
second user data of a second LBA format (Hsu: [0029]: regarding [a second] individual user data in the second namespace)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine D’Abreu and Hsu-NVMe by implementing the LBA format taught by Hsu-NVMe. One of ordinary skill in the art would be motivated to make this modification in order to allow the host to define different lengths of user data and metadata (Hsu: [0029]).
Regarding Claim 2, D’Abreu in view of Hsu-NVMe teaches the method of claim 1, as referenced above, wherein the second user data and the second parity data are stored in a same memory block as the first user data and the first parity data (D’Abreu: Fig. 1, #104; and Paragraph [0043], “The ECC codeword 120 may include data 122 (e.g., the first data), ECC bits 124, and a portion 126. The ECC codeword 110 may include data 112 (e.g., the second data) and ECC bits 114. The ECC codeword 120 may be stored at the physical page 118, and the ECC codeword 110 may be stored at the physical page 108. The ECC bits 114, 124 may include parity bits to enable the ECC engine 132 to correct one or more bit errors in the data 112, 122”; wherein memory block is being interpreted broadly and as seen in fig. 1).
Regarding Claim 8, D’Abreu in view of Hsu-NVMe teaches the method of claim 1, as referenced above, wherein the first user data are comprised in logical blocks in a first format, and the second user data are comprised in logical blocks in a second format (Hsu: [0004]; [0029]: SSD controller 130 [can] create more than one namespace, for example, two namespaces, each namespace has independent LBA range to store individual user data and the namespaces use different LBA formats to manage their user data. NVMe: Page 246, Section 6.1.1: a namespace is a collection of logical blocks whose logical block addresses range from 0 to the size of the namespace – 1. A first namespace (defined as a collection of logical blocks) for storing first individual user data contains LBAs in a first format. A second namespace for storing second individual user data contains LBAs in a different second format).
Regarding Claim 9, the method of Claim 1 performs the same steps as the system of Claim 9, and Claim 9 is rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of D’Abreu in view of Hsu-NVMe.
D’Abreu further discloses a memory system comprising:
one or more memory devices (D’Abreu: Paragraph [0194], “the data storage device 102 may be implemented using a microprocessor or microcontroller programmed (e.g., by executing instructions) to perform operations described herein, such as one or more operations of the methods 700-1500. In a particular embodiment, the data storage device 102 includes a processor executing instructions (e.g., firmware) retrieved from the memory 104”); and
a memory controller coupled to the one or more memory devices, wherein the memory system is configured to perform operations (D’Abreu: Paragraph [0194], “the data storage device 102 may be implemented using a microprocessor or microcontroller programmed (e.g., by executing instructions) to perform operations described herein, such as one or more operations of the methods 700-1500. In a particular embodiment, the data storage device 102 includes a processor executing instructions (e.g., firmware) retrieved from the memory 104”)
Regarding Claim 10, D’Abreu in view of Hsu-NVMe teaches the system of Claim 9 above. The method of Claim 2 performs the same steps as the system of Claim 10, and Claim 10 is rejected using the same art and rationale set forth above in the rejection of Claim 2 by the teachings of D’Abreu in view of Hsu-NVMe.
Regarding Claim 12, D’Abreu in view of Hsu-NVMe teaches the memory system of claim 9, as referenced above, wherein the operations further comprise:
storing a first identifier of the first user data in the memory controller, wherein the first identifier corresponds to the first encoding algorithm (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use); and
storing a second identifier of the second user data in the memory controller, wherein the second identifier corresponds to the second encoding algorithm (see above).
Regarding Claim 13, D’Abreu in view of Hsu-NVMe teaches the memory system of claim 12, as referenced above, wherein the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table, and wherein logical addresses of the first user data are mapped to the first identifier in the P2L mapping table, and logical addresses of the second user data are mapped to the second identifier in the P2L mapping table (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use).
Regarding Claim 14, D’Abreu in view of Hsu-NVMe teaches the system of Claim 9 above. The method of Claim 8 performs the same steps as the system of Claim 14, and Claim 14 is rejected using the same art and rationale set forth above in the rejection of Claim 8 by the teachings of D’Abreu in view of Hsu-NVMe.
Regarding Claim 15, D’Abreu discloses a memory controller (D’Abreu: Paragraph [0194], “the data storage device 102 may be implemented using a microprocessor or microcontroller programmed (e.g., by executing instructions) to perform operations described herein, such as one or more operations of the methods 700-1500. In a particular embodiment, the data storage device 102 includes a processor executing instructions (e.g., firmware) retrieved from the memory 104”) comprising:
at least one processor (D’Abreu: [0194]);
a memory coupled to the at least one processor and storing instructions for execution by the at least one processor to (D’Abreu: [0194]):
cause a first interface to:
receive a first write command comprising first user data (D’Abreu: Paragraph [0116], “The method 1200 may include receiving a first request for write access from a host device to write first data to a memory having a three-dimensional memory configuration and including multiple layers formed upon a substrate, at 1204”); and
receive a second write command comprising second user data (D’Abreu: Paragraph [0122], “The method 1200 may further include receiving a second request for write access from the host device to write second data to the memory, at 1228. The second data may correspond to the data 112”);
cause an encoder implemented in the at least one processor to:
generate first parity data corresponding to the first user data based on a first encoding algorithm (D’Abreu: Paragraph [0038], “For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique. In an illustrative embodiment, the first encoding technique is associated with a lower complexity and/or a higher code rate than the second encoding technique”); and
generate second parity data corresponding to the second user data based on a second encoding algorithm, wherein the second encoding algorithm is different from the first encoding algorithm (D’Abreu: Paragraph [0038], “For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique. In an illustrative embodiment, the first encoding technique is associated with a lower complexity and/or a higher code rate than the second encoding technique”); and
cause a second interface configured to:
send a third write command to write the first user data and the first parity data in a memory block of a memory device (D’Abreu: Paragraph [0043], “The ECC codeword 120 may include data 122 (e.g., the first data), ECC bits 124, and a portion 126. The ECC codeword 110 may include data 112 (e.g., the second data) and ECC bits 114. The ECC codeword 120 may be stored at the physical page 118, and the ECC codeword 110 may be stored at the physical page 108. The ECC bits 114, 124 may include parity bits to enable the ECC engine 132 to correct one or more bit errors in the data 112, 122”); and
send a fourth write command to write the second user data and the second parity data in the memory block (D’Abreu: Paragraph [0043], “The ECC codeword 120 may include data 122 (e.g., the first data), ECC bits 124, and a portion 126. The ECC codeword 110 may include data 112 (e.g., the second data) and ECC bits 114. The ECC codeword 120 may be stored at the physical page 118, and the ECC codeword 110 may be stored at the physical page 108. The ECC bits 114, 124 may include parity bits to enable the ECC engine 132 to correct one or more bit errors in the data 112, 122”); and
cause the first user data, the first parity data, the second user data, and the second parity data to be stored in a same memory block of the memory device (D’Abreu: Paragraph [0043], “The ECC codeword 120 may include data 122 (e.g., the first data), ECC bits 124, and a portion 126. The ECC codeword 110 may include data 112 (e.g., the second data) and ECC bits 114. The ECC codeword 120 may be stored at the physical page 118, and the ECC codeword 110 may be stored at the physical page 108. The ECC bits 114, 124 may include parity bits to enable the ECC engine 132 to correct one or more bit errors in the data 112, 122”; wherein memory block is being interpreted broadly and as seen in fig. 1).
D’Abreu does not disclose:
first user data of a first logical block address (LBA) format;
second user data of a second LBA format
However, Hsu-NVMe teaches:
first user data of a first logical block address (LBA) format (Hsu: [0029]: SSD controller 130 [can] create more than one namespace, for example, two namespaces, each namespace has independent LBA range to store individual user data and the namespaces use different LBA formats to manage their user data)
second user data of a second LBA format (Hsu: [0029]: regarding [a second] individual user data in the second namespace).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine D’Abreu and Hsu-NVMe by implementing the LBA format taught by Hsu-NVMe. One of ordinary skill in the art would be motivated to make this modification in order to allow the host to define different lengths of user data and metadata (Hsu: [0029]).
Regarding Claim 16, D’Abreu in view of Hsu-NVMe teaches the memory controller of claim 15, as referenced above, wherein the memory controller is configured to control the memory device to store the second user data and the second parity data in a same memory block as the first user data and the first parity data (D’Abreu: Fig. 1, #104; and Paragraph [0043], “The ECC codeword 120 may include data 122 (e.g., the first data), ECC bits 124, and a portion 126. The ECC codeword 110 may include data 112 (e.g., the second data) and ECC bits 114. The ECC codeword 120 may be stored at the physical page 118, and the ECC codeword 110 may be stored at the physical page 108. The ECC bits 114, 124 may include parity bits to enable the ECC engine 132 to correct one or more bit errors in the data 112, 122”; wherein memory block is being interpreted broadly and as seen in fig. 1).
Regarding Claim 17, D’Abreu in view of Hsu-NVMe teaches the memory controller of claim 15, as referenced above, wherein the second interface is further configured to:
receive the first user data and the first parity data from the memory block (D’Abreu: Paragraph [0046], “the data storage device 102 may be configured to sense data using the memory access parameter table 154, such as in response to receiving one or more requests for read access from the host device 172 for data stored at the memory 104. To further illustrate, the controller 130 may receive a first request for read access to the memory 104 from the host device 172. The first request may indicate that the data 122 is to be accessed from the memory 104. The first request may indicate a first logical address associated with the data 122. After receiving the first request from the host device 172, the controller 130 may receive a second request for read access to the memory 104 from the host device 172. The second request may indicate that the data 112 is to be accessed from the memory 104. The second request may indicate a second logical address associated with the data 112”); and
receive the second user data and the second parity data from the memory block (D’Abreu: Paragraph [0046], “the data storage device 102 may be configured to sense data using the memory access parameter table 154, such as in response to receiving one or more requests for read access from the host device 172 for data stored at the memory 104. To further illustrate, the controller 130 may receive a first request for read access to the memory 104 from the host device 172. The first request may indicate that the data 122 is to be accessed from the memory 104. The first request may indicate a first logical address associated with the data 122. After receiving the first request from the host device 172, the controller 130 may receive a second request for read access to the memory 104 from the host device 172. The second request may indicate that the data 112 is to be accessed from the memory 104. The second request may indicate a second logical address associated with the data 112”);
wherein the memory controller further comprises a decoder configured to:
decode the first parity data based on the first encoding algorithm (D’Abreu: Paragraph [0049], “The controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to decode the data 112, 122. For example, the controller 130 may access the parameter 150 to determine that the ECC codeword 120 is encoded using a first encoding technique and/or that the ECC codeword 120 is to be decoded using a first decoding technique that corresponds to the first encoding technique. As another example, the controller 130 may access the parameter 152 to determine that the ECC codeword 110 is encoded using a second encoding technique and/or that the ECC codeword 110 is to be decoded using a second decoding technique that corresponds to the second encoding technique”); and
decode the second parity data based on the second encoding algorithm (D’Abreu: Paragraph [0049], “The controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to decode the data 112, 122. For example, the controller 130 may access the parameter 150 to determine that the ECC codeword 120 is encoded using a first encoding technique and/or that the ECC codeword 120 is to be decoded using a first decoding technique that corresponds to the first encoding technique. As another example, the controller 130 may access the parameter 152 to determine that the ECC codeword 110 is encoded using a second encoding technique and/or that the ECC codeword 110 is to be decoded using a second decoding technique that corresponds to the second encoding technique”).
Regarding Claim 18, D’Abreu in view of Hsu-NVMe teaches the memory controller of claim 15, as referenced above, further configured to:
store a first identifier of the first user data, wherein the first identifier corresponds to the first encoding algorithm (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use).; and
store a second identifier of the second user data, wherein the second identifier corresponds to the second encoding algorithm (see above).
Regarding Claim 19, D’Abreu in view of Hsu-NVMe teaches the memory controller of claim 18, as referenced above, wherein the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table, and wherein logical addresses of the first user data are mapped to the first identifier in the P2L mapping table, and logical addresses of the second user data are mapped to the second identifier in the P2L mapping table (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use).
Claims 3-7, 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over D’Abreu in view of Hsu-NVMe, in further view of HU et al. (US 20130124945 A1, hereinafter “Hu”).
Regarding Claim 3, D’Abreu in view of Hsu-NVMe teaches the method of claim 1, as referenced above.
D’Abreu in view of Hsu-NVMe does not teach:
wherein the first parity data and the second parity data comprise low-density-parity-check (LDPC) parity data, and wherein the first encoding algorithm comprises a first LDPC matrix, and the second encoding algorithm comprises a second LDPC matrix.
However, Hu teaches:
wherein the first parity data and the second parity data comprise low-density-parity-check (LDPC) parity data (Hu: Paragraph [0003], “Data storage applications (for example, solid state drives, hard disk drives, and the like) may use low density parity check (LDPC) to correct errors that occur when storing and reading, or sending and receiving information. One design choice in planning LDPC coding systems is an amount of redundancy (ECC parity bits) used to meet the product specification. This redundancy is represented by the code rate of an LDPC code, which is equal to the user data length divided by the total number of bits stored. The general trend is that the lower the code rate is (more redundancy added), the better protection of the user data, and better performance in error detection and correction. If the code rate is chosen too high, the device may fail before the targeted program/erasure lifetime due to increasing error rates. On the other hand, if the code rate is chosen too low, extra storage space is wasted. Different LDPC encoder/decoder designs are implemented for different code rates, and for different chips/technologies or applications. Devices from different manufacturers may utilize different code rates, and, in that regard, code rates may span a wide range”), and wherein the first encoding algorithm comprises a first LDPC matrix, and the second encoding algorithm comprises a second LDPC matrix (Hu: Paragraph [0024], “Each encoder of encoder bank 204 processes input data to produce a codeword, including, for example, a data payload appended by error correction data. As described previously, an encoder is configured to encode a data payload u using an LDPC generator matrix G, to produce a codeword c”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine D’Abreu, Hsu-NVMe, and Hu by using low-density-parity-check parity data and matrices to encode, as taught by Hu. One of ordinary skill in the art would be motivated to make this modification in order to reduce error rates produced over time. (Hu: Paragraphs [0006]-[0008]).
Regarding Claim 4, D’Abreu in view of Hsu-NVMe, in further view of Hu teaches the method of claim 3, as referenced above, further comprising:
storing a first identifier of the first user data in a memory controller of the memory system, wherein the first identifier corresponds to the first encoding algorithm (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use).; and
storing a second identifier of the second user data in the memory controller, wherein the second identifier corresponds to the second encoding algorithm (see above).
Regarding Claim 5, D’Abreu in view of Hsu-NVMe, in further view of Hu teaches the method of claim 4, as referenced above, wherein the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use).
Regarding Claim 6, D’Abreu in view of Hsu-NVMe, in further view of Hu teaches the method of claim 5, as referenced above, wherein logical addresses of the first user data are mapped to the first identifier in the P2L mapping table, and logical addresses of the second user data are mapped to the second identifier in the P2L mapping table (D’Abreu: Paragraph [0038], “After accessing the logical-to-physical address mapping table 166, the controller 130 may access the ECC parameter table 148 to determine one or more encoding techniques to encode the first data and the second data. For example, if the controller 130 receives first data that is to be stored at the physical page 118, the controller 130 may access the ECC parameter table 148 to determine that the parameter 150 indicates that the first data is to be encoded using a first encoding technique. As another example, the controller 130 may access the ECC parameter table 148 to determine that second data to be stored at the physical page 108 is to be encoded using a second encoding technique that is different than the first encoding technique”; wherein the identifiers are merely the physical pages that correlate to which encoding technique to use).
Regarding Claim 7, D’Abreu in view of Hsu-NVMe, in further view of Hu teaches the method of claim 4, as referenced above, further comprising:
identifying the first LDPC matrix based on the first identifier (Hu: Paragraph [0003], “Data storage applications (for example, solid state drives, hard disk drives, and the like) may use low density parity check (LDPC) to correct errors that occur when storing and reading, or sending and receiving information. One design choice in planning LDPC coding systems is an amount of redundancy (ECC parity bits) used to meet the product specification. This redundancy is represented by the code rate of an LDPC code, which is equal to the user data length divided by the total number of bits stored. The general trend is that the lower the code rate is (more redundancy added), the better protection of the user data, and better performance in error detection and correction. If the code rate is chosen too high, the device may fail before the targeted program/erasure lifetime due to increasing error rates. On the other hand, if the code rate is chosen too low, extra storage space is wasted. Different LDPC encoder/decoder designs are implemented for different code rates, and for different chips/technologies or applications. Devices from different manufacturers may utilize different code rates, and, in that regard, code rates may span a wide range”; Paragraph [0024], “Each encoder of encoder bank 204 processes input data to produce a codeword, including, for example, a data payload appended by error correction data. As described previously, an encoder is configured to encode a data payload u using an LDPC generator matrix G, to produce a codeword c”; and Paragraph [0023], “A SSD controller 201 is operably connected to one or more flash memory devices 202 over a memory channel bus 203. By example, and without limitation, controller 201 includes one or more encoder banks 204 of encoders and one or more banks 205 of decoders. Each bank includes a respective encoder or decoder for a predetermined code rate, with each bank facilitating encoding or decoding according to a selected code rate”); and
decoding the first parity data based on the first LDPC matrix (Hu: Paragraph [0023], “In the depicted example, encoder bank 204 includes a high-rate encoder A 206, a mid-rate encoder 207, and a low-rate encoder 208. Likewise decoder bank 205 includes a high-rate decoder 209, a mid-rate decoder 210, and a low-rate decoder 211. The high-rate, mid-rate, and low-rate encoder/decoder combinations are operable to encode and decode data throughout the life of the SSD, at code rates described previously with respect to FIGS. 1B, 1C, and 1D. While the example of FIG. 2 depicts a system with multiple encoder and decoder pairs, each configured to a different code rate”).
Regarding Claim 11, D’Abreu in view of Hsu-NVMe teaches the system of Claim 9 above. The method of Claim 3 performs the same steps as the system of Claim 11, and Claim 11 is rejected using the same art and rationale set forth above in the rejection of Claim 3 by the teachings of D’Abreu in view of Hsu-NVMe, in further view of Hu.
Regarding Claim 20, D’Abreu in view of Hsu-NVMe teaches the memory controller of claim 15, as referenced above.
D’Abreu in view of Hsu-NVMe does not teach:
wherein the first parity data and the second parity data comprise low-density-parity-check (LDPC) parity data, wherein the first encoding algorithm comprises a first LDPC matrix, and the second encoding algorithm comprises a second LDPC matrix.
However, Hu teaches:
wherein the first parity data and the second parity data comprise low-density-parity-check (LDPC) parity data (Hu: Paragraph [0003], “Data storage applications (for example, solid state drives, hard disk drives, and the like) may use low density parity check (LDPC) to correct errors that occur when storing and reading, or sending and receiving information. One design choice in planning LDPC coding systems is an amount of redundancy (ECC parity bits) used to meet the product specification. This redundancy is represented by the code rate of an LDPC code, which is equal to the user data length divided by the total number of bits stored. The general trend is that the lower the code rate is (more redundancy added), the better protection of the user data, and better performance in error detection and correction. If the code rate is chosen too high, the device may fail before the targeted program/erasure lifetime due to increasing error rates. On the other hand, if the code rate is chosen too low, extra storage space is wasted. Different LDPC encoder/decoder designs are implemented for different code rates, and for different chips/technologies or applications. Devices from different manufacturers may utilize different code rates, and, in that regard, code rates may span a wide range”), wherein the first encoding algorithm comprises a first LDPC matrix, and the second encoding algorithm comprises a second LDPC matrix (Hu: Paragraph [0024], “Each encoder of encoder bank 204 processes input data to produce a codeword, including, for example, a data payload appended by error correction data. As described previously, an encoder is configured to encode a data payload u using an LDPC generator matrix G, to produce a codeword c”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine D’Abreu, Hsu-NVMe, and Hu by using low-density-parity-check parity data and matrices to encode, as taught by Hu. One of ordinary skill in the art would be motivated to make this modification in order to reduce error rates produced over time. (Hu: Paragraphs [0006]-[0008]).
Response to Arguments
Applicant's arguments filed 09/16/2025 with respect to 35 U.S.C. 102/103 have been fully considered but they are moot.
Regarding 35 U.S.C. 101 (software per se), Applicant’s arguments with respect to have been fully considered and are persuasive. The rejections of claims 15-20 have been withdrawn.
Regarding 35 U.S.C. 101 (abstract idea), Applicant’s arguments with respect to have been fully considered and are persuasive. The rejections of claims 1-20 have been withdrawn.
Regarding 35 U.S.C. 102/103, Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly cited art Hsu-NVMe teaches first user data of a first LBA format and second user data of a second LBA format to allow the host to define the size of user data (Hsu: [0029]).
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
NVMe (NPL: “NVMe Namespaces”) – Page 1: a namespace is a collection of LBAs accessible to host software. Page 6: each namespace can be formatted separately with secure erase, crypto erase and sanitize… other[ drives] may allow for different LBA sizes and formats per namespace
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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