DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/08/25 has been considered by the examiner.
Drawings
The drawings received on 06/13/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7, 9-11, 13-14 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiangxi Celfras Integrated circuit Ltd (CN 110134176 B).
Song et al. disclose an LCD circuit and wireless charging system in Figures 1-6.
With regard to claim 1. A power supply circuit (Figure 1) comprising: a first transistor (MP1); a first amplifier (101) including an output coupled to a gate of the first transistor and a first input coupled to a reference node; a current sensing circuit (104) including an input coupled to the gate of the first transistor (MP1); and a first multiplexer (103) including a first input coupled to a drain of the first transistor, a second input coupled to an output of the current sensing circuit (104), and an output coupled to a second input of the first amplifier (101) (see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”).
With regard to claim 2. The power supply circuit of claim 1, wherein the first multiplexer (103) is configured to: select the first input of the first multiplexer in a voltage regulator configuration for the power supply circuit; and select the second input of the first multiplexer in a current regulator configuration for the power supply circuit (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode)..
With regard to claim 7. The power supply circuit of claim 1, further comprising a gate driver including an input coupled to the output of the first amplifier (101) and an output coupled to the gate of the first transistor (MP1).
.
With regard to claim 9. A power supply circuit comprising a low-dropout (LDO) regulator circuit (see [1112-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), the power supply circuit being selectively configurable as a current regulator or as a voltage regulator with respect to a load for the LDO regulator circuit (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode)..
With regard to claim 10. The power supply circuit of claim 9, further comprising: a current sensing circuit (104) including an input coupled to a control node of the LDO regulator circuit (see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), a first input of the LDO regulator circuit being coupled to a reference node; and a first multiplexer (103) including a first input coupled to an output of the LDO regulator circuit, a second input coupled to an output of the current sensing circuit (104), and an output coupled to a second input of the LDO regulator circuit.
With regard to claim 11. The power supply circuit of claim 10, wherein the first multiplexer (103) is configured to: select the first input of the first multiplexer to configure the power supply circuit as the voltage regulator; and select the second input of the first multiplexer to configure the power supply circuit as the current regulator (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode)..
With regard to claim 13. A method of supplying power (Figure 1), the method comprising: generating a representative version of a current flowing through a pass transistor (MP1) of a low-dropout (LDO) regulator circuit; s\(see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), selecting to feed back the representative version of the current to an amplifier (101) as current feedback or to feed back a voltage from a drain of the pass transistor to the amplifier (101) as voltage feedback; and driving, with the amplifier, a gate of the pass transistor of the LDO regulator circuit based on the selected current or voltage feedback (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode)
With regard to claim 14. The method of claim 13, further comprising powering a device with the current flowing through the pass transistor (MP1), wherein the selecting comprises selecting to feed back the representative version of the current to the amplifier (101) as the current feedback.
With regard to claim 17. The method of claim 13, wherein the selecting comprises controlling a first multiplexer (103) including a first input receiving the voltage feedback and a second input receiving the current feedback (where the multiplexer 103 selects the voltage mode or the current mode).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over .
Jiangxi Celfras Integrated circuit Ltd (CN 110134176 B) in view of Cozzolino Carmine (US 2013/320881 A1).
Jiangxi Celfras Integrated circuit Ltd. disclose the claimed invention except for the use of an LED as a load. Cozzoliono teach the use of an LED as a load.
Jiangxi Celfras Integrated circuit Ltd. discloses a power supply circuit comprising a low-dropout (LDO) regulator circuit (see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), the power supply circuit being selectively configurable as a current regulator or as a voltage regulator with respect to a load for the LDO regulator circuit (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode).
Cozzolino teach in Figure 2 an LED 115 as a load supplied by an LDO 200.
It would have been obvious to one having ordinary skill in the art at the time of filing of the invention to provide an LED as taught by Cozzolina in Jiangxi Celfras Integrated circuit Ltd. power supply to provide an accurate output voltage to power the LED.
Allowable Subject Matter
Claims 3-6, 12, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “a power supply rail coupled to a source of the first transistor; a reference current source coupled between the power supply rail and a reference current node; a first resistive element coupled between the reference current node and a reference potential node; and a second resistive element coupled between the second input of the first multiplexer and the reference potential node“ in addition to other limitations recited therein.
Dependent claim 4 is allowable by virtue of their dependency.
Claim 5 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “a second multiplexer including a first input coupled to a reference voltage source, a second input coupled to a reference current source, and an output coupled to the first input of the first amplifier “ in addition to other limitations recited therein
Claim 6 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “wherein the current sensing circuit comprises: a second transistor; a third transistor including a drain coupled to the drain of the second transistor and a source coupled to the second input of the first multiplexer; and a second amplifier including a first input coupled to the drain of the third transistor, a second input coupled to the drain of the first transistor, and an output coupled to a gate of the third transistor“ in addition to other limitations recited therein
Claim 12 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “ a reference voltage source; a reference current source; and a second multiplexer including a first input coupled to the reference voltage source, a second input coupled to the reference current source, and an output coupled to the reference node“ in addition to other limitations recited therein.
Claim 16 is allowed because the prior art of record fails to disclose or suggest a method of supplying power including the limitation “wherein generating the representative version of the current flowing through the pass transistor comprises driving, with the amplifier, a gate of another transistor, the other transistor being a same transistor type as the pass transistor to generate the representative version of the current” in addition to other limitations recited therein.
Claim 18 is allowed because the prior art of record fails to disclose or suggest a method of supplying power including the limitation “wherein the selecting further comprises controlling a second multiplexer including a first input coupled to a reference voltage source and a second input coupled to a reference current source” in addition to other limitations recited therein
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jiang et al. (US 2025/0300617 A1) disclose a voltage regulator with skewed current mirror.
Yen et al. (US 11,705,812 B2) disclose a current-base transitions between buck converter and charge pump modes in an adaptive combination power supply circuit.
Chaput et al. (US 10,666,145 B2) disclose a highly integrated high voltage actuator driver.
Freeman et al. (US 9,602,016 B2) disclose an electrical circuit for delivering power to consumer electronic devices.
Williams et al. (US 8,841,897 B2) disclose a voltage regulator having current voltage foldback based upon load impedance.
Examiner has cited particular columns, line numbers and/or paragraphs in thereferences applied to the claims above for the convenience of the applicant. Althoughthe specified citations are representative of the teachings of the art and are applied tospecific limitations within the individual claim(s), other passages and figures may applyas well.
Additionally, in the event that other prior art is provided and made of record by theExaminer, as being relevant or pertinent to applicant's disclosure but not relied upon.The references are provided for the convenience of the applicant. The Examinerrequest that the references be considered in any subsequent amendments, as they arealso representative of the art and may apply to the specific limitations ofany newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of theclaimed invention, as well as the context of the passage as taught by the prior art and/ordisclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied upon inorder to ensure proper interpretation of the newly added limitations and toverify/ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7:00 AM to 4:00 PM.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838