DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 06/13/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9, 13-14 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiangxi Celfras Integrated circuit Ltd (CN 110134176 B).
Song et al. disclose an LCD circuit and wireless charging system in Figures 1-6.
With regard to claim 9. A power supply circuit comprising a low-dropout (LDO) regulator circuit (see [1112-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), the power supply circuit being selectively configurable as a current regulator or as a voltage regulator with respect to a load for the LDO regulator circuit (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode) and reference voltage source; a reference current source; and a first multiplexer (103) including a first input coupled to the reference voltage source (voltage mode loop), a second input coupled to the reference current source (current mode loop), and an output coupled to the reference node (see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”).
With regard to claim 13. A method of supplying power (Figure 1), the method comprising: generating a representative version of a current flowing through a pass transistor (MP1) of a low-dropout (LDO) regulator circuit; s\(see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), selecting to feed back the representative version of the current to an amplifier (101) as current feedback or to feed back a voltage from a drain of the pass transistor to the amplifier (101) as voltage feedback; wherein the selecting comprises controlling a first multiplexer including a first input coupled to a reference voltage source and a second input coupled to a reference current source and driving, with the amplifier, a gate of the pass transistor of the LDO regulator circuit based on the selected current or voltage feedback (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode)
With regard to claim 14. The method of claim 13, further comprising powering a device with the current flowing through the pass transistor (MP1), wherein the selecting comprises selecting to feed back the representative version of the current to the amplifier (101) as the current feedback.
With regard to claim 17. The method of claim 13, wherein the selecting further comprises controlling a first multiplexer (103) including a first input receiving the voltage feedback and a second input receiving the current feedback (where the multiplexer 103 selects the voltage mode or the current mode).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over .
Jiangxi Celfras Integrated circuit Ltd (CN 110134176 B) in view of Cozzolino Carmine (US 2013/320881 A1).
Jiangxi Celfras Integrated circuit Ltd. disclose the claimed invention except for the use of an LED as a load. Cozzoliono teach the use of an LED as a load.
Jiangxi Celfras Integrated circuit Ltd. discloses a power supply circuit comprising a low-dropout (LDO) regulator circuit (see [0001-0002], in particular “LDO circuit … most power supplies will power the subsequent core circuits through LDO”), the power supply circuit being selectively configurable as a current regulator or as a voltage regulator with respect to a load for the LDO regulator circuit (see [0053] in particular “The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are opened and closed by a multiplexer, thereby switching the voltage mode loop and the current mode loop”, see also Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode).
Cozzolino teach in Figure 2 an LED 115 as a load supplied by an LDO 200.
It would have been obvious to one having ordinary skill in the art at the time of filing of the invention to provide an LED as taught by Cozzolina in Jiangxi Celfras Integrated circuit Ltd. power supply to provide an accurate output voltage to power the LED.
Allowable Subject Matter
Claims 1-4, 6-8 and 16 are allowed over the cited prior art of record..
Claims 10-11 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 1 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “a second multiplexer including a first input coupled to a reference voltage source, a second input coupled to a reference current source, and an output coupled to the first input of the first amplifier“ in addition to other limitations recited therein
Dependent claim 2 is allowable by virtue of their dependency.
Claim 3 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “a power supply rail coupled to a source of the first transistor; a reference current source coupled between the power supply rail and a reference current node; a first resistive element coupled between the reference current node and a reference potential node; and a second resistive element coupled between the second input of the first multiplexer and the reference potential node“ in addition to other limitations recited therein.
Dependent claim 4 is allowable by virtue of their dependency.
Claim 6 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “wherein the current sensing circuit comprises: a second transistor; a third transistor including a drain coupled to the drain of the second transistor and a source coupled to the second input of the first multiplexer; and a second amplifier including a first input coupled to the drain of the third transistor, a second input coupled to the drain of the first transistor, and an output coupled to a gate of the third transistor“ in addition to other limitations recited therein.
Dependent claims 7-8 are allowable by virtue of their dependency.
Claim 16 is allowed because the prior art of record fails to disclose or suggest a method of supplying power including the limitation “wherein generating the representative version of the current flowing through the pass transistor comprises driving, with the amplifier, a gate of another transistor, the other transistor being a same transistor type as the pass transistor to generate the representative version of the current” in addition to other limitations recited therein.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation further comprising: a current sensing circuit including an input coupled to a control node of the LDO regulator circuit, the first input of the LDO regulator circuit being coupled to a reference node; and a second multiplexer including a first input coupled to an output of the LDO regulator circuit, a second input coupled to an output of the current sensing circuit, and an output coupled to a second input of the LDO regulator circuit“ in addition to other limitations recited therein.
Dependent claim 11 is allowable by virtue of their dependency.
Claim 19 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “further comprising: a power supply rail, wherein the LDO regulator circuit comprises a pass transistor, wherein the power supply rail is coupled to a source of the pass transistor, and wherein the reference current source is coupled between the power supply rail and the second input of the first multiplexer; a first resistive element coupled between the second input of the first multiplexer and a reference potential node; and a second resistive element coupled between a second input of the LDO regulator circuit and the reference potential node” in addition to other limitations recited therein
Claim 20 is allowed because the prior art of record fails to disclose or suggest a power supply circuit including the limitation “further comprising a current sensing circuit including an input coupled to an output of the LDO regulator circuit, wherein the LDO regulator circuit comprises a pass transistor and wherein the current sensing circuit comprises: a first transistor including a gate coupled to the input of the current sensing circuit; a second transistor including a drain coupled to a drain of the first transistor and a source coupled to a second input of the LDO regulator circuit; and an amplifier including a first input coupled to the drain of the second transistor, a second input coupled to a drain of the pass transistor, and an output coupled to a gate of the second transistor” in addition to other limitations recited therein
Response to Arguments
Applicant's arguments filed 05/22/26 have been fully considered but they are not persuasive.
Claims 12 and 18 were objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant amended independent claim 9 with allowable claim 12 but without incorporating the intervening claim 10.
Applicant also amended independent claim 13 with allowable claim 18. Without incorporating the intervening claim 18.
As stated in the previous office claims 12 and 18 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Therefore not incorporating the intervening claim doesn’t place the independent claims allowable.
With regard to amended claim 9, doesn’t include all the limitation of allowable claim 12. Claim 12 included “second multiplexer” instead applicant amended it to “first multiplexer” in order not to include intervening claim 10 which recited “a first multiplexer”. The intervening claim 10 was rejected..
Jiangxi Celfras Integrated circuit Ltd (CN 110134176 B) shows a multiplexer figure 4, 104 which was identified in the previous office action.
With regard to amended claim 13, doesn’t include all the limitation of allowable claim 18. Claim 18 included “second multiplexer” instead applicant amended it to “first multiplexer” in order not to include intervening claim 17 which recited “a first multiplexer”. The intervening claim 17 was rejected.
Jiangxi Celfras Integrated circuit Ltd (CN 110134176 B) shows a multiplexer figure 4, 104. Figure 4 showing a multiplexer 103 for selecting the configuration in a voltage mode or a current mode.
Applicant is reminded that the two intervening claims 10 and 17 were rejected, therefore in order to place independent claims 9 and 13 allowable it has to include the intervening claims along with the originally objected claims 12 and 18.
Conclusion
Examiner has cited particular columns, line numbers and/or paragraphs in thereferences applied to the claims above for the convenience of the applicant. Althoughthe specified citations are representative of the teachings of the art and are applied tospecific limitations within the individual claim(s), other passages and figures may applyas well.
Additionally, in the event that other prior art is provided and made of record by theExaminer, as being relevant or pertinent to applicant's disclosure but not relied upon.The references are provided for the convenience of the applicant. The Examinerrequest that the references be considered in any subsequent amendments, as they arealso representative of the art and may apply to the specific limitations ofany newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of theclaimed invention, as well as the context of the passage as taught by the prior art and/ordisclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied upon inorder to ensure proper interpretation of the newly added limitations and toverify/ascertain the metes and bounds of the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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