DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Response to Arguments
Applicant's arguments filed 2/23/26 have been fully considered but they are not persuasive.
In regards to applicants argument that “in Gillingham, the functional logic circuits receive clock signals with different phases, rather than the transmitting circuits. The applicant points out the functions of the functional logic circuit of Gillingham are not signal transmitting circuits, as shown in following Gillingham's column 3, lines 51-6 and column 4, lines 19-23.”: The examiner agrees that “the function logic circuits receive clock signals with different phase” because these phase are transmitted to the functional logic from the clock phase generator. The circuits that transmits/transports the clock phases to the functional logic is the claimed transmitting circuit. The examiner disagrees with the second half of the statement “rather than the transmitting circuits”. The different clock signals with different phases are supplied to transmitting circuits (drivers in 5120, 5220, 5320 and 5420 respectively). A driver is a transmitting circuit. Clock tree 5220, 5320, 5420 are the other transmitting circuits. In figure 5 the clock phase W is supplied to transmitting circuit 5120. The clock phase Y is supplied to the driver in transmitting circuit 5220. The clock phase X is supplied to the driver in transmitting circuit 5320. Clock phase Z is supplied to the driver in transmitting circuit 5420. A driver is by definition a transmitting circuit. Applicants appear to be applying different meaning to the word “transmitting” to mean something other than simply transmitting/transporting as in driving. Gillingham et al states “FIG. 5 is a block diagram of a distribution network 5000 for transporting the four-phase clock signals from circuit 4000, FIG. 4, to logic circuits such as 2000, FIG. 2, on the same chip.”. Gillingham, et al also states “Circuit 4000 generates phase X (wave 3220) by delaying phase W by 1/4 cycle (90.degree.). Phase Z (wave 3240) is the inverse of phase X, obtained by interchanging the two wires of its signal line”. Thus Gillingham et al teaches generating the clock phases in 4000 and transmitting the generated clock in 5120, 5220, 5320, and 5420 to the logic circuits in 2000.
In regards to applicants argument that “Gillingham does not work in different channels or different lanes. The components 5125, 5225, 5325 of Gillingham”: This is clearly incorrect. Applicant appears to be defining the term channel/lane different than its standard meaning Gillingham et al teaches 4 separate channels/lanes 5125, 5225, 5325, and 5425. There is nothing in applicants claim language that would require these channels/lanes 5125, 5225, 5325, 5425 to not read on the claimed channels. A lane is simply a line upon which a signal is transmitted.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-11, 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gillingham et al PN 5,124,571.
In regards to claims 1, 9, 18: Gillingham et al teaches a signal transmitting system (figures 4 and 5), comprising: a first transmitting circuit (driver 5121), operating according to a first operation clock signal (W) with a first phase (column 4 line 19 et seq. "The waveform 3210 of phase W rises at the 0.degree"); a second transmitting circuit (5220, 5320, or 5420), operating according to a second operation clock signal (X, Y or Z) with a second phase (Column 4 line 19 et seq. "Waveform 3220 of phase X rises at the 90.degree" Y and Z are the inverse of W and X respectively thus raise at 180 and 270 degrees respectively), wherein the first phase and the second phase are different (0 degrees is different from 90 degrees is different from 180 degrees is different from 270 degrees); and a multi-phase clock signal generating circuit (Column 5 line 35 et seq. "In one form of the embodiment described more fully in connection with FIG. 5, conventional circuits convert each clock phase separately to single-ended form at the outputs of the phase-generation circuit shown in FIG. 4" and Column 6 line 54 "FIG. 4 is a diagram of a circuit 4000 for producing differential signals representing the clock phases W-Z having the waveforms shown as 3210-3240 in FIG. 3" … "Therefore, generating four equally-spaced clock phases in this system requires only the generation of a 90.degree.-degree phase shift from an incoming master clock. As shown in FIG. 3, phase W (wave 3210) is the same as the single-phase master clock signal MC (wave 3410). Phase Y (wave 3230) is the inverse of phase W, obtained by interchanging the two wires of its signal line. Circuit 4000 generates phase X (wave 3220) by delaying phase W by 1/4 cycle (90.degree.). Phase Z (wave 3240) is the inverse of phase X, obtained by interchanging the two wires of its signal line. That is, the major function of circuit 4000 is to produce an accurate, stable 90.degree.-phase shift of an input differential signal and to output it in a compatible form."), coupled to the first transmitting circuit and the second transmitting circuit, to generate the first operation clock signal and the second operation clock signal (Coupled via signal lines 4103, 4104, 4710, 4711).
In regards to claims 2, 10: Gillingham et al teaches different channels (5125, 5225, 5325, 5425).
In regards to claims 3, 11: Gillingham et al teaches the transmitters are drivers with the driver of the first transmitter operating at the first operational clock signal and the driver of the second transmitter operating at the second operational clock signal.
In regards to claim 17: Gillingham et al teaches multiple transmitting circuits at least 2 for each phase. This minimum of 8 is larger than 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, 12-13, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gillingham et al PN 5,124,571 in view of Saeki PN 2007/0177700.
In regards to claim 4, 12, 19: Gillingham et al teaches generating the four phases and transmitting them on separate channels as described above. Gillingham et al however does not state the four phase clock generator is a phase locked loop. Saeki teaches a "conventional" four phase, phase locked loop ([0002] "Referring to FIG. 5, a four-phase clock generation circuit (abbreviated as a "four-phase generation circuit") 10 receives a clock signal CLK generated by a PLL (Phase Locked Loop) circuit or the like not shown, and generates four-phase clock signals with phases thereof mutually spaced by 90 degrees by frequency division of the clock signal CLK." It would have been obvious to have Gillingham et al's clock phase generator be phase locked because this would have prevented clock deviation over time.
In regards to claims 5, 13: Saeki teaches a PLL circuit generating the plurality of clock signals as well as a first and a second interpolator circuit 30₁ and 30₂ coupled to different phases.
Claim(s) 6-7, 14-15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gillingham et al PN 5,124,571 in view of Lomas et al PN 2009/0304112.
In regards to claims 6, 14, 20: Gillingham et al does not teach a random clock signal. Lomas et al teaches ([0009] "The preferred embodiment of the invention includes a digitally clocked Automatic Gain Control (AGC) loop utilising a Pseudo Random Binary (PRBS) clock. The purpose of the PRBS clock is to spread the energy of any signal sidebands that are formed in the signal path due to switching the gain in discrete steps"). It would have been obvious to use a PRBS clock because this would "spread the energy of any signal sidebands that are formed in the signal path due to switching".
In regards to claims 7, 15: Lomas teaches PRBS.
Claim(s) 8, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gillingham et al PN 5,124,571 in view of Bhagwan PN 5,781,055.
In regards to claims 8, 16: Gillingham et al teaches four phase clock generation however the clock generation is not using a delay line. Bhagwan teaches a four phase clock generator using a delay line (figure 4 and Column 3 line 53 et seq. " The tapped output nodes 30A-30D carry the multi-phase clock signals generated by the delay line 62"). All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL R MYERS whose telephone number is (571)272-3639. The examiner can normally be reached telework M-F start 7-8 leave 4-5.
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/Paul R. MYERS/ Primary Examiner, Art Unit 2176