DETAILED ACTION
Claims 1, 19, 24, 25 are amended. Claim 6 is canceled.
Claims 1-5, 6-25 are pending.
Priority: June 16, 2023
Assignee: Akeana
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1,24,25 are rejected for reciting a limitation with antecedent issues.
Amended Claim 1, recites, ‘wherein the sending an invalidating snoop instruction occurs prior to the transmitting a forwarding snoop instruction’.
But claim 1 in prior limitations recites, ‘sending,…. an invalidating snoop instruction’….. and ‘transmitting,…., a forwarding snoop instruction,’.
Here, the first mention used ‘an invalidating instruction’ and ‘a forwarding snoop instruction’. So subsequent mention of the same elements must use ‘the’. Claims 24-25 have a similar issue.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-18, 20-25 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Jalal et al (20190079868) in view of Arm (‘AMBA 5 CHI Architecture Specification’, 2014, Pgs. 1-20 to 16-463) and Tune (20140281180).
As per Claim 1, Jalal discloses a processor-implemented method for cache management (Jalal, [0015 – In Fig. 1, a System-on-Chip/SoC contains multiple processing devices, multiple data caches and shared data resources]; [0020 - A cache coherence protocol employs a MOESI cache coherence model]) comprising:
accessing a system on a chip (SOC) (Jalal, [0015 – In Fig. 1, system 100 is implemented in a System-on-Chip/SoC]) wherein the SOC communicates internally on a coherent bus (Jalal, [Fig. 1: interconnect circuit 106/coherent bus]; [0015 – In Fig. 1, blocks 102 generate data access requests and are called request nodes/RNs]),
wherein the SOC includes a plurality of coherent request nodes (Jalal, [Fig. 1: request nodes/RN’s or RN-F’s]) and a first coherent home node (Jalal, [Fig. 1: a home node 108, HN-F]),
and the first coherent home node includes a directory-based snoop filter (DSF) (Jalal, [Fig. 1: a snoop filter 400/DSF]; [Fig. 5: snoop filter directory]),
wherein the DSF comprises a cache with a plurality of ways (Jalal, [0019 – In Fig. 1, snoop filter 400 monitors data transactions and maintains the status of data stored in system cache 116]);
requesting, by a first coherent request node within the plurality of coherent request nodes (Jalal, [Fig. 1]), ownership of a coherent cache line within the SOC (Jalal, [0050 – As per Table 2, request node, RNF1, performs a cacheable read to the same memory location/address A]),
wherein the requesting includes an address associated with the coherent cache line (Jalal, [0050 - location/address A]);
detecting, by the first coherent home node, that the coherent cache line is shared with one or more other coherent request nodes (Jalal, [0050 – The read causes the HNF snoop filter to send a snoop to RNF0 for address A, since the snoop filter presence vector indicates that the data is in the cache of RNF0, thereby implying detecting by the home node that the coherent cache line is shared with other RN-Fs]),
wherein the detecting is based on a presence vector within the DSF of the first coherent home node (Jalal, [0050 - The snoop filter/DSF presence vector indicates that the data is in the cache of RNF0]);
determining, by the first coherent home node, a current owner of the coherent cache line (Jalal, [0027 - The snoop filter cache 302 contains a number of records 308 associated with cached data in the system. Each record 308 comprises tag field 310, a cache coherence status field 312, a RNF-ID field 314 that identifies the owner of any SharedDirty/SD or Owned data, and presence vector 316, thereby implying that the information helps the HN-F to determine the current owner of the cache line]),
wherein the determining is based on information within the DSF of the first coherent home node (Jalal, [0049 – As per Table 2, the snoop filter/DSF records the data as UniqueClean/UC and updates the presence vector to indicate that RNF0/current owner has a copy of the data]);
Arm further discloses,
sending, by the first coherent home node, to the one or more other coherent request nodes (Arm, [Pg. 1-27: See Figs. 1-2]; [Pg. 1-30: See Figs. 1-4]), except the current owner that was determined (Arm, [Pg. 4-189 - A snoop filter or directory within the interconnect to track the state of cache lines present in RN-F caches. The tracking can be as detailed as knowing each RN-F that has a copy of the cache line. Such tracking permits the ICN to filter unnecessary snooping of an RN-F, thereby implying determination of current owner]), an invalidating snoop instruction (Arm, [Pg. 1-24 - Write-Invalidate protocol - A protocol in which an RN writing to a cache line that is shared in the system must invalidate all the shared copies before proceeding with the write. The AMBA CHI protocol is a Write-Invalidate protocol]; [Pg. 4-186 – SnpCleanInvalid, SnpMakeInvalid; Since the claim does not recite any invalidating snoop instruction/transaction name, the recitation is a valid interpretation]);
transmitting (Arm, [Pg. 2-85 – See Fig. 2-25]), by the first coherent home node, a forwarding snoop instruction (Arm, [Pg. 2-85 - The interconnect/HN provides a Snoop request, SnpSharedFwd or SnpUniqueFwd, on the SNP channel; Also see Pg. 2-45]),
wherein the forwarding snoop instruction establishes a direct cache transfer (DCT) (Arm, [Pg. 4-222 - Forwarding Snoop transactions – Forwarding/Fwd type snoops are used by Home to support DCT/Direct Cache Transfer]) between the first coherent request node and the current owner of the coherent cache line (Arm, [Pg. 2-85 - The snooped RN/current owner forwards the Data to the Requester using the CompData opcode on the WDAT channel]; [Pg. 1-31 - Defines the feature which permits a peer RN-F to send Data directly to the Requester]),
wherein the sending an invalidating snoop instruction occurs prior to the transmitting a forwarding snoop instruction (Arm, [Pg. 4-162 – Coherence Protocol]; [Pg. 124, Write-Invalidate protocol - A protocol in which an RN writing to a cache line that is shared in the system must invalidate all the shared copies before proceeding with the write. The AMBA CHI protocol is a Write-Invalidate protocol; This implies that the invalidating snoop is broadcast on the bus before the writing node updates its local cache, which ensures that all other caches holding a copy of the data receive the invalidation signal and mark their copies as invalid. This further implies that the invalidating snoop occurs prior to the forwarding snoop]; [Pg. 4-222, Sec. 4.8.3: Forwarding Snoop transactions – Forwarding/Fwd type snoops are used by Home to support DCT]; [Pg. 2-85, Pg. 4-228 - Home is permitted to send the SnpUniqueFwd snoop to an RN-F in Shared state if Home determines that the invalidating snoop needs to be sent to only one cache, thereby also implying that the invalidating snoop precedes the forwarding snoop; Since the claim previously recites sending the invalidating snoop by the home node, to the one or more request nodes, it suggests sending the invalidating snoop to at least one request node. Therefore the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the coherence protocol of Arm into the multicore SoC architecture of Jalal, for the benefit of using a scalable packet-based communication where all transactions are handled by an interconnect-based Home Node that co-ordinates required snoops, cache, and memory accesses (Arm, Pg. 1-20).
Tune clarifies the DSF related cache as follows,
wherein the DSF comprises a cache with a plurality of ways (Tune, [0042 – In Fig. 1, inclusive snoop directory memory 14 is a SRAM memory having multiple ways, i.e. set associative. These ways are addressed using an index value derived from a portion of the memory address of the memory access request]; [0039 - Inclusive snoop directory memory 14/cache is part of a snoop filter/DSF]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the set associative DSF cache of Tune into the multicore SoC architecture of Jalal, Arm for the benefit of using the inclusive snoop directory memory for coherent writes and cache maintenance operations to reduce the amount of snoop traffic generated (Tune, 0041).
As per Claim 2, the rejection of claim 1 is incorporated, and Jalal discloses,
wherein the first coherent request node comprises a plurality of processor cores and caches (Jalal, [0015 – In Fig. 1, each functional block 102 comprises cluster of processing cores/CPUs that share an L2 cache, with each processing core having its own L1 cache]).
As per Claim 3, the rejection of claim 2 is incorporated, and Jalal discloses,
coupling, within the first coherent request node, a hierarchical cache to one or more processor cores within the plurality of processor cores (Jalal, [0015 – In Fig. 1, each RN-F 102 comprises cluster of processing cores/CPUs that share an L2 cache, with each processing core having its own L1 cache]),
wherein the hierarchical cache is shared among the one or more processor cores (Jalal, [0015 – In Fig. 1, cores/CPUs share an L2 cache]),
and wherein the hierarchical cache is further coupled to a compute coherency block (CCB) (Jalal, [0018 - To maintain coherence, each RN includes a cache controller 114/CCB]).
Arm clarifies the hierarchical cache as follows,
coupling, within the first coherent request node (Arm, [Fig. 11-1]), a hierarchical cache to one or more processor cores within the plurality of processor cores (Arm, [Pg. 11-351 – In Fig. 11-1, each chip in the system has two processors per cluster/RN, with a three level cache hierarchy]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the coherence protocol of Arm into the multicore SoC architecture of Jalal, Tune for the benefit of using a scalable packet-based communication where all transactions are handled by an interconnect-based Home Node that co-ordinates required snoops, cache, and memory accesses (Arm, Pg. 1-20).
As per Claim 4, the rejection of claim 3 is incorporated, and Jalal discloses,
wherein the requesting is accomplished by the CCB within the first coherent request node (Jalal, [0018 – In Fig. 1, to maintain coherence, each RN-F/first includes a cache controller 114 that accepts load and store instructions from the processor cores. The cache controller 114 also issues and receives coherence requests and responses via the interconnect circuit 106 from other nodes, thereby implying that the requesting is accomplished by the CCB within the first RN-F]).
As per Claim 5, the rejection of claim 4 is incorporated, and Jalal discloses,
wherein the forwarding snoop instruction establishes a DCT between the CCB (Jalal, [0018 - The cache controller 114/CCB also issues and receives coherence requests and responses via the interconnect circuit 106 from other nodes]) within the first coherent request node and the current owner of the coherent cache line (Jalal, [0031 - In response to the snoop, RNF0 downgrades the data in its cache to state SD, also in line 2 of the table, and provides data with snoop response. RNF1 receives the cache data in the SC state from RNF0 directly/DCT]).
Arm clarifies the forwarding snoop instruction and DCT as,
wherein the forwarding snoop instruction (Arm, [Pg. 1-26 – Transaction Classification, Snoop: SnpSharedFwd]) establishes a DCT (Arm, [Pg. 1-31 - DCT: Defines the feature which permits a peer RN-F to send Data directly to the Requester]) between the CCB within the first coherent request node and the current owner of the coherent cache line (Arm, [Pg. 4-194 - Snoop response without Data to Home and Direct Cache Transfer (DCT): This Snoop response is used when the Snoopee/current owner sends Data to the Requester]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the coherence protocol of Arm into the multicore SoC architecture of Jalal, Tune for the benefit of using a scalable packet-based communication where all transactions are handled by an interconnect-based Home Node that co-ordinates required snoops, cache, and memory accesses (Arm, Pg. 1-20).
As per Claim 7, the rejection of claim 3 is incorporated, and Jalal discloses,
wherein a second coherent request node, in the plurality of coherent request nodes, includes a CCB (Jalal, [0018 – In Fig. 1, to maintain coherence, each RN includes cache controller 114/CCB, thereby implying that the second RN-F includes a CCB]).
As per Claim 8, the rejection of claim 7 is incorporated, and Jalal discloses,
wherein the DSF includes an entry for each cache line within the hierarchical cache coupled to the CCB (Jalal, [Fig. 1]) of the second coherent request node and the hierarchical cache coupled to the CCB of the second coherent request node (Jalal, [0027 – In Fig. 3, snoop filter cache 302 contains a number of records 308 associated with cached data in the system. Each record 308/entry comprises tag field 310, a cache coherence status field 312, an RNF-ID field 314, and a presence vector 316. The presence vector 316 contains bits that indicate which nodes/RN-F’s of the system have the data in their local cache, thereby implying that the DSF includes an entry for each cache line within the hierarchical cache coupled to the CCB of the second RN-F]).
As per Claim 9, the rejection of claim 1 is incorporated, and Jalal discloses,
the determining further comprises searching, by the first coherent home node (Jalal, [0043 – In Fig. 5, following a request sent from an RN-F to the HN-F, to access data at an address in system memory, the address is looked-up in the system cache of the HN-F and in the snoop filter at step 504]), for a hit within the DSF on the address associated with the coherent cache line (Jalal, [0044 – In Fig. 5, step 510, determining if the address is found in the snoop filter,.i.e. snoop filter hit?]).
As per Claim 10, the rejection of claim 1 is incorporated, and Jalal discloses,
reading an owner ID and an owner valid bit within the DSF (Jalal, [0027 – In Fig. 3, each record 308 comprises tag field 310, which identifies the associated data, a cache coherence status field 312 that indicates the MOESI state of the data, an RNF-ID field 314 that identifies the owner of any SharedDirty or Owned data, and a presence vector 316. The presence vector 316 contains bits/owner valid bit that indicate which nodes of the system have the data in their local cache. Thus the snoop filter keeps track, in field 314, of the owner of SharedDirty/SD data in addition to all of the sharers of the data. The owner of the SD data is a device such as a Request Node for CPU cluster, GPU, DSP etc.]).
As per Claim 11, the rejection of claim 1 is incorporated, and Jalal discloses,
wherein the determining further comprises sending a read request to a memory (Jalal, [Fig. 5: step 510, SF hit? No]; [0043 – In Fig. 5, step 510, if the address is not found in the snoop filter, or a snoop filter ‘miss’ occurred, a signal to read the data from memory is sent to a memory controller at step 512]).
As per Claim 12, the rejection of claim 11 is incorporated, and Jalal discloses,
wherein an index of the address associated with the coherent cache line misses in the DSF (Jalal, [0043 – In Fig. 5, step 510, if the address is not found in the snoop filter, then a snoop filter miss occurred]).
As per Claim 13, the rejection of claim 12 is incorporated, and Jalal discloses,
forwarding data from memory to the first coherent request node (Jalal, [0043 – In Fig. 5, the data is received from the memory controller at step 514 and forwarded to the requesting RN-F/first at step 516]).
As per Claim 14, the rejection of claim 13 is incorporated, and Jalal discloses,
saving, in the DSF, details about the coherent cache line (Jalal, [0043 – In Fig. 5, step 512, the snoop filter is updated, thereby implying saving, in the DSF, details about the coherent cache line]).
As per Claim 15, the rejection of claim 2 is incorporated, and Jalal, Arm disclose the DSF or the snoop filter.
Tune further clarifies the DSF as follows,
wherein an index (Tune, [0042 – In Fig. 1, inclusive snoop directory memory 14 is an SRAM memory having multiple ways, i.e. set associative. These ways are addressed using an index value]) of the address associated with the coherent cache line misses in the DSF (Tune, [Fig. 4: step 46, Hit in snoop directory? No]), but all ways associated with the index are occupied (Tune, [0061 – In Fig. 4, step 54, a determination is made as to whether or not there is a free line available in the inclusive snoop directory memory 14, which may depend on the organization of the inclusive snoop directory memory, e.g. set associativity]; [Fig. 4: step 54, Free line in snoop directory? No, thereby implying that all ways associated with the index are occupied]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the set associative DSF cache of Tune into the multicore SoC architecture of Jalal, Arm for the benefit of using the inclusive snoop directory memory for coherent writes and cache maintenance operations to reduce the amount of snoop traffic generated (Tune, 0041).
As per Claim 16, the rejection of claim 15 is incorporated, and Jalal, Arm,
Tune disclose,
evicting a random entry within the way of the DSF that is associated with the index (Tune, [0061 – In Fig. 4, if no free line is detected at step 54, then processing proceeds to step 58 where a line is evicted from the inclusive snoop directory memory 14]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the set associative DSF cache of Tune into the multicore SoC architecture of Jalal, Arm for the benefit of using the inclusive snoop directory memory for coherent writes and cache maintenance operations to reduce the amount of snoop traffic generated (Tune, 0041).
As per Claim 17, the rejection of claim 16 is incorporated, and Jalal, Arm,
Tune disclose,
invalidating, by each coherent request node in the plurality of coherent request nodes (Tune, [0039 – In Fig. 1, L1 cache memories 6 for a pair of cores 4 share a L2 cache memory 8]), an entry corresponding to the random entry within the way of the DSF that was evicted (Tune, [Fig. 4: step 58: Evict line from snoop directory and invalidate/clean cache lines in L2 caches]; [0061 – In Fig. 4, the corresponding cache lines pointed to by the newly evicted directory line are invalidated, cleaned from the L2 cache memories 8]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the set associative DSF cache of Tune into the multicore SoC architecture of Jalal, Arm for the benefit of using the inclusive snoop directory memory for coherent writes and cache maintenance operations to reduce the amount of snoop traffic generated (Tune, 0041).
As per Claim 18, the rejection of claim 17 is incorporated, and Jalal discloses,
writing, to a memory, data from the entry that was evicted (Jalal, [0053 - If evicted, the data is written back to the memory since it was marked as ‘dirty’]),
wherein the data was marked as dirty in a coherent request node in the plurality of coherent request nodes (Jalal, [0051 - The system cache is filled and the data in the system cache is marked ‘dirty’, since the home node determines that the data store RNF0 should now be in the SD/SharedDirty state]).
As per Claim 20, the rejection of claim 1 is incorporated, and Jalal discloses,
wherein the plurality of coherent request nodes includes one or more multicore processors (Jalal, [0015 – In Fig. 1, functional blocks 102 each comprise cluster of processing cores/CPUs)]).
As per Claim 21, the rejection of claim 22 is incorporated, and Jalal, Arm, Tune disclose,
wherein the coherent bus implements an AMBA (Arm, [Pg. 483 – AMBA/ Advanced Microcontroller Bus Architecture provides solutions for the interconnection and management of the functional blocks that make up a System-on-Chip/SoC]) CHI coherency protocol (Arm, [Pg. 1-27, Fig. 1-2: Coherency model, ICN]; [Pg. 1-24 – ICN/interconnect which is the CHI transport mechanism that is used for communication between protocol nodes. The ICN might include protocol nodes such as Home Node and Misc Node]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the coherence protocol of Arm into the multicore SoC architecture of Jalal, Tune for the benefit of using a scalable packet-based communication where all transactions are handled by an interconnect-based Home Node that co-ordinates required snoops, cache, and memory accesses (Arm, Pg. 1-20).
As per Claim 22, the rejection of claim 1 is incorporated, and Jalal discloses,
wherein the SOC includes a second coherent home node (Jalal, [0015 – In Fig. 1, system 100 is implemented in a System-on-Chip/SoC integrated circuit, with second HN-F]).
As per Claim 23, the rejection of claim 22 is incorporated, and Jalal discloses,
wherein the requesting includes the first coherent home node and the second coherent home node (Jalal, [0015 – In Fig. 1 blocks 102/RN-F and 104/RN-F are request nodes that generate requests for data transactions. They are coupled via interconnect circuit 106, to data resources that are accessed via home nodes 108/HN-F’s and memory controller 110 that enable the request nodes to access shared main memory 112 or input/output devices, thereby implying that the requesting includes the first coherent home node and the second coherent home node]).
As per Claim 24, it is similar to claim 1 and therefore the same rejections are incorporated.
As per Claim 25, it is similar to claim 1 and therefore the same rejections are incorporated.
Claim 19 is rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Jalal et al (20190079868) in view of Arm (‘AMBA 5 CHI Architecture Specification’, 2014, Pgs. 1-20 to 16-463), Tune (20140281180), Randall et al (20230139212) and Forrest et al (20200218657).
As per Claim 19, the rejection of claim 18 is incorporated, and Jalal discloses,
saving, in the DSF, details about the coherent cache line (Jalal, [0054 – In Table 2, the presence vector in the SF/snoop filter/DSF is updated, to indicate that RNF0 no longer shares the data, and the data is stored in the system cache and marked ‘dirty’]),
Randall further discloses,
wherein the details include a presence vector (Randall, [0120 - Figs. 12A-12B a presence vector comprising multiple presence bits]; [0123 - Fig. 13 shows a 4-bit presence vector implementation]), an owner ID (Randall, [0126 – In Fig. 13, two bits from the tag portion of the address for cache line C are used to identify one of the bits in the presence vector 0 700 associated with set 0 of the backup snoop filter table; This representation is similar to Fig. 7 of the spec]), an owner valid field (Randall, [0125 - In Fig. 13, it is assumed that the relevant two bits of the tag portion of the address for cache lines A and B identify the third presence bit, and the relevant two bits of the tag portion of the address for cache line C identify the second presence bit, and accordingly the current state/valid of the presence vector 0 is 0110]; [0057 - When adopting an implementation that uses a presence bit vector in association with each of the sets in a lower level snoop filter table, then the current state/validity of the presence bits in the presence bit vector can be used to influence decisions taken when a victim entry is to be selected]), an index value (Randall, [0084 – In Fig. 3, the index portion 160 of the address is provided to a set determination function 197 which determines from that index portion an index value used to identify a particular set within the snoop filter table; It is well known in the art that in an m-way associative snoop filter, row index is same as set index]), and a valid field value (Randall, [0086 – In Fig. 4, at step 210, it is determined if there is a free entry in the identified set. One example of determining is when each of the entries includes a valid bit which is set to indicate that the corresponding entry stores valid coherence data]; [0087 - The valid bit will also be set to identify that the entry stores valid coherence data]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the presence vector of Randall into the multicore SoC architecture of Jalal, Arm, Tune for the benefit of having each entry store, for an associated address, coherence data used to determine which cache storages provided within the multiple processing units need to be subjected to a snoop operation in response to a request specifying that associated address. By using the presence vector, the snoop filter acts as a directory or a M-way associative set of tables, allowing the system to know where data is cached without having to query every single cache every time (Randall, 0006).
Forrest further clarifies the owner ID and owner field value as follows,
wherein the details include a presence vector, an owner ID, an owner valid field (Forrest, [0035 – In Fig. 4, each snoop filter entry stores one valid bit, an owner pointer, which is three bits in order to indicate one of five caching agents that owns a line, and a five-bit presence vector, indicating which of the five caching agents has each line present]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage and filter efficiency of Forrest into the multicore SoC architecture of Jalal, Arm, Tune, Randall for the benefit of having the filtering algorithm impact the number and organization of snoop filter entries and the type of state information stored in each entry. Such state information for a tag filter entry includes a pointer to which caching agent is designated the owner of the cache line, a valid bit that indicates the pointer is valid, and a vector indicating which caching a
agents have a copy of the cache line (Forrest, 0021).
Response to Arguments
The Applicant's arguments filed on November 04, 2025 have been fully considered, but they are not persuasive.
Applicant argues: ‘Thus, Arm specifically restricts the usage if a forwarding snoop to the case where an invalidating snoop must be sent to only one requestor’. (Rem, Pg. 9)
Response: This argument is incorrect.
The combination of Jalal, Arm, Tune wherein Arm, Pg. 1-24 recites, ‘Write-Invalidate protocol: A protocol in which an RN writing to a cache line that is shared in the system must invalidate all the shared copies before proceeding with the write’. This shows that the primary function of the invalidating snoop instruction is to enforce cache coherence by guaranteeing that all cached copies are marked as invalid. This prevents multiple nodes from having different, outdated versions of the same data.
With reference to Fig. 1, Para-0033 of the spec recites, ‘Another state can include a shared clean (SC) state…..Another state can include a shared dirty (SD) state’. Accordingly, Arm, Pg. 4-163 recites, ‘SC Shared Clean: Other caches might have a shared copy of the cache line….The cache line cannot be modified without invalidating any shared copies and obtaining unique ownership of the cache line’. And ‘SD Shared Dirty: Other caches might have a shared copy of the cache line….The cache line cannot be modified without invalidating any shared copies and obtaining unique ownership of the cache line’.
Arm, Pg. 4-171 recites, ‘The completion response to a MakeInvalid request ensures that all cached copies are invalidated. The request permits that any cached Dirty copies are discarded’. Here, the first coherent RN/Request node’s MakeInvalid call indicates its intent to invalidate its own copy, but the HN/Home is the central authority responsible for coordinating the global invalidation process to guarantee coherence across all (one or more) participants in the network.
Arm, Pg. 1-29 recites, ‘The HN/Home Includes a Point of Coherence (PoC) that manages coherency by snooping the required RN-Fs, consolidating the snoop responses for a transaction, and sending a single response to the requesting RN’. In essence, the ‘invalidating snoop instruction’ is a core mechanism of write-invalidate CHI protocols to maintain coherence.
The invalidation signal ensures that an older copy of the data is not used, forcing subsequent accesses, whether for a read or write, to obtain the new, correct value, which may involve forwarding from the owner. Therefore, the invalidation precedes the point where the new, valid data is propagated or accessed by others. Please see updated O/A.
More importantly, claim 1 recites, ‘sending, by the first coherent home node, to the one or more other coherent request nodes, except the current owner that was determined, an invalidating snoop instruction’. Therefore claim 1 recites that the invalidating snoop is sent to at least one other coherent RN (but not the owner). This limitation validates the Arm, SnpUniqueFwd transaction, Pg. 2-85, Pg. 4-228, as a relevant citation.
Lastly, Claim 1 also recites, ‘the forwarding snoop instruction establishes a direct cache transfer (DCT) between the first coherent request node and the current owner of the coherent cache line’. In the AMBA CHI protocol, the SnpUniqueFwd forward snoop is the transaction type that establishes DCT and hence Arm discloses the claim 1 limitation.
The claims are completely based on the AMBA CHI protocol, a well-known ARM developed standard for high-performance, cache-coherent communication in SoC designs, connecting processors and memory controllers efficiently.
That said, neither the claim nor the spec recite the specific name of ‘the forwarding snoop instruction’ that establishes a DCT. Neither the claim nor the spec recite the specific name of the ‘invalidating snoop instruction’ or recite a validation mechanism/transaction to check that the invalidation snoop instruction was successful, e.g. a snoop response like SnpResp from the other Request/RNs. In other words, establishing DCT between the ‘first coherent request node’ and the owner is claimed without any snoop response verification from the ‘one or more other coherent request nodes’. As recited, the ‘invalidating snoop instruction’ is a no-op. Hence the argument lacks technical validity and is not commensurate with the claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132