Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
With respect to claim 1, Applicant’s arguments are moot as a new reference has been used to teach newly added aspects of the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bains in view of DDR4 (Howard, Shamree, EE Times: DDR4 Not just a Speed Bump, 04/23/2013).
As to claim 1, Bains teaches a memory comprising:
an alert terminal (see fig. 2, disclosing sending an error indicator to a memory controller);
at least one alert source circuit configured to provide a first alert detection signal responsive to a first type of alert or a second alert detection signal responsive to a second type of alert (see Fig. 2 and Fig. 4, and paragraphs 0058-0059 disclosing error detection and the types of errors that can be detected), wherein the first type of alert is associated with a first condition detected with respect to the memory and the second type of alert is associated with a second condition detected with respect to the memory (see Fig. 4 and paragraphs 0058 and 0067, disclosing the different conditions/severity that can be detected with respect to the memory (uncorrectable, CENC, CEm, etc.) ; and
Bains does not explicitly teach an alert generator circuit configured to provide an alert signal to the alert terminal at an active level for a first duration responsive to the first alert detection signal or to provide the alert signal to the alert terminal at the active level for a second duration responsive to the second alert detection signal, wherein the first duration is different than the second duration.
However, Bains does teach the use of a single pin for sending error information (see paragraph 0067). And DDR4 teaches holding an alert signal (i.e. single pin) low for different durations to differentiate between two different type of errors (see page 1).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with DDR4’s methods because it is inexpensive and enables you do determine which kind of error you have when a single signal is used to alert a controller (see page 1).
As to claim 3, the references teach claim 1 as detailed above. Bain further teaches a clock terminal configured to receive a clock signal, wherein the alert generator circuit comprises a timing circuit configured to determine the first duration and the second duration based, in part, on a number of cycles of the clock signal (see paragraphs 110-112, disclosing bus clocks that are used in transmitting data to the controller).
As to claim 5, the references teach claim 1 as detailed above. Bains further teaches a memory array configured to store data bits and associated parity bits; and an error correction circuit configured to correct the data bits based on the associated parity bits (Fig 2, disclosing error checking and correcting memory and see paragraph 0063, disclosing checking and correcting errors using parity) and provide the first alert detection signal responsive to determining that the data bits include an error which cannot be corrected by the error correction circuit (see fig. 4, and associated text, disclosing detecting and reporting).
As to claim 7, the references teach claim 1 as detailed above. Bains further teaches the alert terminal is coupled via an alert bus to a controller (see Figs. 2, 3 and paragraph 067, disclosing a single or multiple pins to send error information to a memory controller).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bains and DDR4.
The references teach claim 1 as referenced above. They do not explicitly teach a mode register, wherein responsive to the first alert detection signal the mode register is configured to store information about the first type of alert.
However, the examiner takes official notice of buffers (that store data at least temporarily for transmission) and registers.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bain with the use of this storage because it allows you to hold the data for later reference or transmission.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bains and DDR4, in view of Ayyapureddi (US 20220051716 A1).
As to claim 6, the references teach claim 1 as detailed above. They do not explicitly teach a memory array comprising a plurality of word lines, each of which is associated with a respective row address and count value; and refresh control circuit configured to determine that one of the plurality of word lines is an aggressor row based on the respective count value and store the respective row address in an aggressor queue, wherein the refresh control circuit is configured to provide the second alert detection signal responsive to detecting an error with the respective count value and configured to provide a third alert detection signal responsive to the aggressor queue being full.
However, Ayyapureddi teaches this detection of an aggressor row based on a count and a signal indicating that as well an aggressor queue is full, as well as a signal indicating when an attack is occurring based on those signals (see paragraphs 0045-0069).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with the methods of Ayyapureddi because it enables frustration of attacks and prevent data decay in memories (see paragraphs 0009-0011).
Allowable Subject Matter
Claims 2, 8-12, 14, and 16 -21 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON B BRYAN whose telephone number is (571)270-7091. The examiner can normally be reached Mon-Fri, 8-5 First Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 5712720631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON B BRYAN/ Primary Examiner, Art Unit 2114
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