Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) filed on 06/21/2024 and 01/02/2025 has/have been considered by the Examiner and made of record in the application file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16, 17, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 16, 17, 19, and 20 there is a lack of antecedent basis in the claims for “the active level.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lasch (US 20120210109 A1).
As to claim 1, Lasch teaches an apparatus comprising:
an alert terminal (see paragraph 0020 and Fig. 2, disclosing that the reset output bus 205 can be output on a pin and coupled to an output function generator 206 and output pin 208);
at least one alert source circuit configured to provide a first alert detection signal responsive to a first type of alert or a second alert detection signal responsive to a second type of alert (see paragraphs 0013-0018, disclosing a reset reason status register 118 that issues different signals depending on the event that caused the processor to be reset); and
an alert generator circuit configured to provide an alert signal to the alert terminal at an active level for a first duration responsive to the first alert detection signal or to provide the alert signal to the alert terminal at the active level for a second duration responsive to the second alert detection signal (see paragraphs 0013-0020, disclosing reset output bus 205 that can be held low for different durations depending on the reason for the processor reset, and that this signal output on a pin and coupled to an output function generator 206 and output pin 208).
As to claim 4, Lasch teaches claim 1 as detailed above. Lasch further teaches a mode register, wherein responsive to the first alert detection signal the mode register is configured to store information about the first type of alert (see paragraphs 0013-0018, disclosing a reset reason status register 118).
As to claim 7, Lasch teaches claim 1 as detailed above. Lasch further teaches the alert terminal is coupled via an alert bus to a controller (see paragraph 0020, disclosing that pin 208 is connected to the CPU).
As to claim 15, Lasch teaches a method comprising:
detecting a first type of alert or a second type of alert (see paragraphs 0013-0018, disclosing a reset reason status register 118 that issues different signals depending on the event that caused the processor to be reset);
activating an alert signal at a first time responsive to the first type or the second type of alert;
deactivating the alert signal at a second time responsive to the first type of alert; and
deactivating the alert signal at a third time responsive to the second type of alert, wherein the third time is after the second time (see paragraphs 0013-0020, disclosing reset output bus 205 that can be held low for different durations (see example time frames) depending on the reason for the processor reset, and that this signal output on a pin and coupled to an output function generator 206 and output pin 208).
Claim(s) 5, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bains (US 20210224155 A1).
As to claim 5, Bains teaches an apparatus comprising:
an alert terminal (see fig. 2, disclosing sending an error indicator to a memory controller);
at least one alert source circuit configured to provide a first alert detection signal responsive to a first type of alert or a second alert detection signal responsive to a second type of alert (see Fig. 2 and Fig. 4, disclosing error detection and the types of errors that can be detected); and
an alert generator circuit configured to provide an alert signal to the alert terminal at an active level for a first duration responsive to the first alert detection signal or to provide the alert signal to the alert terminal at the active level for a second duration responsive to the second alert detection signal (see paragraph 0058, Fig. 4, and 0067-0073, disclosing signals sent along the error indication 282 depending on the type of error detected; the examiner interprets t active bits are asserted for some duration; examiner notes that nothing in the claims indicates the durations must be different lengths of time).
a memory array configured to store data bits and associated parity bits; and an error correction circuit configured to correct the data bits based on the associated parity bits (Fig 2, disclosing error checking and correcting memory and see paragraph 0063, disclosing checking and correcting errors using parity) and provide the first alert detection signal responsive to determining that the data bits include an error which cannot be corrected by the error correction circuit (see fig. 4, and associated text, disclosing detecting and reporting).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lasch.
As to claim 3, Lasch teaches claim 1 as detailed above. Lasch further teaches the alert generator circuit comprises a timing circuit configured to determine the first duration and the second duration based, in part, on a number of cycles of the clock signal (see paragraphs 0013-0020, disclosing reset output bus 205 that can be held low for different numbers of clock cycles depending on the reason for the processor reset).
Lasch does not explicitly teach receiving the clock signals.
However, Lasch teaches clock signals (see paragraph 0019) and asserting signals at particular counts of clock cycles (see paragraphs 0013-0020). It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lasch with receiving the signals because they are needed to count the clock cycles to assert the signal for the proper amount of time.
As to claim 18, Lasch teaches claim 15 as detailed above. Lasch further teaches and counting a number of clock cycles beginning at the first time deactivating the alert signal when the number of clock cycles reaches a first value responsive to the first type of alert; and deactivating the alert signal when the number of clock cycles reaches a second value responsive to the second type of alert (see paragraphs 0013-0020, disclosing reset output bus 205 that can be held low for different durations depending on the reason for the processor reset).
Lasch does not explicitly teach receiving the clock signals.
However, Lasch teaches clock signals (see paragraph 0019) and asserting signals at particular counts of clock cycles (see paragraphs 0013-0020). It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lasch with receiving the signals because they are needed to count the clock cycles to assert the signal for the proper amount of time.
As to claim 19, Lasch teaches claim 15 as detailed above. Lasch does not explicitly teach detecting the alert signal at the active level; counting a time that the alert signal is at the active level; and determining the type of alert based on the time.
However, Lasch teaches decoding/reading the encoded signals (see paragraph 0013).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lasch with decoding by reversing the encoding process by counting the time that an alert signal is active because it enables one to determine the encoded reason for the reset.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bain, in view of Ayyapureddi (US 20220051716 A1).
As to claim 6, Bains teaches an apparatus comprising:
an alert terminal (see fig. 2, disclosing sending an error indicator to a memory controller);
at least one alert source circuit configured to provide a first alert detection signal responsive to a first type of alert or a second alert detection signal responsive to a second type of alert (see Fig. 2 and Fig. 4, disclosing error detection and the types of errors that can be detected); and
an alert generator circuit configured to provide an alert signal to the alert terminal at an active level for a first duration responsive to the first alert detection signal or to provide the alert signal to the alert terminal at the active level for a second duration responsive to the second alert detection signal (see paragraph 0058, Fig. 4, and 0067-0073, disclosing signals sent along the error indication 282 depending on the type of error detected; the examiner interprets t active bits are asserted for some duration; examiner notes that nothing in the claims indicates the durations must be different lengths of time).
Bains does not explicitly teach a memory array comprising a plurality of word lines, each of which is associated with a respective row address and count value; and refresh control circuit configured to determine that one of the plurality of word lines is an aggressor row based on the respective count value and store the respective row address in an aggressor queue, wherein the refresh control circuit is configured to provide the second alert detection signal responsive to detecting an error with the respective count value and configured to provide a third alert detection signal responsive to the aggressor queue being full.
However Ayyapureddi teaches this detection of an aggressor row based on a count and a signal indicating that as well an aggressor queue is full, as well as a signal indicating when an attack is occurring based on those signals (see paragraphs 0045-0069).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with the methods of Ayyapureddi because it enables frustration of attacks and prevent data decay in memories (see paragraphs 0009-0011).
Claim(s) 8-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bains in view of Lasch.
As to claim 8, a system comprising:
an alert bus (See Fig. 2, error indication 282);
a memory (see Fig. 2, disclosing memory 230) configured to provide an alert signal along the alert bus at an active level for a period of time (see paragraph 0058, Fig. 4, and 0067-0073, disclosing signals sent along the error indication 282); and
Bains does not explicitly teach a controller configured to determine a duration of the period of time and determine a type of alert based on the duration of the alert signal.
However, Bains teaches sending indicators on a single pin (see Fig. 4 and associated text). And Lasch teaches that information can be encoded and decodedas different numbers of clock cycles of signal assertions (see paragraphs 0013-0020); the examiner interprets decoding by determine the time or clock cycles is obvious as it reverses the encoding).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with the encoding of Lasch because it enables sending encoded information regarding problems on a single pin (see paragraph 0017) such as that described in Bains which allows for using fewer pins and conductors thus saving routing space and cost.
As to claim 9, Bains teaches the system of claim 8. Bains further teaches a clock bus, wherein the controller further comprises a clock generator circuit configured to provide a clock signal along the clock bus (see paragraph 0027; the examiner interprets the clock bus corresponds to the conductors carrying the clock signals in the clock circuitry).
Bains does not explicitly teach that the memory is configured to provide the alert signal at the active level for a number of cycles of the clock signal wherein the number is based on the type of alert.
However, Bains teaches sending indicators on a single pin (see Fig. 4 and associated text). And Lasch teaches that information can be encoded as different numbers of clock cycles of signal assertions (see paragraphs 0013-0020).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with the encoding of Lasch because it enables sending encoded information regarding problems on a single pin (see paragraph 0017) such as that described in Bains which allows for using fewer pins and conductors thus saving routing space and cost.
As to claim 10, Bains and Lasch teach the system of claim 9 as detailed above. Bains does not explicitly teach the controller includes an alert logic circuit configured to count a number of the cycles of the clock signal starting when the alert signal changes to the active level and ending when the alert signal changes to an inactive level.
However, Lasch teaches that information can be encoded as different numbers of clock cycles of signal assertions (held low for a certain number of clock cycles (see paragraphs 0013-0020) and that such signals can be decoded or read to determine what they indicate. It is obvious to count the clock cycles because that decodes/ reads to determine what they indicate.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with the encoding/decoding of Lasch because it enables sending encoded information regarding problems on a single pin (see paragraph 0017) such as that described in Bains which allows for using fewer pins and conductors thus saving routing space and cost.
As to claim 11, Bains and Lasch teach the system of claim 8 as detailed above. Bains does not explicitly teach the controller includes an alert logic circuit configured to determine a first type of alert if the period of time is between a first value and a second value, determine a second type of alert if the period of time is between a third value and a fourth value, wherein the second value is longer than the first value, the third value is longer than the second value, and the fourth value is longer than the third value However, Lasch teaches that information can be encoded and decoded as different numbers of clock cycles of signal assertions (see paragraphs 0013-0020, disclosing times 0-100 ms, 100-200ms).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Bains with the encoding/decoding of Lasch because it enables sending encoded information regarding problems on a single pin (see paragraph 0017) such as that described in Bains which allows for using fewer pins and conductors thus saving routing space and cost.
As to claim 12, Bains and Lasch teach the system of claim 11 as detailed above. Lasch further teaches the alert logic circuit is further configured to determine a third type of alert if the alert signal remains at the active level for longer than a fifth value, wherein the fifth value is longer than the fourth value (see paragraphs 0013-0020, disclosing times 0-100 ms, 100-200ms; this is an obvious iteration of the scheme in Lasch, if the value 300ms is chosen to encode information, it is longer than 299ms and 299ms is longer than the 200ms).
As to claim 14, Bains and Lasch teach the system of claim 8 as detailed above. Bains further teaches the memory includes a mode register, and wherein the controller configured to perform a mode register read operation on the mode register responsive to a first type of alert signal (see paragraph 0018, disclosing reading corrected data from memory when an error has been indicated to a memory controller; see paragraph 0030, disclosing memory banks (registers)).
Allowable Subject Matter
Claims 2 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16, 17, and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON B BRYAN whose telephone number is (571)270-7091. The examiner can normally be reached Mon-Fri, 8-5 First Friday off.
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/JASON B BRYAN/Primary Examiner, Art Unit 2114