Prosecution Insights
Last updated: September 17, 2026
Application No. 18/743,314

PULSE COUNTER

Final Rejection §102§103§112
Filed
Jun 14, 2024
Priority
Jun 22, 2023 — FR 2306509
Examiner
BHATIA, AMIT R
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Dolphin Design
OA Round
2 (Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
22 granted / 31 resolved
+3.0% vs TC avg
Strong +19% interview lift
Without
With
+19.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
15 currently pending
Career history
50
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
40.9%
+0.9% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
23.3%
-16.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 31 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Response to Arguments Applicant’s arguments, see I. Drawing Objection (page 5), filed July 7, 2026, with respect to “AFE” and “IAF” as not being mentioned in the description have been fully considered and are persuasive. The objection has been withdrawn. Applicant’s arguments, see I. Drawing Objection (page 5), filed July 7, 2026, with respect to “NRST” as not being mentioned in the description has been fully considered and are not persuasive. The examiner respectfully disagrees that the abbreviation does not appear in the drawing. The abbreviation “NRST” is shown in Fig. 2, at the output of inverter 207. Additionally, the abbreviations “DO_NRSTA” and “CA_NRST” are not defined (i.e. each letter of the abbreviation) in the specification. Applicant’s arguments, see II. Claim Objections (page 5), filed July 7, 2026, with respect to claims 2-5, 7-11, and 13-15 have been fully considered and are persuasive. The objection of claims 2-5, 7-11, and 13-15 has been withdrawn. Applicant’s arguments, see III. Rejections of Claims 2-5 and 9-11 Under 35 U.S.C. §112 (pages 6-7), filed July 7, 2026, with respect to claims 9-10 (§112(a)) have been fully considered and are persuasive. The rejections of claims 9-10, for §112(a), have been withdrawn. Applicant’s arguments, see III. Rejections of Claims 2-5 and 9-11 Under 35 U.S.C. §112 (page 6), filed July 7, 2026, with respect to claims 3-5 and 10-11 (§112(b)) have been fully considered and are persuasive. The rejections of claims 3-5, for §112(b), have been withdrawn. Applicant’s arguments, see IV. Rejections of Claims 1-15 Under 35 U.S.C. §102 and §103 (pages 7-10), filed July 7, 2026, with respect to the rejections of claims 1-15 have been fully considered and are not persuasive. Applicant argues, “Yang neither discloses nor suggests the use of a flip-flop to replace the memory”. Examiner respectfully disagrees. The rejection is not based on replacing a memory with a flip-flop. The rejection of Yang does not rely on any memory element, nor does the claim recite a memory replacement as argued. The rejection relies on the register element which corresponds to the claimed flip-flop. The examiner is interpreting the register as a flip-flop, as evidenced by Beginner's Guide to the Shift Register in Digital Electronics (https://www.build-electronic-circuits.com/shift-register/). Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: NRST, DO_NRSTA, CA_NRST. The abbreviation and functionality are not defined in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Claim 10 (line 2) recites "signal supplied by the first circuit". It is unclear if this first circuit is the circuit in claim 6 or the circuit in claim 1. Thus, this is indefinite under 112(b). Claim Rejections - 35 USC § 102 Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-6, and 9-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by YANG MINHAO ET AL: "Design of an Always-On Deep Neural Network-Based 1-micro-W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 54, no. 6, 1 June 2019 (2019-06-01), pages 1764-1777, XP011726809, ISSN: 0018-9200, DOI: 10.1109/JSSC. 2019.2894360; hereinafter Yang. Regarding Claim 1, Yang discloses a pulse counter (Section III.E. and Fig. 16: the "binarized MLP" comprises counters - "Ripple counters") comprising an asynchronous counter (Section III.E.: "Nine-bit counter," "interface between the asynchronous feature extraction front-end and the synchronous inference computing") and a circuit configured to trigger a read operation of a value of said asynchronous counter (Section III.E.: "the control signals for the counters[...] are generated by the controller block"; Fig. 16: the "controller block" produces selection signals "sel0_cnt" and "sel1_cnt" to read the values of the "Nine-bit counters"), said circuit being synchronized by a clock signal (Fig. 16: the "controller block" is controlled by a clock signal "clk"); and a flip-flop (Fig. 16: the presence of "reg" registers suggests the use of flip-flops; as evidenced by the Beginner's Guide to the Shift Register in Digital Electronics [https://www.build-electronic-circuits.com/shift-register/]) adapted to receive said value from said asynchronous counter during a reading phase (the registers serving to temporarily store the values of the "Nine-bit counters"). Regarding Claim 3, 4, and 5, Yang discloses the pulse counter according to claim 1, in which the reading phase is triggered by an edge of a first synchronization signal, the reading phase is stopped by an edge of a second synchronization signal, and wherein said edge of the second synchronization signal further triggers the resetting of said value of said asynchronous counter (Fig. 16: the reading of counter values when signals "sel0_cnt" and "sel1_cnt" are received, and the resetting when a signal "rst_cnt" is received, are implicitly performed on the edges of the clock signal "clk"). Regarding Claim 6, Yang discloses a circuit (Section II and Fig. 3) suitable for recognizing words from an audio file comprising the pulse counter (see claim 1 rejection above) according to claim 1. Regarding Claim 9, Yang discloses the circuit according to claim 6, further comprising a first circuit (Abstract, Fig. 3; analog signal processing) adapted to implement an acoustic characteristic extraction function (AFE). Regarding Claim 10, as best understood, Yang discloses the circuit according to claim 6, further comprising a second circuit (Section II; Fig. 3; integrate-and-fire/IAF) adapted to integrate a signal supplied by the first circuit. Regarding Claim 11, Yang discloses the circuit according to claim 6, further comprising a third circuit (Abstract, Sections II & III.E., Fig. 3 & 16; digital binarized MLP comprising a digital deep neural network/DNN) configured to implement digital processing of the signal supplied by said pulse counter (clk). Regarding Claim 12, Yang discloses a device (Abstract) adapted to process an audio file comprising the circuit (see the rejection of claim 6 above) according to claim 6. Regarding Claim 13, Yang discloses the device according to claim 12, further comprising a microphone (Abstract). Regarding Claim 14, Yang discloses the device according to claim 12, further comprising a neural network (Abstract; digital deep neural network/DNN). Regarding Claim 15, Yang discloses the device according to claims 12, adapted to detect the human voice (Abstract; voice activity detector/VAD). Claim Rejections - 35 USC § 103 Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang. Regarding Claims 7 and 8, Yang discloses the claimed invention according to claim 6 except for having a clock frequency between 30 and 40 kHz; in which the clock frequency is equal to 32.728 kHz. It would have been an obvious matter of design choice to specify the value of the clock frequency since the Applicant has not disclosed that a specific clock frequency solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with any clock frequency provided. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Amit R Bhatia/Examiner, Art Unit 2836 /REGIS J BETSCH/SPE, Art Unit 2836
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Prosecution Timeline

Jun 14, 2024
Application Filed
Apr 09, 2026
Non-Final Rejection mailed — §102, §103, §112
Jul 07, 2026
Response Filed
Sep 11, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+19.0%)
2y 5m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 31 resolved cases by this examiner. Grant probability derived from career allowance rate.

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