DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-6 is/are rejected under 35 U.S.C. 102(a)(1) as being (a)(1) by Roe et al. (US 11239698).
PNG
media_image1.png
810
664
media_image1.png
Greyscale
PNG
media_image2.png
647
1044
media_image2.png
Greyscale
PNG
media_image3.png
563
768
media_image3.png
Greyscale
With respect to claim 1, figures 2-8 of Roe et al. (US 11239698) discloses a receiver comprising: an antenna (20 and/or 18) exposed to a magnetic field with a carrier frequency in the RF frequency area (see column 5 lines 49-51 disclosing transfer of information is over wireless radio frequency); and a rectifier stage (fig. 4) of a receiver IC built to extract an internal supply voltage (76) for processing of data with the receiver IC of the receiver; wherein the antenna (18) is built to receive an antenna signal and connected to a tuning circuit (79-88) built to provide a first received signal (Detune P) at a first input pin of the rectifier stage (61) and a second received signal (Detune N) at a second input pin of the rectifier stage (61); and which rectifier stage comprises: a first switch (inside 78 (ie. 104P or 102P)) connected between the first input pin and the internal supply voltage at an output pin of the rectifier stage (74); a switch-on stage (84) built to provide a first switch-on signal (Gate Enable P) to switch the first switch into its connecting status, if the first received signal at the first input pin exceeds the internal supply voltage (Below 2V); a second switch (inside 78 (i.e. 104P or 102P)) connected between the second input pin and the internal supply voltage at the output pin and the switch-on stage is built to provide a second switch-on signal (gate Enable N) to switch the second switch into its connecting status, if the second received signal at the second input pin exceeds the internal supply voltage (below 0v); and a switch-off stage built to provide a first switch-off signal to switch the first switch into its disconnecting status (disabled P), if a variable and steered first switch-off time occurred, and to switch the second switch into its disconnecting status (Disabled N), if a variable and steered second switch-off time occurred, wherein the switch-off stage comprises a control stage (84 controls switch on and switch off stage) configured to perform at least one of: a first determination of whether a falling edge of the first receiver signal or the first-switch off signal occurs first (by controlling the on and off stage the control signal determines which occurs first the falling edge of the first receiver or the first switch off signal); and a second determination of whether a falling edge of the second receiver signal or a second switch-off signal occurs first (based on the controller, the controller decides which occurs first), wherein the control stage is built to steer at least one of a first switch-off time and a second switch-off time to keep falling edges from the first and second determinations as close together as possible (As close together as possible occurs as possible is dependent on the functioning of the circuit). (With respect to the first determination and second determination either one is applicable as they are claimed in the alternative.) (As the control circuit stage controls the switch, it has the ability to determine if the switch off signal or the falling of the receiver signal occurs first merely be functionality of the circuit).
With respect to claim 3, Roe et al. (US 11239698) discloses the receiver according to claim 2, wherein the control stage is built with each determination to stepwise increase or decrease the first switch-off time and/or second switch-off time. (col. 10 lines 49-68 “. The steps may sequence in that order, with the exception being that WaitBelowZero can also transition to WaitBlanking if the 2V level is crossed.”)
With respect to claim 4, Roe et al. (US 11239698) discloses the receiver according to claim 1, wherein the first switch and the second switch are each realized by a PMOS transistor (104Ps or 102Ps) with their drain contacts as output pins of the first switch (104Ps or 102Ps) and the second switch (104Ps or 102Ps) connected to the internal supply voltage and with the source contact as first input pin of the first switch to receive the first received signal and with the source contact as second input pin of the second switch to receive the second received signal. (Here, depending on the configuration of the circuit, the multiple PMOS FETs or NMOS FETs would meet the functional language according to the configuration of the circuit as both NMOS and PMOS configurations are within the scope of the device.)
With respect to claim 5, Roe et al. (US 11239698) discloses the receiver according to claim 4, wherein a driver stage is connected to receive the switch-on signal and the switch-off signal and is connected to the gate contacts of the PMOS transistors (104Ps or 102Ps) to operate the first switch as PMOS diode (105Ps or 103Ps) during switching on of the rectifier stage causing a rather large voltage difference between the first received signal and the internal supply voltage before switching the first switch into its connecting status and to operate the second switch as PMOS diode (105Ps or 103Ps) during switching on of the rectifier stage causing a rather large voltage difference between the second received signal and the internal supply voltage before switching the second switch into its connecting status.
With respect to claim 6, Roe et al. (US 11239698) discloses receiver according to claim 4, wherein the first switch and the second switch each comprise a bulk control stage (stage controlling bulk of transistors via backgate) with cross-coupled (col. 1 lines 48-52 “Some embodiments described herein include an efficient voltage rectification circuit that employs cross coupled PMOS high-side (or NMOS low-side) field effect transistors (FETs) and actively driven low-side NMOS (or high-side PMOS) FETs.) PMOS switches (105P or 103P) to connect the bulk of the PMOS transistors either to the source contact or the drain contact.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roe (US 11239698) in view of Mainsah et al. (US 20210370045).
With respect to claim 7, Roe discloses the receiver according to claim 1, wherein the antenna and tuning circuit are built to receive the antenna signal with the carrier frequency of the system but fails to disclose wherein the defined NFC resonance frequency of 13,56 MHz.
Mainsah et al. discloses that an LVAD can be operated at a defined NFC frequency (see [0037]- [0038] “ In some aspects, the acoustic biomarker detection system 100 can be used to record and analyze precordial sounds (e.g., sounds through the chest wall overlaying the heart) from a patient 102 having a left ventricle assist device (LVAD) 104 that is surgically implanted and assists functions of heart 106. Examples of LVAD 104 can include a HEARTMATE3™ (HM3) LVAD, a HEARTMATE II™ LVAD, a HEARTWARE HVAD™, or any other type of surgically implanted mechanical heart pump.” “In some examples, audio recording device 108 can include a digital stethoscope. In other embodiments, audio recording device 108 can include any electronic device that can be configured to record audio such as a smartphone, tablet, laptop, desktop, smartwatch, etc. Audio recording device 108 may be connected to transducer 110 via a wired or a wireless transmission medium (e.g., BLUETOOTH™, Wi-Fi, Infrared, NFC, etc.).”).
It would have been obvious at the time the invention was made to operate the device in Roe at NFC frequency (normally defined at 13.56 MHz) as it is known to connect medical transducers via a wireless transmission medium such as NFC.
Response to Arguments
Applicant's arguments filed 3/2/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument Roe does not disclose a switch on stage that provides a first switch on signal and a second switch on signal based on an internal supply voltage crossing the received antenna signal, the Examiner disagrees. Because the internal voltage is based on the received antenna signal, the associated crossing of the voltage of the internal voltage convey information about the antenna. “FIG. 4 is a block diagram of circuitry configured to provide a DC rectified voltage 74 which is generated from a power signal inductively transmitted from the e-coil 20 to the i-coil 18. This induces in the i-coil 18 an AC coil voltage 76.” Hence Roe discloses a switch on stage (the enable stages) that provides a first switch on stage and second switch on stage based on an internal supply voltage crossing (because the internal supply voltage 76 is based on the antenna and the crossings of the internal voltage determine the switch stages on). The first signal is a signal based on the antenna.
With respect to the switch off stage, this is interpreted as being if the enable stage is not enabled.
With respect to applicant’s argument, to keep falling edges as close together as possible, the Examiner points out that although it is not expressly clear, “as close together as possible” is not indefinite, but not given patentable weight, because it as close together “as possible” would be within the possibility of the operation of the circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849
Prosecution Insights