Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 11, 14, 21, and 26 are rejected under 35 U.S.C. 102a1 as being anticipated by Pan (US Publication No. 20190190655).
Regarding claim 1, Pan teaches:
A method comprising: obtaining a first set of payload bits having a first priority and a second set of payload bits having a second priority lower than the first priority; (see para. 158: CQI bits may be grouped into MSB and LSB groups. For example, multiple CQI control messages 1302 may be sorted, at 1304, based on priority… Priority sorting may be performed to assign the MSB bit group a higher priority and the LSB bit group a lower priority.)
encoding an input bit sequence using an error correction code to produce a codeword, the input bit sequence comprising the first set of payload bits and the second set of payload bits in bit positions within a combined payload of the input bit sequence, (see para. 158: At 1312, priority mapping may map the CQI MSB group 1306B to a higher priority bit channel group of a polar encoder and may map the CQI LSB group 1306A to a lower priority bit channel group of the polar encoder. When priority mapping is finished, the polar encoder may encode, at 1314, the CQI bits for both the MSB and LSB bit groups and the encoded CQI bits for MSB and LSB jointly. The jointly encoded CQI bits for multiple CQIs… may include more protection for a MSB bit group and less protection for a LSB bit group for the same control information type.)
wherein at least one bit position of the first set of payload bits has a greater error protection than second bit positions of the second set of payload bits within the combined payload; and outputting the codeword. (see para. 158: At 1312, priority mapping may map the CQI MSB group 1306B to a higher priority bit channel group of a polar encoder and may map the CQI LSB group 1306A to a lower priority bit channel group of the polar encoder. When priority mapping is finished, the polar encoder may encode, at 1314, the CQI bits for both the MSB and LSB bit groups and the encoded CQI bits for MSB and LSB jointly. The jointly encoded CQI bits for multiple CQIs… may include more protection for a MSB bit group and less protection for a LSB bit group for the same control information type.) The codeword is considered to be output from the polar encoder.
Regarding claim 4, Pan teaches the method of claim 1. Pan further teaches:
further comprising: encoding the first set of payload bits using an outer code to produce a first set of encoded payload bits, wherein the input bit sequence comprises the first set of encoded payload bits and the second set of payload bits in the bit positions within the combined payload. (see, for example, fig. 13: CRC 1310 calculated from CQI MSB 1306B and is input to polar encoder. The CRC is considered to be the outer code, and it is clear that the first set of encoded payload bits (CQI MSB 1306B + CRC 1310) and second set of payload bits (CQI LSB 1306A) are input to the polar encoder as an input bit sequence.
Claims 11, 21, and 26 correspond to claim 1, and are rejected accordingly.
Claim 14 corresponds to claim 4 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 12, 24, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Cirkic (US Patent No. 11387849).
Regarding claim 2, Pan teaches the method of claim 1. Pan further teaches:
wherein the error correction code is a Polar code, the first set of payload bits is included in first bit positions.., and the second set of payload bits is included in the second bit positions…. (see para. 158: At 1312, priority mapping may map the CQI MSB group 1306B to a higher priority bit channel group of a polar encoder and may map the CQI LSB group 1306A to a lower priority bit channel group of the polar encoder. When priority mapping is finished, the polar encoder may encode, at 1314, the CQI bits for both the MSB and LSB bit groups and the encoded CQI bits for MSB and LSB jointly. The jointly encoded CQI bits for multiple CQIs… may include more protection for a MSB bit group and less protection for a LSB bit group for the same control information type.)
However, Pan does not explicitly teach:
the first set of payload bits is included in first bit positions with smaller bit indices of the input bit sequence, and the second set of payload bits is included in the second bit positions with larger bit indices of the input bit sequence.
In the analogous art of polar codes, Cirkic provides motivation to modify Pan’s invention such that:
the first set of payload bits [including more error protection] is included in first bit positions with smaller bit indices of the input bit sequence, and the second set of payload bits [including less error protection] is included in the second bit positions with larger bit indices of the input bit sequence. (see col. 1, lines 31-37: One issue with existing mechanisms for decoding polar codes lies in the successive decoding (SD) procedure which follows the bit-order of the polar codes. Decoding of polar codes is prone to error propagation and hence, an error made early in the successive decoding procedure will not be corrected, but will instead propagate all the way to the end of the decoding. This will result in a decoding error.) Here, Cirkic provides clear motivation to include strong error-protected bits early in the bit-order, so that it is less likely for an error to propagate throughout the entire successive decoding procedure, resulting in a decoding error.
It would have been obvious to one of ordinary skill in the art having the teachings of Pan and Cirkic before them, before the effectively filed date of the instant application, to incorporate including the more protected bits earlier in the bit order than the less protected bits (as motivated by the teachings of Cirkic), into the polar encoding system of Pan, such that the more error protected MSBs are earlier in the bit order than the less error protected LSBs, to allow for benefits such as higher chance of avoiding early errors during successive decoding (Cirkic, col. 1, lines 31-37). Claims 12, 24, and 29 correspond to claim 2, and are rejected accordingly.
Claims 3, 13, 25, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Shen (US Publication No. 20060156169).
Regarding claim 3, Pan teaches the method of claim 1. Pan further teaches:
wherein the error correction code is a Low Density Parity Check (LDPC) code, the first set of payload bits is included in first bit positions with [higher error protection]… , and the second set of payload bits is included in the second bit positions with [lower error protection]… (see para. 111: Channel coding schemes may be switched (e. g., determined) based on a payload size of a control channel. For example, a first coding scheme (e.g., such as Polar code) may be used when a transmitted payload size of a control channel is larger than a first predefined payload size. A second coding scheme (e.g., such as Reed-Muller code) may be used when a transmitted payload size of a control channel is less than or equal to the first predefined payload size. When the transmitted payload size of a control channel is greater than a second predefined payload size a third coding scheme (e.g., such as LDPC) may be used. And see para. 158: The jointly encoded CQI bits for multiple CQIs… may include more protection for a MSB bit group and less protection for a LSB bit group for the same control information type.) It would be obvious to one of ordinary skill in the art when implementing a LDPC code for two sets of groups, one requiring more error protection, and one requiring less error protection, that the group requiring more would be included in bit positions with higher variable node degrees of the LDPC code, and the group requiring less would be included in bit positions with lower variable node degrees of the LDPC code. This is because it is well known in the art of error correction that coded bits associated with higher variable node degrees have higher coding (error protection) strength, and bits associated with lower variable node degrees have lower coding (error protection) strength. Regardless, a reference is provided for the sake of clarity of the record.
In the analogous art of error correcting codes, Shen teaches:
first bit positions with higher variable node degree of the LDPC code [have better error protection], and second bit positions with lower variable node degree of the LDPC code [have worse error protection]. (see para. 282: Another possible approach seeks to correspond those LDPC coded bits of the LDPC block that have higher coding strength (i.e., higher bit degree thereby indicating relatively more edges connected between those bit nodes and corresponding check nodes) to the MSBs of an n-bit label that is to be symbol mapped according to a modulation (having a constellation shape and corresponding mapping). This approach also seeks to correspond those LDPC coded bits of the LDPC block that have lower coding strength (i.e., lower bit degree thereby indicating relatively fewer edges connected between those bit nodes and corresponding check nodes) to the LSBs of an n-bit label that is to be symbol mapped according to a modulation (having a constellation shape and corresponding mapping).) It would have been obvious to one of ordinary skill in the art having the teachings of Pan and Shen before them, before the effectively filed date of the instant application, to incorporate associating bits needing more error protection with a higher bit degree and associating bits needing less error protection with a lower bit degree (as is well known in the art, but made clear from Shen), into the LDPC coding system of Pan, to allow for benefits such as allowing for modular error protection and coding strength in an LDPC code (Shen para. 282).
Claims 13, 25, and 30 correspond to claim 3, and are rejected accordingly.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Zhang (US Patent No. 9706599).
Regarding claim 5, Pan teaches the method of claim 1.
In the analogous art of coded transmission, Zhang teaches:
including in the combined payload an indication of how many bits are in the first set of bits and how many bits are in the second set of bits. (see col. 16, lines 53-56: the signaling information included in the preamble indicates a size, duration or length of only a portion of the data payload that is to be transmitted immediately after the preamble. And see abstract: The midamble includes an indication of at least one characteristic of the data payload. Such as an indication of a size of the second portion of the data payload, or whether or not the data payload includes one or more other portions in addition to the first and second portions. And see fig. 3.)
It would have been obvious to one of ordinary skill in the art having the teachings of Pan and Zhang before them, before the effectively filed date of the instant application, to incorporate preamble/midambles including the size of next payload into the multi-payload polar encoded system of Pan, to allow for benefits such as communication to the receiver allows it to properly and easily access the data contained in a transmission (Zhang, col. 8, lines 5-8).
Claim 15 corresponds to claim 5 and is rejected accordingly.
Claims 22 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Yang (US Publication No. 20200026475).
Regarding claim 22, Pan teaches the method of claim 21. In the analogous art of bit prioritization, Yang teaches:
terminating the decoding upon successfully decoding the first set of payload bits, without decoding the second set of payload bits. (see para. 49: In the above-mentioned embodiment, if the decoder 134 of the flash memory controller 110 can successfully decode the data by only using the MSBs, the LSBs may not be used for the decoding operations, or the flash memory controller 110 can notify the flash memory module 120 to stop to transfer the LSBs.)
It would have been obvious to one of ordinary skill in the art having the teachings of Pan and Yang before them, before the effectively filed date of the instant application, to early stoppage of decoding in response to success on just the MSB bits (taught by Yang) into the polar encoding system of Pan, to allow for benefits such as efficiency (see Yang, para. 41).
Claim 27 corresponds to claim 22 and is rejected accordingly.
Claims 23 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Xu (US Publication No. 201800343593).
Regarding claim 23, Pan teaches the method of claim 21. Pan further teaches wherein:
further comprising: performing a cyclic redundancy check (CRC) on the first set of payload bits; and transmitting a retransmission request for the codeword upon failure of the CRC. (see para. 161: A CRC or a short CRC may be attached to control MSB and LSB bit groups separately. For example, at 1508, a first CRC 1510 may be attached to control LSB and a second CRC 1512 may be attached to the control MSB group 1506B. In this case, a gNB or receiver may perform error checking for MSB and LSB separately.)
It is generally well known in the art that in response to a CRC check failing for a portion of a message, the whole message is requested to be retransmit. Regardless, a reference is provided for the sake of clarity of the record.
Xu teaches:
performing a cyclic redundancy check (CRC) on the first set of payload bits; and transmitting a retransmission request for the codeword upon failure of the CRC (see para. 59 and fig. 6B: A TB may be segmented into several blocks and each block may be encoded as one codeword . As presented above , a CRC may be attached for each block and may be used for early termination . In this case , only a single bit may be used for acknowledgement / no - acknowledgement ( ACK / NACK ) . That is, a NACK may be obtained by a transmitter for an entire block even if only one sub - block was not decoded correctly at the receiver)
One of ordinary skill in the art, implementing the system disclosed by Pan would find it obvious to use the routine, well known method of requesting a retransmission of a whole message in response to any CRC corresponding to a subsection of the message failing (as shown by Xu).
Claim 28 corresponds to claim 23 and is rejected accordingly.
Conclusion
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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