Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 06/14/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawing
The drawings filed on 06/14/2024 are acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/14/2024 is in compliance
with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Claims 1-12 are pending and are in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2004/0174150 A1), hereinafter ‘Zhang, in view of Shao et al. (US 2015/0198635 A1).
In re to claim 1, Zhang disclose a regulator (i.e. fig. 1) for regulating an input voltage (i.e. VPP1) to output an output voltage (i.e. Vreg, see pars. [0034-0035]), the regulator comprising: a voltage divider circuit (i.e. 213) configured to output, as a feedback voltage (i.e. Vdiv), a voltage generated by dividing the output voltage (i.e. Vreg); an operational amplifier (i.e. 201)configured to compare the feedback voltage (i.e. Vdiv) with a reference voltage (i.e. Vref); a drive transistor (i.e. 202) being disposed between a node at the input voltage (i.e. the node between the input VPP1 and the transistor 202) and a node at the output voltage (i.e. the node Vreg and 202, fig. 1, see pars. [0034-0035]), configured to be controlled based on an output of the operational amplifier (i.e. output of 201), wherein the voltage divider circuit (i.e. 213) includes a plurality of resistors (i.e. resistors 203-208), and a plurality of switches (i.e. 209-212, see par. [0036]), each switch of the plurality of switches being disposed in parallel with a corresponding resistor of the plurality of resistors (i.e. switches 209-212 are connected in parallel to resistors of 204-29, see fig. 1). Except, Zhang fail to explicitly disclose that a logic circuit configured to output an adjustment signal for the output voltage; and an output voltage adjustment circuit configured to adjust the output voltage based on the adjustment signal, the output voltage adjustment circuit is configured to output, to the plurality of switches, a control signal in accordance with the adjustment signal, and the output voltage is supplied as a power supply voltage to the output voltage adjustment circuit. Whereas, Shao teach that a logic circuit (i.e. the ADC 206 can include logic circuitry, see par. 0040]) configured to output an adjustment signal (i.e. n, fig. 2, see para. [0040]) for the output voltage (i.e. Vout, see fig. 2); and an output voltage adjustment circuit (i.e. 112A, fig. 2) configured to adjust the output voltage based on the adjustment signal (i.e. see pars. [0040-0043]); the output voltage adjustment circuit is configured to output, to the plurality of switches, a control signal in accordance with the adjustment signal (i.e. the adjustment signal n, see par. [0040]), and the output voltage (i.e. VOUT) is supplied as a power supply voltage to the output voltage adjustment circuit (i.e. 112, fig. 2, see pars. [0040-0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the regulator of Zhang by incorporating the logic circuit and the voltage adjustment circuit of Shao to enhance the output voltage detection efficiency in adjusting the required output voltage by the load.
In re to claim 3, Zhang disclose the regulator (i.e. fig. 1) according to claim 1. Except, Zhang fail to explicitly disclose that wherein the logic circuit includes an initial value register, and is configured to, after a power-on reset, output the adjustment signal based on an initial value of an adjustment value for the output voltage from the initial value register. Whereas Shao teach that wherein the logic circuit includes an initial value register (i.e. the ADC 206 can include logic circuitry, see par. 0040]), and is configured to, after a power-on reset, output the adjustment signal (i.e. n, fig. 2, see para. [0040]) based on an initial value of an adjustment value for the output voltage from the initial value register (i.e. see pars. [0040-0043]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the regulator of Zhang by incorporating the logic circuit and the voltage adjustment circuit of Shao to enhance the output voltage detection efficiency in adjusting the required output voltage by the load.
In re to claims 4-5, Zhang disclose the regulator (i.e. fig. 1 ) according to claim 1. Except, Zhang fail to explicitly disclose that wherein the logic circuit is configured to output the adjustment signal based on an adjustment value for the output voltage read out from a nonvolatile memory; wherein the output voltage is supplied as a power supply voltage in common to the output voltage adjustment circuit and the logic circuit. Whereas Shao teach that
wherein the logic circuit (i.e. the ADC 206 can include logic circuitry, see par. 0040]) is configured to output the adjustment signal (i.e. n, fig. 2, see para. [0040]) based on an adjustment value for the output voltage read out from a nonvolatile memory (i.e. computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks and the like, see par. [0088]); wherein the output voltage (i.e. 1 04/110, fig. 2) is supplied as a power supply voltage in common to the output voltage adjustment circuit (i.e. 112A, fig. 2) and the logic circuit (i.e. the ADC 206 can include logic circuitry, see par. 0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the regulator of Zhang by incorporating the logic circuit and the voltage adjustment circuit of Shao to enhance the output voltage detection efficiency in adjusting the required output voltage by the load.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al.
(US 2004/0174150 A1), hereinafter ‘Zhang, in view of Shao et al. (US 2015/0198635 A1) and in view of Yamazaki et al. (US 2010/0013442 A1), hereinafter ‘Yamazaki.
In re to claim 12, Zhang disclose a circuit device (i.e. fig. 1) comprising: the regulator (i.e. fig. 1, see par. [0034]) according to claim 1. Except, Zhang and Shao fail to explicitly disclose that a charging circuit configured to, based on the input voltage (i.e. power supplied from power supply circuit 11), charge an object to be charged (i.e.; and a charge control circuit configured to control the charging circuit, wherein the output voltage is supplied as a power supply voltage for the charge control circuit or a power supply voltage for a detection circuit used for the charge control circuit. Whereas, Yamazaki teach that a charging circuit (i.e. charging system, fig. 1, see par. [0122]) configured to, based on the input voltage (i.e. input voltage from power supply device 10, see par. [0123]) charge an object to be charged (i.e. E2, see par. [0026]); and a charge control circuit (i.e. 12) configured to control the charging circuit (i.e. see par. [0125]), wherein the output voltage is supplied as a power supply voltage for the charge control circuit (i.e. 12) or a power supply voltage for a detection circuit (i.e. 14, fig. 3, see par. [00141]) used for the charge control circuit (i.e. see the Abstract and par. [0141]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the regulator of Zhang and Shao by incorporating the charging circuit of Shao to enhance an alternate rechargeable power supply system for the regulator circuit of Zhang and Shao.
Allowable Subject Matter
Claims 2 and 6-11 are objected to as being dependent upon a rejected base claim, but
would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In re to claim 2, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “the output voltage adjustment circuit includes a first inverter configured to output a first control signal for controlling one of the n-type transistor and the p-type transistor, and a second inverter configured to receive an output of the first inverter and to output a second control signal for controlling another of the n-type transistor and the p-type transistor”.
In re to claim 6, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the plurality of resistors include a first resistor group disposed between a feedback voltage node from which the feedback voltage is output and a predetermined voltage node, and a second resistor group disposed between the node at the output voltage and the feedback voltage node”.
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
In re to claims 7-11, claims 7-11 depend on claim 6, thus are also objected for the same reasons provided above.
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838