DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s arguments filed on 07/08/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 13-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants’ arguments, see REMARKS, filed on 07/08/2026, with respect to claims 9-12 have been fully considered and are persuasive. The 103 Rejections of claims 9-12 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 17 are rejected under 35 U.S.C 103 as being unpatentable over Mesa et al. (“Mesa”, US Pub 2022/0345033), in view of Dusmez et al. (“Dusmez”, US Pub 2020/0313421).
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Above Fig. 1-4, from Mesa et al. (“Mesa”, US Pub 2022/0345033)
Regarding independent claim 13, Mesa teaches (Fig. 1-4) a totem pole PFC circuit (bridgeless totem pole PFC circuit 100; Para 46) comprising:
an inductor (L 104) coupled between a first node (i.e., node that connects +Vac 125 to L) and a second node (since, Applicant never claimed or used phrase “direct connection without having intervening elements”, thus under broadest reasonable interpretations (BRI) 2nd node can be interpreted as node that connects -Vac 124 to L, via other elements; &/or node that connects switching node SW node 123 to L directly) (Para 32-53);
a first power switch (SR1 111) coupled between an output node (Vdc out 131) and the second node (since, Applicant never claimed or used phrase “direct connection without having intervening elements”, thus under BRI 2nd node can be interpreted as node that connects -Vac 124 to L, via other elements; &/or node that connects switching node SW node 123 to L directly) (Para 32-53);
a second power switch (SR2 112) coupled between the second node (since, Applicant never claimed or used phrase “direct connection without having intervening elements”, thus under BRI 2nd node can be interpreted as node that connects -Vac 124 to L, via other elements; &/or node that connects switching node SW node 123 to L directly) and a reference ground (132) (Para 32-53);
a high side power switch (S1 121) coupled between the output node (Vdc out 131) and a switching node (SW node 123) (Para 32-53);
a low side power switch (S2 122) coupled between the switching node (SW node 123) and the reference ground (132) (Para 32-53);
a switch control circuit (150; Para 53-78, claims 1-21 and abstract) configured to generate a high side control signal (S1) based on an AC input voltage (Vac);
a comparing circuit (Fig. 2-4 and Table I-II; although not explicitly spelled out the comparing circuit but such operation is in 150, since 150 detects 150 detects i) when + VAC ½ cycle crosses 1st threshold 201 (i.e., during period t1-t0, which is prior to zero-crossing time t0), ii) when - VAC ½ cycle crosses 2nd threshold 202 (i.e., during period t0-t2, which is post time t01) and then 150 controls the switching operation in 100 (i.e., SR1-2, S1-2), based on the detection, as can be seen in Table I, wherein Table II shows varied duty cycle switching of 1st leg 120 (S1-2); para 43-44, 54-55, 66-69 74-77) coupled to the output node (Vdc out 131) and the switching node (operatively coupled to SW node 123, via switching operation) and configured to generate a high side switching signals (S1 being turned on/off by 150) to control the high side power switch (S1); and
a (first) logic circuit (although not explicitly spelled out, but such logic is anticipated since some type of logic or drive is required to control switching operation in 100, based on comparing output) configured to generate a high side drive signal to control the high side power switch (150’s logic output drive that controls S1, based on comparing output), wherein the high side power switch is configured to switch (Fig. 4A, Table I-II; para 43-44, 54-55, 66-69 74-77) in response to the polarity of the AC input voltage (the polarity of VAC being +/- VAC ½ cycle) (Fig. 2-4a; 150 detects i) when + VAC ½ cycle crosses 1st threshold 201 (i.e., during period t1-t0, which is prior to zero-crossing time t0), ii) when - VAC ½ cycle crosses 2nd threshold 202 (i.e., during period t0-t2, which is post time t01) and then 150 controls the switching operation in 100 (i.e., SR1-2, S1-2), based on the detection, as can be seen in Table I, wherein Table II shows varied duty cycle switching of 1st leg 120 (S1-2); wherein Fig. 4A shows switching of S1 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t0-t2; wherein Fig. 4B shows switching of S2 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t1-t0; para 43-44, 54-55, 66-69 74-77).
However, Mesa fails to teach a first comparing circuit (coupled to the output node and the switching node) configured to generate a high side off signal by comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal (to control the high side power switch) based on the high side control signal (i.e., output of the switch control circuit generation based on input signal) and the high side off signal.
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Above Fig. 1D, 2A, from Dusmez et al. (“Dusmez”, US Pub 2020/0313421)
However, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55)
a first comparing circuit (i.e. any one of required respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b)
coupled to the output node (i.e., each of 202ab’s + input connected to the output node providing Vout/Iout to load/capacitor 108, taking into consideration sensed voltage of 104a’s drain and 104b’s source) and the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain) and
configured to generate a high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off)
by comparing a first voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the high side power switch (104a) with a first threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and
a first logic circuit (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b)
configured to generate a high side drive signal to control the high side power switch (respective gate drives for 104a high-side switch and 104b low-side switch)
based on the high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) and the high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
[Additional NOTE: Dusmez also teaches a totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) comprising:
an inductor (inductor L 106’s) coupled between a first node (1st node coupled to + Vin) and a second node (2nd node is a switching mid-node “sw2”, where 126ab are connected in series and also coupled to -Vin, and thus L106 coupled to sw2, via switching operation);
a first power switch (126a) coupled between an output node (126a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and the second node (i.e., 126a’s source connected to 2nd node, which is a switching mid-node “sw2”, where 126ab are connected in series);
a second power switch (126b) coupled between the second node (i.e., 126b’s drain connected to the 2nd switching mid-node “sw2”, where 126ab are connected in series) and a reference ground (126b’s source connected to gnd; Para 28);
a high side power switch (104a) coupled between the output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series);
a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and the reference ground (104b’s source connected to gnd; Para 28); and
a switch control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) configured to generate a high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) based on an AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28).]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mesa’s PFC circuit to additionally include a first comparing circuit (coupled to the output node and the switching node) configured to generate a high side off signal by explicitly comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal (to control the high side power switch) based on the high side control signal (i.e., output of the switch control circuit generation based on input signal) and the high side off signal, as disclosed by Dasmuz, as doing so would have provided an improved circuit design choice by selecting fault triggered diode emulation control for the respective required transistor (i.e., of high-side transistor), in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor, resulting to overall improved efficient operation, preventing any unnecessary power loss within the PFC circuit, while maintaining steady operation from varied AC inputs and to output steady output, as required by the load, as taught by Dasmuz (abstract and Para 1-3).
Regarding claim 17, Mesa teaches wherein the switch control circuit (150; Para 53-78, claims 1-21 and abstract) is further configured to generate a low side control signal (i.e., controlling S2) based on the AC input voltage (the polarity of VAC being +/- VAC ½ cycle) (Fig. 2-4a; 150 detects i) when + VAC ½ cycle crosses 1st threshold 201 (i.e., during period t1-t0, which is prior to zero-crossing time t0), ii) when - VAC ½ cycle crosses 2nd threshold 202 (i.e., during period t0-t2, which is post time t01) and then 150 controls the switching operation in 100 (i.e., SR1-2, S1-2), based on the detection, as can be seen in Table I, wherein Table II shows varied duty cycle switching of 1st leg 120 (S1-2); wherein Fig. 4A shows switching of S1 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t0-t2; wherein Fig. 4B shows switching of S2 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t1-t0; para 43-44, 54-55, 66-69 74-77) in the totem pole PFC circuit.
However, Mesa fails to teach the totem pole PFC circuit further comprising: a second comparing circuit coupled to the switching node and the reference ground and configured to generate a low side off signal by comparing a second voltage indicative of a drain-source voltage of the low side power switch with a second threshold voltage; and a second logic circuit configured to generate a low side drive signal to control the low side power switch based on the low side control signal and the low side off signal.
However, Dasmuz teaches the totem pole PFC circuit further comprising:
a second comparing circuit (2nd comparing circuit ‘202b, 204b’ controlling 104b)
coupled to
the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain) and
the reference ground (104b’s source connected to Gnd and also source voltage being received by 202 -input; Para 28) and
configured to generate a low side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off)
by comparing
a second voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the low side power switch (104b) with
a second threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and
a second logic circuit (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b)
configured to generate a low side drive signal to control the low side power switch (respective gate drives for 104a high-side switch and 104b low-side switch)
based on
the low side control signal (i.e., gate drive for 104b, or 126b, both being low-side switches) and
the low side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
[See above additional NOTE, which is applicable herein.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mesa’s PFC circuit to additionally include a first comparing circuit (coupled to the output node and the switching node) configured to generate a high side off signal by explicitly comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal (to control the high side power switch) based on the high side control signal (i.e., output of the switch control circuit generation based on input signal) and the high side off signal; a second comparing circuit coupled to the switching node and the reference ground and configured to generate a low side off signal by comparing a second voltage indicative of a drain-source voltage of the low side power switch with a second threshold voltage; and a second logic circuit configured to generate a low side drive signal to control the low side power switch based on the low side control signal and the low side off signal, as disclosed by Dasmuz, as doing so would have provided an improved circuit design choice by selecting fault triggered diode emulation control for the respective required transistor (i.e., of high-side & low-side transistor), in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor, resulting to overall improved efficient operation, preventing any unnecessary power loss within the PFC circuit, while maintaining steady operation from varied AC inputs and to output steady output, as required by the load, as taught by Dasmuz (abstract and Para 1-3).
Claim 15 is rejected under 35 U.S.C 103 as being unpatentable over Mesa (US Pub 2022/0345033), in view of Dusmez (US Pub 2020/0313421) and Sinow et al. (“Sinow”, US Pub 2022/0155432).
Mesa and Dusmez fail to teach a first diode coupled between the output node and the first node; and a second diode coupled between the first node and the reference ground.
However, Sinow teaches a first diode (D1) coupled between the output node (Vo) and the first node (+Vac coupling D1’s cathode via switching operation, and D1’s anode coupled to -Vac); and a second diode (D2) coupled between the first node (D2 coupled between -Vac and Gnd) and the reference ground (Gnd).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the totem pole PFC circuit collectively taught by Mesa and Dasmuz to include a first diode coupled between the output node and the first node; and a second diode coupled between the first node and the reference ground, as disclosed by Sinow, as doing so would have provided an improved circuit by controlling the power flow in a specific direction, thus improving overall size and the efficiency of the power conversion circuit, as taught by Sinow (Para 3 and abstract).
Claim 16 and 18 are rejected under 35 U.S.C 103 as being unpatentable over Mesa (US Pub 2022/0345033), in view of Dusmez (US Pub 2020/0313421) and Kinzer et al. (“Kinzer”, US Pat 11145579).
Regarding claim 16, Mesa teaches … an input terminal of the …comparing circuit and the output node; and … configured to provide a conduction path between the input terminal of the …comparing circuit and the output node when the AC input voltage is in a negative half cycle (the polarity of VAC being +/- VAC ½ cycle) (Fig. 2-4a; 150 detects i) when + VAC ½ cycle crosses 1st threshold 201 (i.e., during period t1-t0, which is prior to zero-crossing time t0), ii) when - VAC ½ cycle crosses 2nd threshold 202 (i.e., during period t0-t2, which is post time t01) and then 150 controls the switching operation in 100 (i.e., SR1-2, S1-2), based on the detection, as can be seen in Table I, wherein Table II shows varied duty cycle switching of 1st leg 120 (S1-2); wherein Fig. 4A shows switching of S1 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t0-t2; wherein Fig. 4B shows switching of S2 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t1-t0; para 43-44, 54-55, 66-69 74-77).
However, Mesa fails to teach a first unidirectional device coupled between an input terminal of the first comparing circuit and the output node; and a first conducting circuit coupled to the first unidirectional device and configured to provide a conduction path between the input terminal of the first comparing circuit and the output node when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle).
However, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) … coupled between an input terminal of the first comparing circuit (i.e. inputs of taught 1st comparing circuit ‘202a, 204a’ controlling 104a and inputs of taught 2nd comparing circuit ‘202b, 204b’ controlling 104b) and the output node (output node providing Vout/Iout to load/capacitor 108); and a first conducting circuit (i.e., switch 200a) coupled to …and configured to provide a conduction path for the input terminal of the first comparing circuit (input terminals of 1st comparing circuit ‘202a, 204a’ controlling 104a) and the output node (output node providing Vout/Iout to load/capacitor 108) when the AC input voltage is in a negative half cycle (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mesa’s PFC circuit to additionally include a first comparing circuit (coupled to the output node and the switching node) configured to generate a high side off signal by explicitly comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal (to control the high side power switch) based on the high side control signal (i.e., output of the switch control circuit generation based on input signal) and the high side off signal; a second comparing circuit coupled to the switching node and the reference ground and configured to generate a low side off signal by comparing a second voltage indicative of a drain-source voltage of the low side power switch with a second threshold voltage; and a second logic circuit configured to generate a low side drive signal to control the low side power switch based on the low side control signal and the low side off signal, as disclosed by Dusmez, as doing so would have provided an improved circuit design choice by selecting fault triggered diode emulation control for the respective required transistor (i.e., of high-side & low-side transistor), in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor, resulting to overall improved efficient operation, preventing any unnecessary power loss within the PFC circuit, while maintaining steady operation from varied AC inputs and to output steady output, as required by the load, as taught by Dasmuz (abstract and Para 1-3).
However, Mesa and Dusmez fail to teach, a first unidirectional device (i.e., Applicant’s Fig. 11; D1) coupled between an input terminal of the first comparing circuit (i.e., Applicant’s Fig. 11; 201E CMP, comparing between sensed first voltage of drain-source voltage Vds1 of high-side switch S4, via D1 with a first threshold Vth1; wherein D1 cathode is connected between Vout and S4’s drain, thus establishing a connection with output node Vout) and the output node; and a first conducting circuit (i.e., Applicant’s Fig. 11; 209, which may be a resistor or a current source, coupled between 201E’s input and D1’s anode, thus establishing a conduction path) coupled to the first unidirectional device and configured to provide a conduction path between the input terminal of the first comparing circuit and the output node when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle).
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Above Fig. 1 & 6c, from Kinzer et al. (“Kinzer”, US Pat 11145579)
However, Kinzer teaches (Fig. 1, 6c; desaturation detection circuit 640 may be used for either or both of high-side switch 115 and low-side switch 110 of a totem pole PFC circuit 100; 640 includes power transistor 642 (may be used as high-side or low-side switch), switching node 644, reference ground, unidirectional device being diode 656, comparator 660, reference voltage 662, gate logic control 646, PWM signal 648 and gate drive signal to drive 642; col. 10 L62-col. 11 L32) the control circuit (i.e., control circuit that must provide PWM signal 648), utilization of pins for encapsulated package of a transistor (use of pins explicitly taught for source pins, ground pins, individual signal pins used for I/O terminals (i.e., high-side or low-side transistor’s current sharing terminals sharing nodes), such as any control signals and/or, gate driver signals, etc.,; see col. 4 L43-56, col. 8 L26-36) a first unidirectional device (diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) coupled between an input terminal of the first comparing circuit (diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) and the output node (650 as 1st node/pin coupling to the switching node 644, via a resistor); and a first conducting circuit (voltage divider 654, 664 and Vcc 652, coupled between comparator 660’s input and diode 656’s anode, thus establishing a conduction path) coupled to the first unidirectional device(diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) and configured to provide a conduction path between the input terminal of the first comparing circuit (diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) and the output node (650 as 1st node/pin coupling to the switching node 644, via a resistor) when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle of +V 125).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the PFC circuit collectively taught by Mesa and Dusmez to include a first unidirectional device coupled between an input terminal of the first comparing circuit and the output node; and a first conducting circuit coupled to the first unidirectional device and configured to provide a conduction path between the input terminal of the first comparing circuit and the output node when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle), as disclosed by Kinzer, as doing so would during any fault detection such circuit design choice would have prevented unnecessary damage to the transistor, resulting efficient and overall steady performance within the PFC circuit, while anticipated reduced manufacturing cost, as taught by Kinzer (abstract and col. 10 L62-col. 11 L32).
Regarding claim 18, Mesa teaches … an input terminal of the … comparing circuit and the output node; and … configured to provide a conduction path between the input terminal of the …comparing circuit and the output node when the AC input voltage is in a negative half cycle (the polarity of VAC being +/- VAC ½ cycle) (Fig. 2-4a; 150 detects i) when + VAC ½ cycle crosses 1st threshold 201 (i.e., during period t1-t0, which is prior to zero-crossing time t0), ii) when - VAC ½ cycle crosses 2nd threshold 202 (i.e., during period t0-t2, which is post time t01) and then 150 controls the switching operation in 100 (i.e., SR1-2, S1-2), based on the detection, as can be seen in Table I, wherein Table II shows varied duty cycle switching of 1st leg 120 (S1-2); wherein Fig. 4A shows switching of S1 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t0-t2; wherein Fig. 4B shows switching of S2 in response to the polarity of VAC switching between +/- VAC ½ cycle, during period t1-t0; para 43-44, 54-55, 66-69 74-77).
However, Mesa fails to teach a second unidirectional device coupled between an input terminal of the second comparing circuit and the switching node; and a second conducting circuit coupled to the second unidirectional device and configured to provide a conduction path between the input terminal of the second comparing circuit and the switching node when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle).
However, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) … coupled between an input terminal of the second comparing circuit (i.e. inputs of taught 1st comparing circuit ‘202a, 204a’ controlling 104a and inputs of taught 2nd comparing circuit ‘202b, 204b’ controlling 104b) and the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain); and a second conducting circuit (i.e., switch 200b) coupled to … and configured to provide a conduction path for the input terminal of the second comparing circuit (input terminals of 2nd comparing circuit ‘202b, 204b’ controlling 104b) and the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain) when the AC input voltage is in a positive half cycle (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mesa’s PFC circuit to additionally include a first comparing circuit (coupled to the output node and the switching node) configured to generate a high side off signal by explicitly comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal (to control the high side power switch) based on the high side control signal (i.e., output of the switch control circuit generation based on input signal) and the high side off signal; a second comparing circuit coupled to the switching node and the reference ground and configured to generate a low side off signal by comparing a second voltage indicative of a drain-source voltage of the low side power switch with a second threshold voltage; and a second logic circuit configured to generate a low side drive signal to control the low side power switch based on the low side control signal and the low side off signal, as disclosed by Dusmez, as doing so would have provided an improved circuit design choice by selecting fault triggered diode emulation control for the respective required transistor (i.e., of high-side & low-side transistor), in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor, resulting to overall improved efficient operation, preventing any unnecessary power loss within the PFC circuit, while maintaining steady operation from varied AC inputs and to output steady output, as required by the load, as taught by Dusmez (abstract and Para 1-3).
However, Mesa and Dusmez fail to teach, a second unidirectional device (i.e., Applicant’s Fig. 11; D2) coupled between an input terminal of the second comparing circuit (i.e., Applicant’s Fig. 11; 203E CMP, comparing between sensed first voltage of drain-source voltage Vds2 of low-side switch S3, via D2 with a second threshold Vth2; wherein D2 cathode is connected between node SW (which couples S4’s source and S3’s drain), thus establishing a connection with output node Vout) and the switching node; and a second conducting circuit coupled to the second unidirectional device and configured to provide a conduction path between the input terminal of the second comparing circuit and the switching node when the AC input voltage is in a positive half cycle.
However, Kinzer teaches (Fig. 1, 6c; desaturation detection circuit 640 may be used for either or both of high-side switch 115 and low-side switch 110 of a totem pole PFC circuit 100; 640 includes power transistor 642 (may be used as high-side or low-side switch), switching node 644, reference ground, unidirectional device being diode 656, comparator 660, reference voltage 662, gate logic control 646, PWM signal 648 and gate drive signal to drive 642; col. 10 L62-col. 11 L32) the control circuit (i.e., control circuit that must provide PWM signal 648), utilization of pins for encapsulated package of a transistor (use of pins explicitly taught for source pins, ground pins, individual signal pins used for I/O terminals (i.e., high-side or low-side transistor’s current sharing terminals sharing nodes), such as any control signals and/or, gate driver signals, etc.,; see col. 4 L43-56, col. 8 L26-36) a second unidirectional device (diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) coupled between an input terminal of the first comparing circuit (diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) and the switching node (650 as 1st node/pin coupling to the switching node 644, via a resistor); and a second conducting circuit (voltage divider 654, 664 and Vcc 652, coupled between comparator 660’s input and diode 656’s anode, thus establishing a conduction path) coupled to the second unidirectional device(diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) and configured to provide a conduction path between the input terminal of the second comparing circuit (diode 656, same as Applicant’s Fig. 11-12 unidirectional device diode ‘D1, D3’; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 11 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642) and the switching node (650 as 1st node/pin coupling to the switching node 644, via a resistor) when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle of +V 125).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the PFC circuit collectively taught by Mesa and Dusmez to include a second unidirectional device coupled between an input terminal of the second comparing circuit and the switching node; and a second conducting circuit coupled to the second unidirectional device and configured to provide a conduction path between the input terminal of the second comparing circuit and the switching node when the input voltage changes (i.e., when using AC input and the signal one of the positive or negative half cycle), as disclosed by Kinzer, as doing so would during any fault detection such circuit design choice would have prevented unnecessary damage to the transistor, resulting efficient and overall steady performance within the PFC circuit, while anticipated reduced manufacturing cost, as taught by Kinzer (abstract and col. 10 L62-col. 11 L32).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 14, Dusmez (US Pub 2020/0313421) teaches (Fig. 1D, 2A, 3-8) when the first voltage (i.e., 1st voltage being respective diff amp 202a/202b’s output, which is used as one of the inputs by 204a/204b) is higher than the first threshold voltage (i.e., 0V or any preferred reference voltage used as another input by 204a/204b), the high side power switch is turned on NOT off (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
Thus, cited art(s) failed to teach, “when the first voltage is higher than the first threshold voltage, the high side power switch is configured to be turned off”.
Claims 1-12 and 19-20 are allowed.
Regarding independent claim 1, Dusmez (US Pub 2020/0313421) teaches (Fig. 1D, 2A, 3-8; Para 37-55) a control circuit (i.e., 102) for a totem pole PFC (power factor correction) circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) with a high side power switch (104a) coupled between an output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series) and a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and a reference ground (104b’s source connected to gnd; Para 28), the control circuit (102) configured to be coupled to the output node (output node providing Vout/Iout to load/capacitor 108); a first node to be coupled to the output node (output node providing Vout/Iout to load/capacitor 108); a second node (2nd node being gate drive signal of 104a) configured to be coupled to a control terminal of the high side power switch (104a’s gate); a third node (3rd node being same as the switching mid-node “sw1”, where 104ab are connected in series) configured to be coupled to the switching node (sw1); a fourth node (4th or 5th nodes being one of +/- AC inputs); a fifth pin (4th or 5th nodes being one of +/- AC inputs), wherein the fourth pin and the fifth pin are configured to be coupled to an AC (alternating current) input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28); a switch control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) configured to generate a high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) based on the AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28); a first comparing circuit (i.e. any one of required respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b) coupled to the first node (i.e., 1st node being 104a’s drain output node) and the third node (3rd node being same as the switching mid-node “sw1”, where 104ab are connected in series) and configured to generate a high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) by comparing a first voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the high side power switch (104a) with a first threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and a first logic circuit (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b) configured to generate a high side drive signal (respective gate drives for 104a high-side switch and 104b low-side switch) to control the high side power switch (104a) based on the high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) and the high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
However, Kikuchi (US Pub 2020/0169160) teaches (Fig. 1) uses of controllers (1, 2) being integrated controllers which uses varied pins for specific connection.
Additionally, Li et al. (“Li”, US Pat 9941784) teaches (Fig. 2-15; col. 4 L27-col. 7 L15), regarding claims 1, 3-6, the following, a control circuit (21) for a totem pole PFC (power factor correction) circuit with a high side power switch (Q1, Q3) coupled between an output node (Vbulk) and a switching node (mid node of Q1-2 and mid-node of Q3-4) and a low side power switch (Q2, Q4) coupled between the switching node (mid node of Q1-2 and mid-node of Q3-4) and a reference ground (GND) the control circuit (21) configured to be coupled to the output node (Vbulk); a first node (1st pin node to receive Vbulk, using turn ratio of CT) configured to be coupled to the output node (Vbulk); a second node (2nd node being gate drive signal of Q1) configured to be coupled to a control terminal of the high side power switch (Q1’s gate); a third node (3rd node being same as the switching mid-node, where Q1-2 are connected in series) configured to be coupled to the switching node (sw1); a fourth node (4th or 5th nodes being one of +/- AC inputs); a fifth pin (4th or 5th nodes being one of +/- AC inputs), wherein the fourth pin and the fifth pin are configured to be coupled to an AC (alternating current) input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle); a sixth node configured to be coupled to a control terminal of the low side power switch (i.e., Q2, Q4 gates); a seventh node configured to be coupled to the reference ground (gnd); a switch control circuit (22ab) configured to generate a high side control signal (i.e., gate drive for Q1) and a low side control signal (i.e., gate drive for Q2) based on the AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle); a first current controlled sensing means (22: CT1) coupled to the first node (1st node to receive Vbulk, using turn ratio of CT) and the third node (3rd node being same as the switching mid-node, where Q1-2 are connected in series, using using turn ratio of CT) and configured to generate a high side off signal (i.e., disabling CS1) … a first voltage indicative of a drain-source voltage (Vds) of the high side power switch (Q1) …; a first logic circuit (explicit driver in 21 for Q1) configured to generate a high side drive signal to control the high side power switch (Q1’s gate) based on the high side control signal ((i.e., gate drive for Q1) and the high side off signal (i.e., disabling CS1); a second current controlled sensing means (22: CT2) coupled to the third node and the seventh node and configured to generate a low side off signal (i.e., disabling CS2) … a second voltage indicative of a drain-source voltage of the low side power switch (Vds2 of Q2) …; a second logic circuit (explicit driver in 21 for Q2) to generate a low side drive signal to control the low side power switch (Q2’s gate) based on the low side control signal and the low side off signal (i.e., disabling CS1); wherein the first node (1st pin node to receive Vbulk, using turn ratio of CT) is further configured to be coupled to the output node (Vbulk) through a first unidirectional device (i.e., D1), the control circuit (21) further comprising: a first conducting circuit (resistors (i.e, R1-22) AND switches in 22ab) coupled to the first node (1st pin node to receive Vbulk, using turn ratio of CT) and configured to provide a conduction path between the first pin (1st pin node to receive Vbulk, using turn ratio of CT) and the output node (Vbulk) when the AC input voltage is in a negative half cycle (Vac being -1/2 cycle); wherein the first conducting circuit (resistors (i.e, R1-22) AND switches in 22ab) comprises a current source or a resistor (resistors (i.e, R1-22) AND switches in 22ab) coupled between a first supply voltage and the first pin; a second unidirectional device (D2) coupled between an input terminal of the second current controlled sensing means and the third pin; and a second conducting circuit (resistors (i.e, R1-22) AND switches in 22b) coupled to the second unidirectional device (D2) and configured to provide a conduction path between the input terminal of the second current controlled means and the third pin when the AC input voltage is in a positive half cycle.
However, cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise simply combine with any other arts, due to specific controlled operation, based on explicit specific connection, a control circuit for a totem pole PFC (power factor correction) circuit with a high side power switch coupled between an output node and a switching node and a low side power switch coupled between the switching node and a reference ground, “the control circuit comprising: a first pin configured to be coupled to the output node; a second pin configured to be coupled to a control terminal of the high side power switch; a third pin configured to be coupled to the switching node; a fourth pin; a fifth pin, wherein the fourth pin and the fifth pin are configured to be coupled to an AC (alternating current) input voltage; a switch control circuit configured to generate a high side control signal based on the AC input voltage; a first comparing circuit coupled to the first pin and configured to generate a high side off signal by comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal to control the high side power switch based on the high side control signal and the high side off signal”.
Claims 2-8 depend on claim 1.
Regarding independent claim 9, Dusmez (US Pub 2020/0313421) teaches (Fig. 1D, 2A, 3-8; Para 37-55) a control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) for a totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) with a high side power switch (104a) coupled between an output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series) and a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and a reference ground (104b’s source connected to gnd; Para 28), the control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) comprising: a first node (i.e., 1st node that carries Vs2 of 104b) configured to be coupled to the switching node (sw1); a second pin (i.e., 2nd node that carries Vd3 of 104b) configured to be coupled to the switching node (sw1) through …; a third node (3rd node that provided gate for 104b) configured to be coupled to a control terminal of the low side power switch (104b’s gate); and a fourth node (4th node coupling to Gnd) configured to be coupled to the reference ground (Gnd); wherein the control circuit is configured to control the turning-off of the low side power switch (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) based on a first voltage indicative of a drain-source voltage of the low side power switch (i.e., 2nd voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 1st voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b).
However, Dusmez fails to teach use of pins for the control circuit, corresponds to the specific nodes, such as a first pin (control circuit’s 1st pin corresponding to the 1st node coupling the switching node, which is between high-side and low-side transistor); a second pin (control circuit’s 2nd pin corresponding to the 2nd node also coupling the switching node, via a diode) configured to be coupled to the switching node through a first unidirectional device (i.e., diode; wherein the 2nd node coupling the switching node, via the diode, meaning the diode’s one end coupled to the switching node and the diode’s other end coupled to the 2nd pin of the control circuit an input of a comparator, respectively; wherein the comparator is used to compare the low-side switch’s drain-source voltage, via the diode with a threshold); a third pin (control circuit’s 3rd pin corresponding the 3rd node for coupling low side power switch’s gate/control terminal); and a fourth pin (control circuit’s 4th pin corresponding to the 4th node for coupling the reference ground).
However, Kinzer et al. (“Kinzer”, US Pat 11145579) teaches (Fig. 1, 6c; desaturation detection circuit 640 may be used for either or both of high-side switch 115 and low-side switch 110 of a totem pole PFC circuit 100; 640 includes power transistor 642 (may be used as high-side or low-side switch), switching node 644, reference ground, unidirectional device being diode 656, comparator 660, reference voltage 662, gate logic control 646, PWM signal 648 and gate drive signal to drive 642; col. 10 L62-col. 11 L32) the control circuit (i.e., control circuit that must provide PWM signal 648), utilization of pins for encapsulated package of a transistor (use of pins explicitly taught for source pins, ground pins, individual signal pins used for I/O terminals (i.e., high-side or low-side transistor’s current sharing terminals sharing nodes), such as any control signals and/or, gate driver signals, etc.,; see col. 4 L43-56, col. 8 L26-36), includes a first node/pin (650 as 1st node/pin coupling to the switching node 644, via a resistor); a second node/pin (658 as 2nd node/pin) configured to be coupled to the switching node/pin (658 as 2nd node/pin coupling to the switching node 644, via a unidirectional device 656) through a first unidirectional device (diode 656, same as Applicant’s Fig. 12 unidirectional device diode D3; also Kinzer teaches use of comparator 660, same as Applicant’s Fig. 12 ‘201e, or 203e’, comparing between Vref 662 (same as Applicant’s Fig. 12 ‘Vth1, Vth2’ and signal that connects diode 656; wherein diode 656 also connects to drain terminal of 642); a third node/pin (646 as 3rd node for coupling low side power switch 110’s gate/control terminal); and a fourth node/pin (as 4th node for coupling the reference ground).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dasmuze’s PFC circuit to include transistor package using specific nodes/pins with unidirectional device’s coupling and other for specific elements, as disclosed by Kinzer, as doing so would during any fault detection such circuit design choice would have prevented unnecessary damage to the transistor, resulting efficient and overall steady performance within the PFC circuit, while anticipated reduced manufacturing cost, as taught by Kinzer (abstract and col. 10 L62-col. 11 L32).
However, Dusmez and Kinzer fail to teach use of pins for the control circuit, corresponds to the specific nodes, such as a first pin (control circuit’s 1st pin corresponding to the 1st node coupling the switching node, which is between high-side and low-side transistor); a second pin (control circuit’s 2nd pin corresponding to the 2nd node also coupling the switching node, via a diode) configured to be coupled to the switching node through a first unidirectional device (i.e., diode; wherein the 2nd node coupling the switching node, via the diode, meaning the diode’s one end coupled to the switching node and the diode’s other end coupled to the 2nd pin of the control circuit an input of a comparator, respectively; wherein the comparator is used to compare the low-side switch’s drain-source voltage, via the diode with a threshold); a third pin (control circuit’s 3rd pin corresponding the 3rd node for coupling low side power switch’s gate/control terminal); and a fourth pin (control circuit’s 4th pin corresponding to the 4th node for coupling the reference ground).
However, Ma et al. (“Ma”, US Pat 10305366) teaches the control circuit (Fig. 10-13; col. 12 L41-col. 16 L31) utilizing pins, instead of simple node, such as a first pin (1st pin being 360’s drain input, eventually provided as Vds2 of low-side switch 382 on pin C2 to 100; wherein taught 1st pin is coupling the switching node, which is a mid-node between series connected high-side switch 381 and low side switch 382); a second pin (2nd pin being 360’s source input, eventually provided as Vds2 of low-side switch 382 on pin C2 to 100; wherein taught 2nd pin is coupling the taught switching node) configured to be coupled to the switching node through … device (i.e., 364); a third pin (3rd pin being S2 output for driving low side power switch 382’s gate/control terminal); and a fourth pin (4th pin coupling the reference ground).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the PFC circuit collectively taught by Dusmez and Kinzer to include the use of pins for the control circuit coupling to specific element’s node(s), as taught by Ma as doing so would have at least reduced complexity (i.e., delay of switch control signal timing is substantially eliminated or reduced) and improved performance, efficiency, accuracy of the control of the power converter, e.g. under CRM operation, as taught by Ma (col. 2 L1-40).
However, none of the cited art(s) teaches use of pins for the control circuit, corresponds to the specific node(s), such as “a second pin (control circuit’s 2nd pin corresponding to the 2nd node also coupling the switching node, via a diode) configured to be coupled to the switching node through a first unidirectional device (i.e., diode; wherein the 2nd node coupling the switching node, via the diode, meaning the diode’s one end coupled to the switching node and the diode’s other end coupled to the 2nd pin of the control circuit an input of a comparator, respectively; wherein the comparator is used to compare the low-side switch’s drain-source voltage, via the diode with a threshold)”.
Claims 10-12 depend on claim 9.
Regarding independent claim 19, Dusmez (US Pub 2020/0313421) teaches (Fig. 1D, 2A, 3-8; Para 37-55) a control method for a totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) with a high side power switch (104a) coupled between an output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series) and a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and a reference ground (104b’s source connected to gnd; Para 28), the control method comprising: generating (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) a high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) based on an AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28); providing a first conduction path (1st conduction path using 200a, 2nd conduction path using 200b) … when the AC input voltage is in a negative half cycle (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28); receiving (i.e., specifically 202a, 202b; wherein each being part of respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b) a first voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the high side power switch (104a) … the first conduction path (1st conduction path using 200a, 2nd conduction path using 200b); generating a high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) by comparing (i.e., specifically 204a, 204b; wherein each being part of respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b) the first voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) with a first threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and generating (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b) a high side drive signal (i.e., gate drive for 104a, or 126a, both being high-side switches) to control the high side power switch (104a) based on the high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) and the high side off signal(i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
However, cited art(s) failed to teach, as a whole, a control method for a totem pole PFC circuit with a high side power switch coupled between an output node and a switching node and a low side power switch coupled between the switching node and a reference ground, the control method comprising: generating a high side control signal based on an AC input voltage; “providing a first conduction path through a first unidirectional device (i.e., Applicant’s Fig. 11; D1) when the AC input voltage is in a negative half cycle; receiving a first voltage indicative of a drain-source voltage of the high side power switch through the first conduction path; generating a high side off signal by comparing the first voltage with a first threshold voltage; and generating a high side drive signal to control the high side power switch based on the high side control signal and the high side off signal”.
Claim 20 depends on claim 19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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