DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 06/14/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 13, 17 are rejected under 35 U.S.C 102(a)(1) as being anticipated by Dusmez et al. (“Dusmez”, US Pub 2020/0313421).
6. Regarding independent claim 13, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) a totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) comprising:
an inductor (inductor L 106’s) coupled between a first node (1st node coupled to + Vin) and a second node (2nd node is a switching mid-node “sw2”, where 126ab are connected in series and also coupled to -Vin, and thus L106 coupled to sw2, via switching operation);
a first power switch (126a) coupled between an output node (126a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and the second node (i.e., 126a’s source connected to 2nd node, which is a switching mid-node “sw2”, where 126ab are connected in series);
a second power switch (126b) coupled between the second node (i.e., 126b’s drain connected to the 2nd switching mid-node “sw2”, where 126ab are connected in series) and a reference ground (126b’s source connected to Gnd; Para 28);
a high side power switch (104a) coupled between the output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series);
a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and the reference ground (104b’s source connected to Gnd; Para 28);
a switch control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches)
configured to generate a high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches)
based on an AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28);
a first comparing circuit (i.e. any one of required respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b)
coupled to
the output node (i.e., each of 202ab’s + input connected to the output node providing Vout/Iout to load/capacitor 108, taking into consideration sensed voltage of 104a’s drain and 104b’s source) and
the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain) and
configured to generate a high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off)
by comparing
a first voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the high side power switch (104a) with
a first threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and
a first logic circuit (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b)
configured to generate a high side drive signal to control the high side power switch (respective gate drives for 104a high-side switch and 104b low-side switch)
based on
the high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) and
the high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
7. Regarding claim 17, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) wherein the switch control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) is further configured to generate a low side control signal (i.e., gate drive for 104b, or 126b, both being low-side switches)
based on the AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28), the totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) further comprising:
a second comparing circuit (2nd comparing circuit ‘202b, 204b’ controlling 104b)
coupled to
the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain) and
the reference ground (104b’s source connected to Gnd and also source voltage being received by 202 -input; Para 28) and
configured to generate a low side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off)
by comparing
a second voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the low side power switch (104b) with
a second threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and
a second logic circuit (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b)
configured to generate a low side drive signal to control the low side power switch (respective gate drives for 104a high-side switch and 104b low-side switch)
based on
the low side control signal (i.e., gate drive for 104b, or 126b, both being low-side switches) and
the low side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 9-11 are rejected under 35 U.S.C 103 as being unpatentable over Dusmez (US Pub 2020/0313421), in view of Ma et al. (“Ma”, US Pat 10305366).
10. Regarding independent claim 9, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) a control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) for a totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) with a high side power switch (104a) coupled between an output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series) and a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and a reference ground (104b’s source connected to gnd; Para 28), the control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) comprising:
a first node (i.e., 1st node that carries Vs2 of 104b) configured to be coupled to the switching node (sw1);
a second pin (i.e., 2nd node that carries Vd3 of 104b) configured to be coupled to the switching node (sw1) through …;
a third node (3rd node that provided gate for 104b) configured to be coupled to a control terminal of the low side power switch (104b’s gate); and
a fourth node (4th node coupling to Gnd) configured to be coupled to the reference ground (Gnd);
wherein the control circuit is configured to control the turning-off of the low side power switch (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) based on a first voltage indicative of a drain-source voltage of the low side power switch (i.e., 2nd voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 1st voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b).
However, Dusmez fails to teach the control circuit utilizing pins, instead of simple node, such as a first pin (as 1st node for coupling the switching node); a second pin (as 2nd node) configured to be coupled to the switching node through a first unidirectional device; a third pin (as 3rd node for coupling low side power switch’s gate/control terminal); and a fourth pin (as 4th node for coupling the reference ground).
However, Ma teaches the control circuit (Fig. 10-13; col. 12 L41-col. 16 L31) utilizing pins, instead of simple node, such as
a first pin (1st pin being 360’s drain input, eventually provided as Vds2 of low-side switch 382 on pin C2 to 100; wherein taught 1st pin is coupling the switching node, which is a mid-node between series connected high-side switch 381 and low side switch 382);
a second pin (2nd pin being 360’s source input, eventually provided as Vds2 of low-side switch 382 on pin C2 to 100; wherein taught 2nd pin is coupling the taught switching node) configured to be coupled to the switching node through a first unidirectional deviec (i.e., 364);
a third pin (3rd pin being S2 output for driving low side power switch 382’s gate/control terminal); and
a fourth pin (4th pin coupling the reference ground).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dusmez’s control circuit to include the use of pins with unidirectional device’s coupling and other for specific elements, in place of node, as taught by Ma as doing so would have at least reduced complexity (i.e., delay of switch control signal timing is substantially eliminated or reduced) and improved performance, efficiency, accuracy of the control of the power converter, e.g. under CRM operation, as taught by Ma (col. 2 L1-40).
11. Regarding claim 10, Dusmez teaches
a fifth node configured to be coupled to the output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) through …; and
a sixth node configured to be coupled to a control terminal of the high side power switch (104a’s gate);
wherein the control circuit is configured to control the turning-off of the high side power switch (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) based on a second voltage indicative of a drain-source voltage of the high side power switch (i.e., 2nd voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 1st voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b).
However, Dusmez fails to teach the control circuit utilizing pins, instead of simple node, such as, a fifth pin configured to be coupled to the output node through a second unidirectional device; and a sixth pin (for coupling the high side power switch’s gate/control terminal).
However, Ma teaches the control circuit utilizing pins, instead of simple node, such as, a fifth pin configured to be coupled to the output node (5th pin being 350’s source or drain input, eventually provided as Vds1 of low-side switch 381 on pin C1 to 100; wherein taught 2nd pin is coupling the taught) through a second unidirectional device (354); and a sixth pin (6th pin being S1 for driving the high side power switch’s gate/control terminal).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dusmez’s control circuit to include the use of pins with unidirectional device’s coupling and other for specific elements, in place of node, as taught by Ma as doing so would have at least reduced complexity (i.e., delay of switch control signal timing is substantially eliminated or reduced) and improved performance, efficiency, accuracy of the control of the power converter, e.g. under CRM operation, as taught by Ma (col. 2 L1-40).
12. Regarding claim 11, Dusmez teaches
a seventh node (i.e., 7th node may be one of +Vac, 8th node may be -Vac, or vice versa); and
an eighth pin, wherein the seventh pin and the eighth pin are configured to be coupled to an AC input voltage (i.e., 7th node may be one of +Vac, 8th node may be -Vac, or vice versa);
wherein the control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) is further configured to control the low side power switch based on the AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28).
However, Dusmez fails to teach the control circuit utilizing pins, instead of simple node, such as the seventh pin and the eighth pins (for coupling to AC input voltage).
However, Ma teaches
a seventh pin (i.e., 7th to 8th pins being on AC1 vs. AC2, received by from Vac); and
an eighth pin, wherein the seventh pin and the eighth pin are configured to be coupled to an AC input voltage (i.e., 7th to 8th pins on AC1 vs. AC1, received by from Vac);
wherein the control circuit is further configured to control the low side power switch based on the AC input voltage.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dusmez’s control circuit to include the use of pins with unidirectional device’s coupling and other for specific elements, in place of node, as taught by Ma as doing so would have at least reduced complexity (i.e., delay of switch control signal timing is substantially eliminated or reduced) and improved performance, efficiency, accuracy of the control of the power converter, e.g. under CRM operation, as taught by Ma (col. 2 L1-40).
Claims 15 is rejected under 35 U.S.C 103 as being unpatentable over Dusmez (US Pub 2020/0313421), in view of Sinow et al. (“Sinow”, US Pub 2022/0155432).
Regarding claim 15, Dusmez fails to teach a first diode coupled between the output node and the first node; and a second diode coupled between the first node and the reference ground.
However, Sinow teaches a first diode (D1) coupled between the output node (Vo) and the first node (+Vac coupling D1’s cathode via switching operation, and D1’s anode coupled to -Vac); and a second diode (D2) coupled between the first node (D2 coupled between -Vac and Gnd) and the reference ground (Gnd).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dusmez’s totem pole PFC circuit to include a first diode coupled between the output node and the first node; and a second diode coupled between the first node and the reference ground, as disclosed by Sinow, as doing so would have provided an improved circuit by controlling the power flow in a specific direction, thus improving overall size and the efficiency of the power conversion circuit, as taught by Sinow (Para 3 and abstract).
Allowable Subject Matter
Claims 14, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12, cited prior art(s) failed to teach, “a first conducting circuit coupled to the second pin and configured to provide a conduction path between the second pin and the switching node when the AC input voltage is in a positive half cycle; and a first comparing circuit coupled to the second pin and the fourth pin and configured to generate a low side off signal to control the turning-off of the low side power switch by comparing the first voltage with a first threshold voltage.
Regarding claim 14, Dusmez teaches (Fig. 1D, 2A, 3-8) when the first voltage (i.e., 1st voltage being respective diff amp 202a/202b’s output, which is used as one of the inputs by 204a/204b) is higher than the first threshold voltage (i.e., 0V or any preferred reference voltage used as another input by 204a/204b), the high side power switch is turned on NOT off (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
Thus, cited art(s) failed to teach, “when the first voltage is higher than the first threshold voltage, the high side power switch is turned off”.
Regarding claim 16, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) … coupled between an input terminal of the first comparing circuit (i.e. inputs of taught 1st comparing circuit ‘202a, 204a’ controlling 104a and inputs of taught 2nd comparing circuit ‘202b, 204b’ controlling 104b) and the output node (output node providing Vout/Iout to load/capacitor 108); and a first conducting circuit (i.e., switch 200a) coupled to …and configured to provide a conduction path for the input terminal of the first comparing circuit (input terminals of 1st comparing circuit ‘202a, 204a’ controlling 104a) and the output node (output node providing Vout/Iout to load/capacitor 108) when the AC input voltage is in a negative half cycle (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28).
However, Dusmez fails to teach, “a first unidirectional device (i.e., Applicant’s Fig. 11; D1) coupled between an input terminal of the first comparing circuit (i.e., Applicant’s Fig. 11; 201E CMP, comparing between sensed first voltage of drain-source voltage Vds1 of high-side switch S4, via D1 with a first threshold Vth1; wherein D1 cathode is connected between Vout and S4’s drain, thus establishing a connection with output node Vout) and the output node; and a first conducting circuit (i.e., Applicant’s Fig. 11; 209, which may be a resistor or a current source, coupled between 201E’s input and D1’s anode, thus establishing a conduction path) coupled to the first unidirectional device and configured to provide a conduction path between the input terminal of the first comparing circuit and the output node when the AC input voltage is in a negative half cycle”.
[Additional NOTE: in regards to use of 1st-2nd unidirectional devices and 1st-2nd conducting circuit, see, alternative following teaching of Li et al. (“Li”, US Pat 9941784), under allowable subject matters, regarding claims 1, 3-6.]
Regarding claim 18, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) … coupled between an input terminal of the second comparing circuit (i.e. inputs of taught 1st comparing circuit ‘202a, 204a’ controlling 104a and inputs of taught 2nd comparing circuit ‘202b, 204b’ controlling 104b) and the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain); and a second conducting circuit (i.e., switch 200b) coupled to … and configured to provide a conduction path for the input terminal of the second comparing circuit (input terminals of 2nd comparing circuit ‘202b, 204b’ controlling 104b) and the switching node (i.e., each of 202ab’s - input connected to the switching mid-node sw1, wherein 104ab connected in series, taking into consideration sensed voltage of 104a’s source and 104b’s drain) when the AC input voltage is in a positive half cycle (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28).
However, Dusmez fails to teach, “a second unidirectional device (i.e., Applicant’s Fig. 11; D2) coupled between an input terminal of the second comparing circuit (i.e., Applicant’s Fig. 11; 203E CMP, comparing between sensed first voltage of drain-source voltage Vds2 of low-side switch S3, via D2 with a second threshold Vth2; wherein D2 cathode is connected between node SW (which couples S4’s source and S3’s drain), thus establishing a connection with output node Vout) and the switching node; and a second conducting circuit coupled to the second unidirectional device and configured to provide a conduction path between the input terminal of the second comparing circuit and the switching node when the AC input voltage is in a positive half cycle”.
[Additional NOTE: in regards to use of 1st-2nd unidirectional devices and 1st-2nd conducting circuit, see, alternative following teaching of Li et al. (“Li”, US Pat 9941784), under allowable subject matters, regarding claims 1, 3-6.]
Claims 1-8 and 19-20 are allowed. The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) a control circuit (i.e., 102) for a totem pole PFC (power factor correction) circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) with
a high side power switch (104a) coupled between an output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series) and
a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and a reference ground (104b’s source connected to Gnd; Para 28),
the control circuit (102) configured to be coupled to the output node (output node providing Vout/Iout to load/capacitor 108);
a second node (2nd node being gate drive signal of 104a) configured to be coupled to a control terminal of the high side power switch (104a’s gate);
a third node (3rd node being same as the switching mid-node “sw1”, where 104ab are connected in series) configured to be coupled to the switching node (sw1);
a fourth node (4th or 5th nodes being one of +/- AC inputs);
a fifth pin (4th or 5th nodes being one of +/- AC inputs), wherein the fourth pin and the fifth pin are configured to be coupled to an AC (alternating current) input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28);
a switch control circuit (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) configured to generate a high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) based on the AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28);
a first comparing circuit (i.e. any one of required respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b) coupled to the first node (i.e., 1st node being 104a’s drain output node) and the third node (3rd node being same as the switching mid-node “sw1”, where 104ab are connected in series) and configured to generate a high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) by comparing a first voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the high side power switch (104a) with a first threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and
a first logic circuit (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b) configured to generate a high side drive signal (respective gate drives for 104a high-side switch and 104b low-side switch) to control the high side power switch (104a) based on the high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) and the high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
However, Kikuchi (US Pub 2020/0169160) teaches (Fig. 1) uses of controllers (1, 2) being integrated controllers which uses varied pins for specific connection.
Additionally, Li et al. (“Li”, US Pat 9941784) teaches (Fig. 2-15; col. 4 L27-col. 7 L15), regarding claims 1, 3-6, the following, a control circuit (21) for a totem pole PFC (power factor correction) circuit with a high side power switch (Q1, Q3) coupled between an output node (Vbulk) and a switching node (mid node of Q1-2 and mid-node of Q3-4) and a low side power switch (Q2, Q4) coupled between the switching node (mid node of Q1-2 and mid-node of Q3-4) and a reference ground (GND)
the control circuit (21) configured to be coupled to the output node (Vbulk);
a first node (1st pin node to receive Vbulk, using turn ratio of CT) configured to be coupled to the output node (Vbulk);
a second node (2nd node being gate drive signal of Q1) configured to be coupled to a control terminal of the high side power switch (Q1’s gate);
a third node (3rd node being same as the switching mid-node, where Q1-2 are connected in series) configured to be coupled to the switching node (sw1);
a fourth node (4th or 5th nodes being one of +/- AC inputs);
a fifth pin (4th or 5th nodes being one of +/- AC inputs), wherein the fourth pin and the fifth pin are configured to be coupled to an AC (alternating current) input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle);
a sixth node configured to be coupled to a control terminal of the low side power switch (i.e., Q2, Q4 gates);
a seventh node configured to be coupled to the reference ground (Gnd);
a switch control circuit (22ab) configured to generate a high side control signal (i.e., gate drive for Q1) and a low side control signal (i.e., gate drive for Q2) based on the AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle);
a first current controlled sensing means (22: CT1) coupled to the first node (1st node to receive Vbulk, using turn ratio of CT) and the third node (3rd node being same as the switching mid-node, where Q1-2 are connected in series, using turn ratio of CT) and configured to generate a high side off signal (i.e., disabling CS1) … a first voltage indicative of a drain-source voltage (Vds) of the high side power switch (Q1) …;
a first logic circuit (explicit driver in 21 for Q1) configured to generate a high side drive signal to control the high side power switch (Q1’s gate) based on the high side control signal ((i.e., gate drive for Q1) and the high side off signal (i.e., disabling CS1);
a second current controlled sensing means (22: CT2) coupled to the third node and the seventh node and configured to generate a low side off signal (i.e., disabling CS2) … a second voltage indicative of a drain-source voltage of the low side power switch (Vds2 of Q2) …;
a second logic circuit (explicit driver in 21 for Q2) to generate a low side drive signal to control the low side power switch (Q2’s gate) based on the low side control signal and the low side off signal (i.e., disabling CS1);
wherein the first node (1st pin node to receive Vbulk, using turn ratio of CT) is further configured to be coupled to the output node (Vbulk) through a first unidirectional device (i.e., D1), the control circuit (21) further comprising:
a first conducting circuit (resistors (i.e., R1-22) AND switches in 22ab) coupled to the first node (1st pin node to receive Vbulk, using turn ratio of CT) and configured to provide a conduction path between the first pin (1st pin node to receive Vbulk, using turn ratio of CT) and the output node (Vbulk) when the AC input voltage is in a negative half cycle (Vac being -1/2 cycle);
wherein the first conducting circuit (resistors (i.e., R1-22) AND switches in 22ab) comprises a current source or a resistor (resistors (i.e., R1-22) AND switches in 22ab) coupled between a first supply voltage and the first pin;
a second unidirectional device (D2) coupled between an input terminal of the second current controlled sensing means and the third pin; and
a second conducting circuit (resistors (i.e., R1-22) AND switches in 22b) coupled to the second unidirectional device (D2) and configured to provide a conduction path between the input terminal of the second current controlled means and the third pin when the AC input voltage is in a positive half cycle.
However, cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise simply combine with any other arts, due to specific controlled operation, based on explicit specific connection,
a control circuit for a totem pole PFC (power factor correction) circuit with a high side power switch coupled between an output node and a switching node and a low side power switch coupled between the switching node and a reference ground, “the control circuit comprising: a first pin configured to be coupled to the output node; a second pin configured to be coupled to a control terminal of the high side power switch; a third pin configured to be coupled to the switching node; a fourth pin; a fifth pin, wherein the fourth pin and the fifth pin are configured to be coupled to an AC (alternating current) input voltage; a switch control circuit configured to generate a high side control signal based on the AC input voltage; a first comparing circuit coupled to the first pin and configured to generate a high side off signal by comparing a first voltage indicative of a drain-source voltage of the high side power switch with a first threshold voltage; and a first logic circuit configured to generate a high side drive signal to control the high side power switch based on the high side control signal and the high side off signal”, as claimed in claim 1; and
“the control circuit comprising: a first pin configured to be coupled to the switching node; a second pin configured to be coupled to the switching node through a first unidirectional device; a third pin configured to be coupled to a control terminal of the low side power switch; and a fourth pin configured to be coupled to the reference ground; wherein the control circuit is configured to control the turning-off of the low side power switch based on a first voltage indicative of a drain-source voltage of the low side power switch”, as claimed in claim 9.
Claims ‘2-8’ are depending from claim 1.
Regarding independent claim 19, Dusmez teaches (Fig. 1D, 2A, 3-8; Para 37-55) a control method for a totem pole PFC circuit (Fig. 1D; full-bridge switching power stage 125 in a totem PFC configurations; Para 17, 37) with a high side power switch (104a) coupled between an output node (104a’s drain connected to output node providing Vout/Iout to load/capacitor 108) and a switching node (i.e., 104a’s source connected to a switching mid-node “sw1”, where 104ab are connected in series) and a low side power switch (104b) coupled between the switching node (i.e., 104b’s drain connected to the switching mid-node “sw1”, where 104ab are connected in series) and a reference ground (104b’s source connected to Gnd; Para 28), the control method comprising:
generating (when controller alone &/or in combination with state machine 112, is used to for driver 103 to provide respective gate/control signals for above respective taught switches; wherein note that 103 can be comprised of independent or more than one to drive respective switches) a high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) based on an AC input voltage (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28);
providing a first conduction path (1st conduction path using 200a, 2nd conduction path using 200b) … when the AC input voltage is in a negative half cycle (input voltage being AC input toggling between +1/2 cycle vs. -1/2 cycle; Para 28);
receiving (i.e., specifically 202a, 202b; wherein each being part of respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b) a first voltage indicative of a drain-source voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) of the high side power switch (104a) … the first conduction path (1st conduction path using 200a, 2nd conduction path using 200b);
generating a high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off) by comparing (i.e., specifically 204a, 204b; wherein each being part of respective 1st comparing circuit ‘202a, 204a’ controlling 104a, 2nd comparing circuit ‘202b, 204b’ controlling 104b) the first voltage (i.e., 1st voltage indicating of a drain-source voltage of 104a being diff amp 202a’s output used as one/- input in 204a; whereas, 2nd voltage indicating of a drain-source voltage of 104b being respective diff amp 202b’s output used as one/- input in 204b) with a first threshold voltage (i.e., 1st -2nd threshold voltages being 0V or any preferred reference voltage, used as another/+ input for respective 204a and 204b); and
generating (i.e., 1st logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200a (to enable or disable 114a’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110a or for current 116a), in order to control high-side switches 104a and 126a; whereas, in contrast 2nd logic circuit formed when specifically state machine 112 takes over to control ‘driver 103 and switches 200b (to enable or disable 114b’s included taught comparing circuit(s))’ due to fault sensing (such as, for temp 110b or for current 116b), in order to control low-side switches 104b and 126b) a high side drive signal (i.e., gate drive for 104a, or 126a, both being high-side switches) to control the high side power switch (104a) based on the high side control signal (i.e., gate drive for 104a, or 126a, both being high-side switches) and the high side off signal (i.e., 204a/204b operates based on respective diff, amp. 202a/202b’s output; wherein when + input of 204a/204b > -input of 204a/204b, 204 provided logic high output, causing respective switches 104a/104b to be on; and in contrast when + input of 204a/204b < -input of 204a/204b, 204 provided logic low output, causing respective switches 104a/104b to be off).
[Additional NOTE: in regards to use of 1st-2nd unidirectional devices and 1st-2nd conducting circuit, see, alternative above teaching of Li et al. (“Li”, US Pat 9941784), under allowable subject matters, regarding claims 1, 3-6.]
However, cited art(s) failed to teach, as a whole, a control method for a totem pole PFC circuit with a high side power switch coupled between an output node and a switching node and a low side power switch coupled between the switching node and a reference ground, the control method comprising: generating a high side control signal based on an AC input voltage; “providing a first conduction path through a first unidirectional device (i.e., Applicant’s Fig. 11; D1) when the AC input voltage is in a negative half cycle; receiving a first voltage indicative of a drain-source voltage of the high side power switch through the first conduction path; generating a high side off signal by comparing the first voltage with a first threshold voltage; and generating a high side drive signal to control the high side power switch based on the high side control signal and the high side off signal”.
Claim 20 is depending from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hu et al. (“Hu”, US Pub 2017/0040883) teaches (Fig. 2) the PFC circuit includes AC input voltage (i.e., 202 with +/- 1/2 AC cycle), input CLC filter (316, 215, 218) and controller (240) having to use pins (Para 39), for input, drain terminal (D) of a low-side switch (S1 230a), source terminal (S) of a low-side switch (S1 230a), feedback, gate drive, ground.
Hashimoto et al. (US Pub 2019/0326810) teaches (Fig. 9) various AC input detection controller (5a) for a bridgeless/totem PFC circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NUSRAT QUDDUS whose telephone number is (571)270-7921. The examiner can normally be reached on M-Th 9-4PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CRYSTAL L. HAMMOND can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NUSRAT QUDDUS/Examiner, Art Unit 2838