DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 09/08/2026 has been entered and fully considered.
Claims 1-20 are pending of which claims 1, 6, and 14 are independent and amended
The IDS(s) submitted on 11-14-2025 is being considered.
Internet Communications
Applicant is encouraged to submit a written authorization for Internet communications (PTO/SB/439, http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) in the instant patent application to authorize the examiner to communicate with the applicant via email. The authorization will allow the examiner to better practice compact prosecution. The written authorization can be submitted via one of the following methods only: (1) Central Fax which can be found in the Conclusion section of this Office action; (2) regular postal mail; (3) EFS WEB; or (4) the service window on the Alexandria campus. EFS web is the recommended way to submit the form since this allows the form to be entered into the file wrapper within the same day (system dependent). Written authorization submitted via other methods, such as direct fax to the examiner or email, will not be accepted. See MPEP § 502.03.
Response to Arguments
Applicants’ arguments filed on 09/08/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues in the Remarks of 09/08/2026 that the amended limitation reciting “…wherein the one or more CRC bits are appended after all of the plurality of CBs of the at least one of the one or more CB bundles;..” is not taught by the primary reference, Jayasinghe.
Applicant argues in the last two paragraphs of page 7 of the Remarks that Jayasinghe indicates that error detection bits for a code block group are generated before any code blocks of that group exists and cites paragraphs 28, 30, 33 and 35. Applicant appears to suggest that if the error detections bits for a code block group is generated prior to any code blocks of that group exists it cannot be appended after all of the plurality of CBs of the at least one CB bundle/group are formed.
Applicant continues to argue with respect to the amended limitation in claim 1 in the first two paragraphs on page 8 of the Remarks that Jayasinghe in paragraph 35 discloses that the error detection bits 412 are comprised in the last, kth, code block and is not necessarily appended after all the plurality of bits. Applicant attempts to strengthen the argument by citing Jayasinghe’s paragraph 35 suggests bits of the code block group may follow Jayasinghe’s error detection bits within the same code block.
Finally, Applicant admits Jayasinghe in paragraph 30 unequivocally teaches placing the error detection bits “per code block group instead of per code block” in order to reduce the number of CRC bits and Applicant indicates such teaching only shows how many error detection fields and not the position of those CRC bits relative to the code blocks.
Examiner’s Response: Examiner respectfully disagrees with all of the arguments presented by Applicant with respect to claim 1.
In the applicant-initiated interview the examiner communicated to Applicants’ representative that first the amended limitation did not change the scope of independent claim 1 and the above arguments were not persuasive.
To make the record clear, the amended limitation reciting “…wherein the one or more CRC bits are appended after all of the plurality of CBs of the at least one of the one or more CB bundles;..” is redundant and does not change the scope of claim 1 as claim 1 originally filled recites “…append one or more cyclic redundancy check (CRC) bits at an end of one or more code block (CB) bundles…”
Applicants’ argument in the last two paragraphs of page 7 of the Remarks pointing out that Jayasinghe indicates that error detection bits for a code block group are generated before any code blocks of that group exists is irrelevant because when the error detection bits are generated is not claimed. Even if claimed Jayasinghe can store the error detection bits and later append it to the end of the code block bundle/group. Further the examiner is not convinced that the CRC codes are generated earlier in Jayasinghe’s embodiments.
Applicant in the last argument with respect to claim 1, admits that a single set of CRC bits are allocated/associated per Code Block Group/Bundle is taught in Jayasinghe’s paragraph 30. What Applicant is not sure where the CRC bits are placed. Examiner suggests Applicant review Fig. 4 where Code Block Group1 410 has CRC 412 attached/appended to it. AHence Fig. 4 and paragraph 30 unequivocally teach the amended limitation.
Regarding claim 6, Applicant in the last paragraph of page 8 of the Remarks argues that the claim requires two quantities of CRC bits that pertain to the same code block and requires that “the first quantity of CRC bits is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle.” Applicant argues on page 9 of the Remarks that the examiner’s citations from paragraphs 34, 35, and 37.
Applicant further argues in the first paragraph of page 10, that Jayasinghe’s paragraph 34 discloses the 24-bit value for CRC as a CRC for Code Block Group and not for a Code Block and is not applicable to teach the limitation in question reciting
“…append a first quantity of cyclic redundancy check (CRC) bits at an end of at least one code block (CB) of a CB bundle comprising a plurality of CBs, wherein the first quantity of CRC bits is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle…”
Examiner’s Response: Examiner respectfully disagrees with Applicant’s arguments presented above with respect to claim 6.
The limitation reciting “…append a first quantity of cyclic redundancy check (CRC) bits at an end of at least one code block (CB) of a CB bundle comprising a plurality of CBs, wherein the first quantity of CRC bits is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle…” calls for a Code Block Group comprising a plurality of Code Blocks to have a CRC bits configured for at least one Code Block but can be for more than one Code Block and can be for the entire Code Block Group comprising more than one CB.
Hence the CBG level CRC in paragraph 34 applies and is configured for 24 bits as the CRC number of bits but per paragraph 34 the CRC bits can be varied and be configured to be greater than 24 bits depending on many criteria including number of Code Blocks. Hence Paragraph 34 teaches two CRC levels where one is 24 bits and the other can be configured to be variable to be higher than 24 bits. Even though Paragraph 34 refers to two Code block Groups the 24-bits CRC and the Variable CRC refer to one Code Block Group. It appears to the examiner that Applicant is claiming broadly and arguing narrowly.
Regarding claim 14, Applicant argues in the Remarks on page 11 with respect to independent claim 14, just like independent claim 16, the primary reference Cheng’277 fails to teach the required two quantities of CRC bits that pertain to the same code block and that “the first quantity of CRC bits is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle.” Applicant argues on page 11 of the Remarks that the examiner’s citations from Cheng’277’s paragraphs 17, 18, 26, 264 and 267 with respect to Fig. 6 fails to teach the required two quantities of CRC bits that pertain to the same code block and requires that “the first quantity of CRC bits is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle.”
Examiner’s Response: The examiner respectfully disagrees with Applicant’s arguments stated above with respect to claim 14.
Again, the examiner is interpreting the Code Blocks shown in Fig. 6 as CB0 and CB1 having CRC-B as a CRC with length of 24 bits per paragraph 17 and 26, But it can be configured for 32 bits length per paragraph 267 and 24-bits CRC is less than a configured 32 bits CRC fully meeting the limitations in question. Further, code block CB2 can have CRC-B or CRC-B+CRC-A again fully meeting the claimed broad limitations.
It appears once again to the examiner that Applicant is claiming broadly and arguing narrowly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jaysinghe et al (US 20200295873 A1, hereinafter referred to as Jay)
Regarding claim 1, Jay discloses an apparatus for wireless communications at a transmitter node (Fig. 10 and paragraphs 55-56), comprising:
at least one memory (Fig. 10 memory 20 paragraph 57) comprising instructions (Fig. 10 software instruction 22- paragraph 56); and
one or more processors (Fig. 10 processor 15 and controller 12 data circuitry 10 – paragraphs 59 and 61) , individually or collectively, configured to execute the
instructions and cause the apparatus to:
append one or more cyclic redundancy check (CRC) bits at an end of one
or more code block (CB) bundles, wherein each of the one or more CB bundles
comprises a plurality of CBs, wherein the one or more CRC bits are appended after all of the plurality of CBs of the at least one of the one or more CB bundles; (See Fig. 4 and paragraphs 30 and 33 wherein CRC 412 is appended to code block group/bundle (CBG) in Fig. 4, wherein CBG1 410 is appended with CRC 412 and so on and so forth till CBG N 414 appended with CRC 416. See paragraph 0033)
transmit at least one of the one or more CB bundles. (i.e. the code block group is transmitted by transmitting each of the code blocks contained in the code block group/bundle as in Fig. 2 block 206. See also paragraph 28. See Fig. 5A block 502 where each code block bundle/group is transmitted by forward the code blocks contained in the bundle. See paragraph 38)
Regarding claim 6, an apparatus for wireless communications at a transmitter node (Fig. 10 and paragraphs 55-56), comprising:
at least one memory (Fig. 10 memory 20 paragraph 57) comprising instructions (Fig. 10 software instruction 22- paragraph 56); and
one or more processors (Fig. 10 processor 15 and controller 12 data circuitry 10 – paragraphs 59 and 61) , individually or collectively, configured to execute the
instructions and cause the apparatus to:
append a first quantity of cyclic redundancy check (CRC) bits at an end of at least one code block (CB) of a CB bundle comprising a plurality of CBs, (See Fig. 4 and paragraphs 30 and 33 and 35 wherein in Fig. 4 each code block group/code bloc bundle have 1 to K Code Blocks(CBs) where each CB in the bundle/group a has a CRC attached), wherein the first quantity of CRC bits (per paragraph 35 and Fig. 4 all of the CRC associated with the CBs in the CBG except the last CB which is the Kth CB can be considered the first quantity of CRC ) is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle(Per paragraph 35 the CRC associated with Kth code block is the second quantity has the same as error detection bits 412 which is 24 bits per paragraph 0034 but can be variable and less than the configured or set 24 bits ) ; and transmit the CB bundle. (i.e. the code block group is transmitted by transmitting each of the code blocks contained in the code block group/bundle as in Fig. 2 block 206. See also paragraph 28. See Fig. 5A block 502 where each code block bundle/group is transmitted by forward the code blocks contained in the bundle. See paragraph 38)
Regarding claim 2, Jay discloses the apparatus of claim 1, wherein all of the plurality of CBs in the at least one of the one or more CB bundles are associated with a similar channel variation in a frequency domain. (Jay discloses CB blocks of the same CBG are associated to similar resources elements and therefore undergo same channel conditions. Per paragraph 32 Jay discloses the size of the transport block may depend on an amount of radio resources available to the source device, e.g. time-frequency resources scheduled by the access node. The size of the code block may depend on channel conditions between the source device and the sink device, e.g. signal-to-noise ratio (SNR) of a radio channel. A lower SNR or poorer channel conditions may require addition of more parity check bits, thus increasing the size of the code block. See also paragraph 19)
Regarding claim 4, Jay discloses the apparatus of claim 1, wherein: the one or more processors, individually or collectively, are configured to execute the instructions and cause the apparatus to compute a CB bundle CRC for the at least one of the one or more CB bundles based on all information bits of the plurality of CBs in the at least one of the one or more CB bundles, wherein the CB bundle CRC comprises at least the one or more CRC bits; (See Paragraph 35 the Kth code block of the CBG/ CB bundle kas a CR attached based on all information bits of the plurality of CBs in the form parity bits and systematic data bits of the CBs) the appending comprises appending the CB bundle CRC at an end of the at least one of the one or more CB bundles. (See Fig. 4 CRC appended to each CB)
Regarding claim 5, Jay discloses the apparatus of claim 1, wherein the one or more processors, individually or collectively, are configured to execute the instructions and cause the apparatus to: determine that a quantity of the one or more CB bundles for a transport block (TB) is equal to one (Per Paragraph 36 last sentence if the number of the bits of CB and CBG are equal then the transport block is one) ; and determine not to append a CB bundle CRC comprising at least the one or more CRC bits at an end of a single CB bundle when the quantity of the one or more CB bundles for the TB is equal to one. (Per paragraph 36 if the CB bits equals the bits of the CBG then TB equals one and there is no need to append a CBG CRC as the CB CRC suffices.)
Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US 20230188277 A1, hereinafter referred to as Cheng) .
Regarding claim 14, Cheng discloses a method (Figs. 1-15) for wireless communications at a transmitter node (Fig. 9 Network Node 16) , comprising: appending a first quantity of cyclic redundancy check (CRC) bits at an end of at least one code block (CB) of a CB bundle comprising a plurality of CBs (i.e. in Fig. 6 Transport Block comprises Code Blocks CB0, CB1 and CB2 and CRC-B of a first quantity is appended at the end of each blocks CB0 and CB1 per paragraph 0017 and CRC-B is 24 bits per paragraph 26) , wherein the first quantity of CRC bits is less than a second quantity of CRC bits configured for the at least one CB of the CB bundle (i.e. CB2 has CRC-B +CRC-A appended at the end of CB2 and CRC-B+CRC-A being 24 bits +24 bits = 48 bits is greater than 24 bits of CRC-B – see paragraphs 17, 26, and 267 and Fig. 6 and Figs. 19-22); and transmitting the CB bundle. (i.e. Fig. 16 S144 and Fig. 17 S152)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jay in view of Ye et al (US 20200235759 A1, hereinafter referred to as Ye)
Regarding claim 3, Jay discloses the apparatus of claim 1, but fails to disclose wherein in a quantity of the one or more CB bundles is based on a maximum allowable size of a CB and a quantity of CBs.
Ye, in the same endeavor, discloses wherein a quantity of the one or more CB bundles is based on a maximum allowable size of a CB and a quantity of CBs. (Per paragraph 236 indicates that several parameters may need to be determined for CBG generation and CBG level CRC attachment including the number of CGs in a TB , the number of CBs in each CBG and the CRC length for each CBG. Per paragraphs 92 and 135 and 223 discuss the CB size being maximum and claim 32)
In view of the above, having Jay’s error detection and channel coding of transport blocks and then given the well- established teaching of Ye’s techniques for LDPC coding, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Jay’s error detection and channel coding of transport blocks as taught by Ye’s techniques for LDPC coding, since Ye states in paragraph 234 that the modification results in increasing the throughput of the data transmissions by a group of blocks that share a common CRC to reduce overhead.
Regarding claim 7, Jay discloses the apparatus of claim 6, but fails to disclose wherein the second quantity of the CRC bits is based on a maximum allowable quantity of CRC bits for the at least one CB of the CB bundle.
Ye, in the same endeavor, discloses wherein the second quantity of the CRC bits is based on a maximum allowable quantity of CRC bits for the at least one CB of the CB bundle. (in paragraph 111 the maximum allowable quantity for CRC to be 24, 16 or other value for at least one CB and per paragraphs 249-251 and in particular per paragraph 236 and TB CRC 710 is based on a maximum allowable quantity of CRC bits for the at least one CB of the CB.)
In view of the above, having Jay’s error detection and channel coding of transport blocks and then given the well- established teaching of Ye’s techniques for LDPC coding, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Jay’s error detection and channel coding of transport blocks as taught by Ye’s techniques for LDPC coding, since Ye states in paragraph 234 that the modification results in increasing the throughput of the data transmissions by a group of blocks that share a common CRC to reduce overhead.
Regarding claim 9, Jay discloses the apparatus of claim 6, but fails to disclose where in a CRC length for each of the plurality of CBs of the CB bundle is same.
Ye, in the same endeavor, discloses where in a CRC length for each of the plurality of CBs of the CB bundle is same. (See Paragraph 124 in relation to Fig. 5 indicating the CRC length for each CB being equal.)
In view of the above, having Jay’s error detection and channel coding of transport blocks and then given the well- established teaching of Ye’s techniques for LDPC coding, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Jay’s error detection and channel coding of transport blocks as taught by Ye’s techniques for LDPC coding, since Ye states in paragraph 234 that the modification results in increasing the throughput of the data transmissions by a group of blocks that share a common CRC to reduce overhead.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jay in view of Cheng et al (US 2024 0204915 A1, hereinafter referred to as Cheng2).
Regarding claim 10, Jay discloses the apparatus of claim 6, but fails to disclose wherein a same CRC length for each of the plurality of CBs of the CB bundle is defined for all values of a delayed spread.
Cheng2, in the same endeavor, discloses wherein a same CRC length for each of the plurality of CBs of the CB bundle is defined for all values of a delayed spread.(See paragraph 349 indicates same CRC length for each CB for all values of delay)
In view of the above, having Jay’s error detection and channel coding of transport blocks and then given the well- established teaching of Cheng2’s techniques for CRC length determination, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Jay’s error detection and channel coding of transport blocks as taught by Cheng2’s techniques for CRC length determination, since Cheng2 states in paragraph 0006 that the modification results in improving transmission performance and data transmission efficiency.
Claim(s) 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ye et al (US 20200235759 A1, hereinafter referred to as Ye)
Regarding claim 15 , Cheng discloses the method of claim 14, but fails to disclose wherein the second quantity of the CRC bits is based on a maximum allowable quantity of CRC bits for the at least one CB of the CB bundle.
Ye, in the same endeavor, discloses wherein the second quantity of the CRC bits is based on a maximum allowable quantity of CRC bits for the at least one CB of the CB bundle. (in paragraph 111 the maximum allowable quantity for CRC to be 24, 16 or other value for at least one CB and per paragraphs 249-251 and in particular per paragraph 236 and TB CRC 710 is based on a maximum allowable quantity of CRC bits for the at least one CB of the CB.)
In view of the above, having Cheng's error detection and channel coding of transport blocks and then given the well- established teaching of Ye’s techniques for LDPC coding, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Cheng’s error detection and channel coding of transport blocks as taught by Ye’s techniques for LDPC coding, since Ye states in paragraph 234 that the modification results in increasing the throughput of the data transmissions by a group of blocks that share a common CRC to reduce overhead.
Regarding claim 17 , Cheng discloses the method of claim 14, but fails to disclose where in a CRC length for each of the plurality of CBs of the CB bundle is same.
Ye, in the same endeavor, discloses where in a CRC length for each of the plurality of CBs of the CB bundle is same. (See Paragraph 124 in relation to Fig. 5 indicating the CRC length for each CB being equal.)
In view of the above, having Cheng’s error detection and channel coding of transport blocks and then given the well- established teaching of Ye’s techniques for LDPC coding, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Jay’s error detection and channel coding of transport blocks as taught by Ye’s techniques for LDPC coding, since Ye states in paragraph 234 that the modification results in increasing the throughput of the data transmissions by a group of blocks that share a common CRC to reduce overhead.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20230188277 A1, hereinafter referred to as Cheng) in view of Cheng et al (US 2024 0204915 A1, herein after referred as Cheng’2 ).
Regarding Claim 18, Cheng discloses the method of claim 14, but fails to disclose wherein a same CRC length for each of the plurality of CBs of the CB bundle is defined for all values of a delayed spread.
Cheng2, in the same endeavor, discloses wherein a same CRC length for each of the plurality of CBs of the CB bundle is defined for all values of a delayed spread.(See paragraph 349 indicates same CRC length for each CB for all values of delay)
In view of the above, having Cheng’s error detection and channel coding of transport blocks and then given the well- established teaching of Cheng2’s techniques for CRC length determination, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Cheng’s error detection and channel coding of transport blocks as taught by Cheng2’s techniques for CRC length determination, since Cheng2 states in paragraph 0006 that the modification results in improving transmission performance and data transmission efficiency.
Allowable Subject Matter
Claims 8,11-13, 16, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HABTE MERED/Primary Examiner, Art Unit 2474
