Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED OFFICE ACTION
Claim Status
Claims 1-20 are pending in this application and are under examination in this Office Action. No claims have been allowed.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 7,
Claim 7 recites “a differential high-speed photodiode of the set of differential high-speed photo-diodes,” but no “set of differential high-speed photo-diodes” is introduced in claim 1 or elsewhere in the dependency chain. Accordingly, the metes and bounds of claim 7 are unclear because the claim relies on antecedent basis that is not present. Claim 7 therefore fails to particularly point out and distinctly claim the invention.
Regarding claim 17,
Claim 17 depends from claim 12, yet recites “the set of ground pours is connected to the ground plane ....” Claim 12, however, does not introduce any “set of ground pours”; that feature first appears in claim 16. Accordingly, claim 17 lacks proper antecedent basis and is indefinite because the claim fails to make clear which structure is allegedly connected to the recited ground plane.
Accordingly, claims 7 and 17 are rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for the obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As reiterated by the Supreme Court in KSR, and as set forth in MPEP 2141 (R-01.2024), II, the factual inquiries of Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), applied for establishing a background for determining obviousness under 35 U.S.C. §103, are summarized as follows:
Determining the scope and content of the prior art;
Ascertaining the differences between the prior art and the claims at issue;
Resolving the level of ordinary skill in the pertinent art; and
Considering objective evidence indicative of obviousness or non-obviousness, if present.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter disclosed in the prior art was created by another (i.e., not by the inventive entity) unless proven otherwise. Applicant is advised of the obligation under 37 C.F.R. § 1.56 to point out the inventor and effective filing dates of each claim, and any evidence of common ownership/assignment as of the effective filing date, so that the examiner may properly consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the claimed invention(s).
Claims 1,4,5,6,8,9 and 10 are rejected under 35 U.S.C. § 103 as being unpatentable over Nelson et al. (US20200219865A1) in view of Tu et al. (Optics Express, 2014), further in view of Tavlykaev et al. (US20030228081A1) and Jacques et al. (US20220404680A1).
Claim 1
Nelson teaches an optical communications assembly in a transceiver/co-packaged optics context, including a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC), where short electrical connections are formed between optoelectronic devices on the PIC and corresponding interface circuits on the EIC. Nelson expressly teaches that the interface circuits include transimpedance amplifiers for photodetectors and modulator drivers for modulators, and further teaches separate Rx and Tx PIC/IC implementations in which the Rx PIC includes photodetectors and TIAs and the Tx PIC includes modulators and modulator drivers “[0002] One or more aspects of embodiments according to the present disclosure relates to optoelectronic systems, and more particularly to a system and method for co-packaging optics and transceiver components. [0034] Referring to FIGS. 1A and 1B, in some embodiments, short electrical connections between (i) a component (e.g., a photodetector and / or modulator) on a photonic integrated circuit 105 (PIC) and (ii) a component or circuit (e.g., a transimpedance amplifier and / or modulator driver) on an electronic integrated circuit 110 may be formed by flip - chip bonding the photonic integrated circuit 105 to the electronic integrated circuit 110 to form a flip - chip assembly. The photonic integrated circuit may include a substrate (e.g., a silicon substrate) having a front surface (the upper surface of the photonic integrated circuit 105, in the orientation of FIG. 1A), on or in which may be V - grooves (for passive alignment to an optical fiber, not shown for ease of illustration), optical waveguides, optoelectronic devices (e.g., photodetectors and modulators), and one or more metal layers forming conductive traces for routing electrical signals to and from the optoelectronic devices. The optical waveguides may include mode converters (e.g., tapered sections) e.g., for converting between a mode that may propagate in a 3 - micron wide waveguide and (i) a mode that may propagate in a single - mode fiber, or (ii) a mode that may produce a useful intensity distribution in an optoelectronic device. The electronic integrated circuit 110 may have a length between 5 mm and 15 mm (e.g., a length of 10.2 mm) and a width between 2 mm and 9 mm (e.g., a width of 4.4 mm) and the photonic integrated circuit 105 may have a length between 7 mm and 30 mm (e.g., a length of 15 mm) and a width between 3 mm and 11 mm (e.g., a width of 5.5 mm). [0035] The electronic integrated circuit 110 may be a silicon integrated circuit, and the front surface of the electronic integrated circuit 110 (the lower surface, in the orientation of FIG. 1A) may include interface circuits for interfacing with the optoelectronic devices, e.g., transimpedance amplifiers for amplifying photocurrents generated by photodetectors on the photonic integrated circuit 105, and modulator drivers for driving modulators (e.g., electro absorption (EA) modulators) on the photonic integrated circuit 105. Each of these interface circuits may be part of a respective high-speed channel on the front surface of the electronic integrated circuit 110. Each high-speed channel may include (in addition to the interface circuit), a serial receiver circuit (for a high-speed channel connected to a modulator) or a serial transmitter circuit (for a high-speed channel connected to a photodetector). These serial receiver and transmitter circuits may be, for example, XSR or USR receiver or transmitter circuits, and they may be used for exchanging data with a digital electronic circuit (e.g., a switch application specific integrated circuit (ASIC)) as discussed in further detail below. Each high-speed channel may further include circuitry for connecting the interface circuit to the serial receiver circuit or serial transmitter circuit (e.g., a clock and data recovery circuit connected to the transimpedance amplifier, in the case of a high-speed channel connected to a photodetector). The circuits on the electronic integrated circuit 110 may occupy a relatively small fraction (e.g., less than one half or less than one quarter) of the area of the electronic integrated circuit 110, and in some embodiments the excess area may be employed, e.g., to fabricate a microcontroller on the first portion 115 of the electronic integrated circuit 110…...[0043] In some embodiments, all of the optoelectronic devices on a photonic integrated circuit 105 are the same. For example, on a photonic integrated circuit 105 that may be referred to as a receiving PIC (Rx PIC), all of the optoelectronic devices are photodetectors, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as an Rx IC), are all transimpedance amplifiers. Similarly, on a photonic integrated circuit 105 that may be referred to as a transmitting PIC (TX PIC), all of the optoelectronic devices may be modulators, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as a Tx IC), are all modulator drivers. [0044] FIG. 4 shows a fabrication flow, in some embodiments. A Tx IC is prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing, and an Rx IC is similarly prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing. Wafer back grinding may be employed to reduce overall thickness of the Tx IC or Rx IC while also reducing case to junction thermal resistance between the IC and ASIC heat sink discussed in further detail below. A TX PIC is prepared using steps including III - V micro - transfer printing (To place the modulators, which may be III - V devices, on the PIC), bumping (with the copper pillar bumps 140), and dicing, and an Rx PIC is prepared using steps including bumping (with the copper pillar bumps 140), and dicing. The Tx IC is then soldered to the Tx PIC to form an assembly that may be referred to as a “Tx sub assembly”, and the Rx IC is then soldered to the Rx PIC to form an assembly that may be referred to as a “Rx sub assembly”. The Tx sub assembly and the Rx sub assembly are then secured to a carrier 315, and fiber pigtails are attached to the PICs, to form an assembly that may be referred to as an optical engine. In these sub-assemblies the PIC may be substantially thicker than the IC especially in the case when the IC is subject to wafer - back grinding during wafer preparation. A thicker PIC reduces warpage to support fine pitch bump assembly in 135 and improves component rigidity after fiber pigtail assembly. In some embodiments, the photonic integrated circuit 105 has a thickness between 500 microns and 1000 microns, e.g., about 680 microns, and the electronic integrated circuit 110 has a thickness between 100 microns and 700 microns, e.g., 580 microns. [0045] One or more optical engines may be used to provide optical interfaces to a digital integrated circuit 505 (e.g., a switch ASIC) as shown in FIG. 5. An ASIC heat sink 510 conducts heat away from the digital integrated circuit 505 (e.g., to a heat - pipe - based cooling system). A top clamp 515 (together with a bottom portion 517) secures the optical engine and the compressible membrane connector 305 to the printed circuit board 310 and conducts away heat flowing through the carrier 315 from the optical engine; the top clamp is thermally connected to a removable heat sink section 520 through a layer of compliant thermal interface material 525. In the embodiment of FIG. 5, the carrier 315 lacks the alignment ridges 320 shown in FIG. 3; in other embodiments, however, one or more alignment ridges 320 may be present, and the structure may otherwise be similar to that illustrated in FIG. 5. The printed circuit board 310 may form the substrate of a package, including the elements illustrated in FIG. 5, that may be secured and connected to another printed circuit board (e.g., a motherboard) by an array of conductors 530 on the lower surface of the printed circuit board 310. Such a motherboard may have a hole or cutout to accommodate the bottom portion 517 of the clamp. A second beachfront 540 may be used to accommodate another optical engine (not shown), or, for example, an edge connector for making serial electrical connections to the digital integrated circuit 505 (as discussed in further detail below)” [Nelson ¶¶ [0002], [0034] - [0035], [0043] - [0045]; Figs. 1A-5.].
Nelson further teaches, or at least strongly suggests, an optical communications device including a silicon-photonics-type transceiver environment having a set of receivers, a set of transmitters, and a set of drivers associated with PIC optoelectronic devices. Nelson further teaches close conductive interconnection between the PIC and EIC through metal bumps in an overlap region so that transmitter and receiver circuitry operate in a compact integrated package “…... [0036] In some embodiments, the electrical connection between an optoelectronic device on the photonic integrated circuit 105 and the corresponding interface circuit (e.g., amplifier) on the electronic integrated circuit 110 may have a length of less than 500 microns, or less than 200 microns, or less than 100 microns. In some embodiments, the length may be nearly as small as the height of the metal bumps 140 (e.g., copper pillar bumps, discussed in further detail below) forming connections between the photonic integrated circuit 105 and the electronic integrated circuit 110. In some embodiments, the analog portion of a receiving channel (e.g., a photodetector and a transimpedance amplifier connected to the photodetector) may have a bandwidth (e.g., a 3 dB bandwidth) of at least 10 GHz, or at least 20 GHz, or at least 60 GHz, where the bandwidth is defined in terms of the transfer function from amplitude modulation on light received by the photodetector, to the corresponding signal at the output of the transimpedance amplifier. The bandwidth may be a relatively sensitive function of the aforementioned interconnect length between the PIC 140 an IC 110, e.g., a relatively small increase in the interconnect length may result in a significant decrease in bandwidth. Similarly, the analog portion of a transmitting channel (e.g., a modulator and a drive amplifier in the modulator driver connected to the modulator) may have a bandwidth (e.g., a 3 dB band width) of at least 10 GHz, or at least 20 GHz, or at least 60 GHz, where the bandwidth is defined in terms of the transfer function from an electrical signal at the input of the drive amplifier to the corresponding amplitude modulation produced by the modulator. The bandwidth may be a relatively sensitive function of the aforementioned interconnect length between the PIC 140 an IC 110, e.g., a relatively small increase in the interconnect length may result in a significant decrease in bandwidth. In some embodiments, the configuration of FIGS. 1A and 1B makes it unnecessary for the electronic integrated circuit 110 (or the photonic integrated circuit 105) to have a redistribution layer on either surface; it may be sufficient instead to have a relatively small number of patterned metal layers (e.g., 10 or fewer metal layers) on one or both of the electronic integrated circuit 110 and the photonic integrated circuit 105. [0037] The photonic integrated circuit 105 and the electronic integrated circuit 110 may be offset from each other so that each of the photonic integrated circuit 105 and the electronic integrated circuit 110 overhangs the other, as illustrated in FIG. 1A. In particular, a first portion 115 of the electronic integrated circuit 110 may overhang a first edge 120 of the photonic integrated circuit 105 and a first portion 125 of the photonic integrated circuit 105 may overhang a first edge 130 of the electronic integrated circuit 110. Referring to FIG. 1B, the photonic integrated circuit 105 and the electronic integrated circuit 110 may overlap in an area of overlap 135. In some embodiments, the first portion 125 of the photonic integrated circuit 105 and the first portion 115 of the electronic integrated circuit 110 are on opposite sides of the area of overlap 135 (as shown, for example, in FIG. 1B) and the area of overlap 135 is generally between the first portion 115 of the electronic integrated circuit 110 and the first portion 125 of the photonic integrated circuit 105. In other embodiments the relative positions may be different; for example, the first portion 115 of the electronic integrated circuit 110 may extend away from the area of overlap 135 in a first direction and the first portion 125 of the photonic integrated circuit 105 may extend away from the area of overlap 135 in a second direction, perpendicular to the first direction. [0038] In the area of overlap 135 the photonic integrated circuit 105 and the electronic integrated circuit 110 may be secured together and electrically connected through a plurality of metal bumps. For example, a plurality of solder topped copper pillar bumps 140 (e.g. Cu / Ni / SnAg bumps) may be formed on the front surface of the photonic integrated circuit 105, and a corresponding plurality of pads 145 (e.g., Ni / Au pads) may be formed on the front surface of the electronic integrated circuit 110; the photonic integrated circuit 105 may then be soldered to the electronic integrated circuit 110, with each solder - topped copper pillar bump 140 of the photonic integrated circuit 105 in the area of overlap being soldered to a respective pad on the electronic integrated circuit 110. The soldering may be performed, for example, using thermocompression bonding. [0039] Each of the copper pillar bumps 140 may have a diameter of between 25 um (microns) and 100 um and a height of between 25 um and 100 um. Each of the copper pillar bumps 140 may be formed on a pad opening (e.g., an opening in an insulating (e.g., silicon dioxide) layer on the front surface of the photonic integrated circuit 105) having a diameter of between 10 um and 70 um. [0040] Referring to FIG. 2A, the copper pillar bumps 140 in the area of overlap 135 may be on a grid (e.g., a grid with a pitch between 50 um and 150 um) substantially filling the area of overlap 135, which may be rectangular as shown. In some embodiments, the corner bumps may be omitted as shown, for stress relief. The pads 145 (e.g., Ni / Au pads) on the electronic integrated circuit 110 may have a diameter exceeding 100 um (in an embodiment in which the pitch of the grid exceeds 100 um). The pitch of the copper pillar bumps 140 may be chosen based on design channel count and density. For example, reducing bump pitch (and channel pitch accordingly) reduces the width of the PIC 105 and electronic integrated circuit 110. A reduction in chip width increases bandwidth density and reduces overall product form factor within high volume manufacturing limits. For example, in some embodiments the optical engines dis cussed herein are populated on the edge of the printed circuit board 310 which may form the substrate of the switch ASIC package (FIG. 5. This substrate form factor is ultimately determined by the widths of the PIC 105 and the electronic integrated circuit 110, which is dependent on bump pitch. Furthermore, reducing the substrate form factor improves the aforementioned serializer - deserializer performance and reduces cost in high volume. This is discussed in further detail below. Each of the high-speed channels 150 may be connected by a pair of conductive traces on the front surface of the electronic integrated circuit 110 to a respective pair of pads, or "connector bumps” (e.g., Ni / Au pads) in the first portion 115 of the front surface of the electronic integrated circuit 110 as part of a connection (e.g., an XSR or USR connection, or other suitable serial electrical connection) to, e.g., a switch ASIC, as discussed in further detail below. The pads in the first portion 115 of the front surface of the electronic integrated circuit 110 may be similar to, although they may have different dimensions from, the pads on the front surface of the electronic integrated circuit 110 in the area of overlap 135. FIG. 2B shows an example of a candidate pin assignment for the connector bumps. The corner connector bumps may be absent (as shown in FIG. 2A) or present (as shown in FIG. 2B) ………” (Nelson ¶¶ [0034] - [0040], [0043] - [0045]; Figs. 1A-4.).
Nelson does not expressly disclose that the transmitter-side modulators are specifically a set of Mach-Zehnder modulators having ground pours and bonding wires at least partially surrounding the MZMs so as to electromagnetically confine transmission from each transmitter. However, Tu expressly teaches a silicon Mach-Zehnder interferometer optical modulator with a shield coplanar waveguide transmission-line electrode design, and teaches that the shield-CPW suppresses parasitic slot-line mode and improves both electrical bandwidth and electro-optical bandwidth. Thus, Tu teaches the core concept of shielding a silicon MZM transmission structure in order to confine and control RF propagation around the modulator “With a shield coplanar waveguide (CPW) transmission line electrode design was demonstrated. This shield-CPW electrode suppresses the signal distortion caused by the parasitic slot-line (SL) mode and improves the electrical bandwidth and the electro-optical (EO) bandwidth. With the shield-CPW electrodes and 5.5 mm-long phase shifters, the silicon MZI optical modulator delivered an EO bandwidth of above 24 GHz and a V π = 3.0 V was achieved at λ = 1310nm. When modulated at 28-Gb/s data rate, it achieved an extinction ratio of 5.66 dB under a driving voltage of V pp = 1.3 V, corresponding to a power consumption of 0.8 pJ/bit……. The emerging silicon photonics technology has received intense research and development efforts by the optical communication industry due to its superior advantages such as small die sizes, low cost and high integration capability [1–4]. Silicon modulator is one of the most important components for high quality and large volume of data uploading in the future fiberoptic network. Since the comprehensive study of electro-optical (EO) effect in silicon material in 1987 [5], silicon EO modulator has achieved remarkable progress. Recently with reverse biased p-n junction, the data rate of silicon optical modulator has reached over 50-Gb/s for both of 1310 nm and 1550 nm [6–10]. The aggregated data rate and modulation efficiency may be further increased by utilizing the amplitude-shift keying (ASK) and phase-shift keying (PSK) technologies [11, 12]. Chip-scale integration of silicon modulators with wavelength division multiplexing (WDM) multiplexers as well as III-V lasers were also demonstrated [13,14]. For all practical applications, low power consumption and driving voltage are critical performance requitement. That is why in the past, optical modulator fabricated by LiNbO3 and compound material was usually made to have a long phase shifting length. However, such long phase shifter also introduces high microwave loss and velocity mismatching which limit the EO bandwidth. Typically, travelling-wave electrode is implemented to reduce the driving voltage while maintain high EO bandwidth. Coplanar waveguide (CPW) and slot-line (SL) waveguide are two of the most common travelling-wave electrode designs. Between them, CPW is more popular for the advantages of low dispersion, low radiation and the ease of shunt and series connections. However, SL mode can be triggered by the asymmetric CPW electrodes, which in turn becomes the main obstacle for its implementation in practice [15]. When applying CPW electrodes onto optical modulator, the parasitic SL mode can induce strong microwave reflection which suppresses the bandwidth of the modulator. A simple wire-bonding method has been utilized to eliminate this parasitic SL mode [16], but it is not effective and also this approach is not compatible with CMOS process [17]. An air bridge technique, where a shield metal layer is added on top of CPW, has been demonstrated to be more effective for suppressing of this parasitic SL mode [18]. Based on this, shield-CPW electrode has been utilized on LiNbO3 modulators [19]. Nevertheless, there is no report on applying this shield-CPW electrode on silicon modulators. In this work, we implemented a shield-CPW electrode to suppress the unwanted SL modes in silicon modulator. For illustration, with a 5.5 mm-long phase shifter, the driving voltage V pp is reduced to be less than 1.3 V in a single-end MZI silicon modulator to achieve a 28-Gb/s data rate and above 24 GHz EO-S21 −3 dB bandwidth with a power consumption of 0.8 pJ/bit……...” [Tu, Abstract, p. 2-3, Fig. 1.].
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However, within analogous art, Tavlykaev teaches, in an MZI modulator context, a coplanar waveguide structure that includes a hot central electrode and two ground planes or electrodes formed on opposite sides of the central electrode “The present invention relates to an optical modulator including an optical waveguide, and at least one CPW-to-CPS transition. The CPW segments include a hot electrode; and a ground plane disposed on each side of the hot electrode, and they share a ground plane. The CPS Segment extends along an interaction length of the modulator. In one embodiment, two driving Signals are applied So that the modulator operates as a dual-drive modulator. In another embodiment, a domain-inverted region is formed in a Substrate of the dual-drive modulator to overlap with one arm of the optical waveguide (MZI) and invert a sign of a phase shift induced in that arm. Finally, a fixed chirp can be introduced into the dual-drive modulator by asymmetrically positioning the interferometer arms into gaps of the CPW segments with respect to the hot electrode, and by employing unequal width gaps in the CPW segments.” [Tavlykaev, Abstract; Figs. 1 and 4.]
Tavlykaev additionally teaches bonding wires (air bridges) used to connect one ground plane with adjacent ground planes at transitions in order to provide current paths and ensure efficient electromagnetic transformation of the microwave mode “[0005] In the optical waveguide structure of a modulator, and as shown in FIG. 1, a Mach-Zehnder interferometer (MZI)102 is typically disposed. A Mach-Zehnder modulator includes an interferometer 102 having an input waveguide 103 and arms 104,105 that branch from the input waveguide 103, and an output waveguide 106 at the junction of the arms 104, 105. Typically, an optical signal is directed into and propagates in the input waveguide 103, and is split between the arms 104, 105 so that approximately one-half of the input optical Signal propagates in each of the interferometer arms 104,105. A modulating signal is applied to the modulator in order to change the effective refractive indices of the interferometer arms and to introduce a relative phase shift between the two optical Signals. The phase-shifted optical Signals combine at the output waveguide 106 and produce intensity modulation. Depending on the relative phase shift between the two optical Signals, they may interfere either constructively or destructively. The output of the modulator is thus, an intensity modulated optical Signal. A relative phase shift between the optical signals in the arms 104, 105 of approximately It is required to Switch the output of the modulator between adjacent on and off States. [0006] The electrode structure shown in FIG. 1 is a microwave Coplanar Waveguide (CPW) aligned with respect to the waveguide Structure in Such a way that the interferometer arms 104,105 are positioned in the electrode gaps 107 and run alongside the gap edges (in X-cut devices). A CPW electrode structure includes a hot central (signal) electrode 108 and two ground planes or electrodes 109,110 formed on opposite sides of the central electrode 108. Microwave (modulating) signals are provided to the signal electrode 108 from a microwave Source 111, via a connector and a microwave cable. The widths of the gap 107 and hot electrode 108 are tapered at the input and output. Advantageously, a CPW structure with properly chosen widths of the gap 107 and hot electrode 108 at the modulator input has a microwave field distribution closely matching that of a coaxial cable connecting the modulator to the microwave Source 111. [0007] FIG. 1 shows an intensity modulator 100 with the So-called “push-pull configuration, wherein the electric field crossing one interferometer arm 104 is opposite to that crossing the other 105. AS Such, the electro-optic phase shifts induced in the two arms 104, 105 are of equal magnitude but opposite sign. Effectively, the intensity modulator 100 incorporates two phase modulators, represented by the two arms 104, 105, which are driven 180 degrees out of phase with respect to each other. The outputs of the two-phase modulators are combined to result in an intensity modulation that depends on the relative phase difference between the arms 104, 105. In the push-pull configuration, the phase difference doubles compared to the phase shift in each arm and the half-wave Voltage of the modulator is therefore halved, which represents a significant advantage over other Schemes” [Tavlykaev ¶¶ [0005] - [0007]].
Tavlykaev further teaches ground structures disposed on opposite sides of the modulator electrode and bond-wire connections between adjacent ground structures “[0036] FIG. 4 illustrates one embodiment of the present invention, which is an optical (phase) modulator 400, including a channel optical waveguide 409 and two CPW segments 401, 402. The CPW segments provide mode symmetry when RF is coupled into and out of the electrode structure. The RF traverses a (i.e., asymmetric) CPS line segment 403, which extends along the interaction length 404 of the modulator 400, and imparts electro-optic modulation to the optical waveguide 409. Each CPW segment 401, 402 includes a hot central (signal) electrode 405 and two ground planes or electrodes 406, 407, 414 formed on opposite sides of the central electrode 405. Bonding wires 411 are used to connect ground plane 407 with ground planes 406, 414 of CPW sections 401, 402 at their interfaces with CPS section 403. This is done, in accordance with the principles of microwave theory, in order to provide current paths from/to the two ground CPW planes 406, 414 to/from the single ground plane 407 of the CPS section and to ensure, in terms of electro-magnetic wave distributions, efficient transformation of the CPW microwave mode to that of the CPS, and Vice versa. [0037] The phase modulator according to one embodiment of the present invention, as shown in FIG. 4, includes advantages previously achieved individually with CPW and CPS structures. Indeed, the CPW segments 401, 402 ensure efficient coupling to an input coaxial cable 408 and a termination circuitry, if any (not shown in FIG. 4). [0038] According to microwave theory, good overlap between the microwave field distribution of a coaxial cable and that of a CPW can be achieved, by a proper choice of the gap and hot electrode width of the CPW segment, which results in efficient electromagnetic coupling. At the same time, the CPS segment 403 can provide efficient modulation through good electro-optical overlap and be made to have impedance close to that of the feed line 408, by a proper choice of the gap 415 and hot electrode 405 width of the CPS Segment. [0039] Furthermore, efficient conversion of the RF power from the gap 412 not used for modulation to the other, can be achieved by employing bond wires (air bridges) 411 at the CPW/CPS transitions, as described above. For optimum operation, the gaps 412,415 and hot electrode 405 widths of the CPS and CPW segments should be designed to provide good impedance and mode matching between them. AS an example, the hot electrode widths for the CPW and CPS Segments can be chosen to be continuous acroSS the transition, as shown in FIG. 4. In this case, CPW gap 412 should be made wider than CPS gap 415, since if they were equal, the CPW segments 401, 402 would have a lower impedance than the CPS Segment 403, causing an impedance discontinuity at the transitions and microwave reflection. If the difference between gapS 412 and 415 is significant enough to cause microwave mode mismatch and radiation loSS, chamfered transitions can be employed, as is well known and detailed in microwave techniques. If the CPW/CPS transition is optimized, following these rules, the conversion efficiency is known to exceed 90%.” [Tavlykaev ¶¶ [0036] - [0039]].
Further, Jacques teaches a driver chip wire-bonded to a TW-MZM structure, including a first wire-bond, a second wire-bond, and a third wire-bond between electrodes associated with the transmission lines of the Mach-Zehnder modulator “[0003] In one aspect , in general , an apparatus comprises : an electro - optic material ; an optical waveguide structure forming a Mach - Zehnder interferometer in proximity to the electro - optic material , where the Mach - Zehnder interferometer includes a first optical waveguide arm and a second optical waveguide arm ; a first electrical input port configured to receive a first drive signal ; a second electrical input port configured to receive a second drive signal that has a negative amplitude relative to the first drive signal ; a first transmission line configured to propagate a first electromagnetic wave over at least a portion of the first optical waveguide arm to apply an optical phase modulation to an optical wave propagating in the first optical waveguide arm according to an electro - optic modulation of a portion of the electro - optic material ; a second transmission line configured to propagate a second electromagnetic wave over at least a portion of the second optical waveguide arm to apply an optical phase modulation to an optical wave propagating in the second optical waveguide arm according to an electro optic modulation of a portion of the electro - optic material ; and a drive signal interconnection structure configured to provide a first electrical connection between the first electrical input port and an electrode shared by the first and second transmission lines , and a second electrical connection between the second electrical input port and respective electrodes of the first and second transmission lines , where the drive signal interconnection structure is configured to preserve relative phase shifts between the first and second drive signals ; where an input impedance at the first electrical input port and an input impedance at the second electrical input port are substantially equal to each other,. [0008] The drive signal interconnection structure comprises a first wire - bond between the first electrical input port and the electrode shared by the first and second transmission lines , and a second wire - bond between the second electrical input port and a metal trace that is contiguous with each of the respective electrodes of the first and second transmission lines” [Jacques ¶¶ [0003], [0008], Figs. 1A-1D, 4A.].
Jacques also teaches that the driver chip may include optional ground contacts, and that the interconnection techniques are applicable to a G-S-S-S-G electrode configuration having ground electrodes on both sides “[0012] The drive signal interconnection structure comprises a first wire - bond between the first electrical input port and the electrode shared by the first and second transmission lines, a second wire - bond between the second electrical input port and an electrode of the first transmission line , and a third wire - bond between the electrode of the first trans
mission line and an electrode of the second transmission line. [0013] The third - wire bond is bonded at an angle selected to preserve relative phase shifts between the first and second drive signals. [0014] The drive signal interconnection structure comprises a first wire - bond between the first electrical input port and the electrode shared by the first and second transmission lines , a second wire - bond between the second electrical input port and an electrode of the first transmission line , a plurality of wire - bonds between the electrode of the first transmission line and an electrode of the second transmission line. [0048] Some of the described approaches are directed to achieving optimal interconnection between a differential driver and a modulator that has a radio frequency ( rf ) transmission line electrode configuration of the type S - S – S or G - S - S - S - G ( e.g. , as shown in FIGS . 1A - 1D ) . In some of the examples described herein , the S - S - S electrode configuration is used to show implementations of a differential drive electrode configuration for an E - O crystal TW - MZM , but the techniques described herein can also be applied to G - S – S - S - G electrode configuration , and other integrated modulator technologies that may benefit from S - S - S or G - S - S - S – G differential electrode configurations , such as SOH modulators . In some implementations, the S signal from a 2 – port driver is split on - chip in interconnection circuitry that is fabricated on , or bonded to , the same die as the MZM . In other implementations , a 3 - port driver provides an S signal and two S signals at respective driver output ports , and the S signal is split within the driver ( e.g. , as shown in FIG . 2A ) , and in some implementations , at the transistor level ( e.g. , as shown in FIG . 2B ) . In some implementations , a passive termination circuit can be used to properly bias the driver output signals for an open - collector ( OC ) architecture . In either the 2 - port or 3 - port driver implementations, the connections between the driver and the modulator can be formed using any of a variety of techniques, including wire - bonds , or a controlled collapse chip connection , also called flip - chip or C4 connection . Also , the output ports of the driver may serve as input ports of the TW - MZM , including any wire - bonds or other structures extending to various portions of the TW - MZM” [Jacques ¶¶ [0012] - [0014],[0048]].
Jacques further, provides additional evidence of practical driver-to-MZM wire-bond implementations with ground-contact architecture and bond wires spanning between opposite-side electrodes “[0055] Referring to FIG . 4A , a driver chip 400 is connected to an optoelectronic chip 402A by a drive signal interconnection structure 404A that is formed by wire – bonds 406 and 408 and metal structures within a single metal layer of the optoelectronic chip 402A . A TW - MZM is formed on the optoelectronic chip 402A by structures that include a center electrode 410 , outer electrodes 411 and 412 , and a Mach - Zehnder interferometer with waveguide arms 413 and 414. The wire - bond 406 is formed between an S contact pad of the driver chip 400 and an outer electrode contact pad 415 in a metal layer of the optoelectronic chip 402A . A V – shaped metal trace connection 416 in the same metal layer connects to each of the outer electrodes 411 and 412. The wire – bond 408 , which is longer than the wire - bond 406 , is formed between an S contact pad of the driver chip 400 and a center electrode contact pad 418. The lengths of the wire – bonds 406 and 408 are selected so that the propagation delay across a wide bandwidth for rf signals between the driver and the beginning of the transmission lines of the TW - MZM are substantially equal . This propagation delay matching pre serves relative phase shifts between the S and S signals . In some implementations , wedge - bonds can be installed to achieve relatively precise relative timing for matching the propagation delay . The driver chip 400 can also optionally include ground contacts ( G ) as shown in this example . [0056] Between the contact pad 418 and the center electrode 410 is an impedance buffer 420 , which compensates for an impedance difference between the impedance for the parallel combination of split S signals and the impedance of the single S signal at the input ports of the optoelectronic chip 402A , where the input ports are defined at the beginning of the wire - bonds 406 and 408 , respectively . Alternatively , in other examples , there can be impedance buffers between the ends of the v - shaped metal trace connection 416 and the outer electrodes 411 and 412 , instead of , or in addition to the location shown in this example . The change
in impedance that is provided by the impedance buffer 420 can be configured based on various structural factors , including the exact coplanar waveguide geometry of the transmission lines , such as the width and / or spacing of the three metal traces that form the electrodes of the transmission lines . The impedance buffer 420 can be formed from one or more layers of resistive material , and / or conductive material , and can include circuit components such as resonant stubs or transformers . The components , materials and / or structural geometries can be configured to provide inductance and / or capacitance that may be needed to compensate for any impedance mismatch over a broad rf signal band width . An impedance buffer 420 may not be needed in some implementations if the input impedances are matched based on the geometries of the electrodes 410 , 411 , and 412. For example , if the outer electrodes 411 and 412 are each half the width of the center electrode 410 so that their resistance is about twice as high , then their equivalent combined parallel impedance at the input port for the S signal may be substantially equal to the impedance at the input port for the S signal . Or , more generally , the outer electrodes 411 and 412 may have an equivalent parallel characteristic impedance Z that is substantially equal to the characteristic impedance Zo of the center electrode 410” [Jacques ¶¶ [0055] - [0056]].
It would have been obvious to a person of ordinary skill in the art, at the time the invention was made, to modify Nelson’s compact PIC/EIC transceiver package with Tu’s shielded silicon MZM electrode arrangement and with Tavlykaev’s and Jacques’s opposite-side ground structures and bond-wire interconnections. Nelson already teaches the highly integrated transmitter/receiver package context in which short, high-bandwidth electrical paths are desired. Tu expressly teaches that shielding around a silicon MZM suppresses unwanted modes and improves bandwidth. Tavlykaev teaches that bond wires between adjacent ground structures provide current-return paths and proper electromagnetic transformation, and Jacques shows that such wire-bonded MZM drive arrangements were practical in differential-drive modulator implementations with optional ground contacts. Combining these teachings would have predictably resulted in a SiP transceiver in which the MZM transmission structures are at least partially surrounded by ground pours/ground structures and bonding wires so as to confine electromagnetic propagation, reduce parasitic coupling, improve signal integrity, and preserve receiver performance in a dense co-packaged transceiver environment. The combination therefore would have been a predictable use of prior-art elements according to their established functions.
Further, a person of ordinary skill in the art would have recognized strong design pressure in a dense SiP transceiver package to control the high-swing RF fields launched from each driver into each MZM so that those fields do not radiate into adjacent channels or receiver circuitry. Nelson supplies the compact co-packaged transmitter/receiver environment in which such isolation is especially important, Tu teaches that shielded MZM transmission structures improve bandwidth by suppressing parasitic modes, Tavlykaev teaches that adjacent grounded structures bridged by bond wires provide proper return-current paths and mode control, and Jacques shows that those same concepts were practical in real driver-to-MZM wire-bond implementations. Thus, the claimed arrangement results from the predictable combination of known shielding, grounding, and wire-bond interconnect techniques to solve the known RF-integrity problem in compact optical transceivers, with the expected benefits of reduced parasitic coupling, improved impedance control, improved EO bandwidth, and better transmitter/receiver isolation.
For purposes of this rejection, the claimed “ground pours” are reasonably read on laterally disposed grounded conductive regions, ground planes, or shield electrodes formed in or on the PIC-side modulator structure adjacent the MZM transmission path. Likewise, the phrase “at least partially surrounding” does not require a completely closed cage; under the broadest reasonable interpretation it is satisfied by grounded conductive structures and bond-wire bridges that bracket, fence, or otherwise bound the driven MZM path on multiple sides so as to confine the electromagnetic field relative to surrounding circuitry.
Claim 4
With respect to claim 4, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 4 additionally requires that the set of bonding wires connect adjacent ground pours of the set of ground pours on a photonic integrated circuit. However, within analogous art, Tavlykaev expressly teaches bonding wires used to connect one ground plane with adjacent ground planes of CPW sections at their interfaces, thereby teaching bond-wire connection between adjacent ground structures on the modulator structure “[0036] FIG. 4 illustrates one embodiment of the present invention, which is an optical (phase) modulator 400, including a channel optical waveguide 409 and two CPW segments 401, 402. The CPW segments provide mode symmetry when RF is coupled into and out of the electrode structure. The RF traverses a (i.e., asymmetric) CPS line segment 403, which extends along the interaction length 404 of the modulator 400, and imparts electro-optic modulation to the optical waveguide 409. Each CPW segment 401, 402 includes a hot central (signal) electrode 405 and two ground planes or electrodes 406, 407, 414 formed on opposite sides of the central electrode 405. Bonding wires 411 are used to connect ground plane 407 with ground planes 406, 414 of CPW sections 401, 402 at their interfaces with CPS section 403. This is done, in accordance with the principles of microwave theory, in order to provide current paths from/to the two ground CPW planes 406, 414 to/from the single ground plane 407 of the CPS section and to ensure, in terms of electro-magnetic wave distributions, efficient transformation of the CPW microwave mode to that of the CPS, and Vice versa. [0037] The phase modulator according to one embodiment of the present invention, as shown in FIG. 4, includes advantages previously achieved individually with CPW and CPS structures. Indeed, the CPW segments 401, 402 ensure efficient coupling to an input coaxial cable 408 and a termination circuitry, if any (not shown in FIG. 4). [0038] According to microwave theory, good overlap between the microwave field distribution of a coaxial cable and that of a CPW can be achieved, by a proper choice of the gap and hot electrode width of the CPW segment, which results in efficient electromagnetic coupling. At the same time, the CPS segment 403 can provide efficient modulation through good electro-optical overlap and be made to have impedance close to that of the feed line 408, by a proper choice of the gap 415 and hot electrode 405 width of the CPS Segment. [0039] Furthermore, efficient conversion of the RF power from the gap 412 not used for modulation to the other, can be achieved by employing bond wires (air bridges) 411 at the CPW/CPS transitions, as described above. For optimum operation, the gaps 412,415 and hot electrode 405 widths of the CPS and CPW segments should be designed to provide good impedance and mode matching between them. AS an example, the hot electrode widths for the CPW and CPS Segments can be chosen to be continuous acroSS the transition, as shown in FIG. 4. In this case, CPW gap 412 should be made wider than CPS gap 415, since if they were equal, the CPW segments 401, 402 would have a lower impedance than the CPS Segment 403, causing an impedance discontinuity at the transitions and microwave reflection. If the difference between gapS 412 and 415 is significant enough to cause microwave mode mismatch and radiation loSS, chamfered transitions can be employed, as is well known and detailed in microwave techniques. If the CPW/CPS transition is optimized, following these rules, the conversion efficiency is known to exceed 90%.” [Tavlykaev ¶¶ [0036] - [0039]; Fig. 4.].
Additionally, Jacques also teaches a plurality of wire-bonds between electrodes on opposite sides of a TW-MZM interconnection structure “[0012] The drive signal interconnection structure comprises a first wire - bond between the first electrical input port and the electrode shared by the first and second transmission lines, a second wire - bond between the second electrical input port and an electrode of the first transmission line , and a third wire - bond between the electrode of the first trans mission line and an electrode of the second transmission line. [0013] The third - wire bond is bonded at an angle selected to preserve relative phase shifts between the first and second drive signals. [0014] The drive signal interconnection structure comprises a first wire - bond between the first electrical input port and the electrode shared by the first and second transmission lines , a second wire - bond between the second electrical input port and an electrode of the first transmission line , a plurality of wire - bonds between the electrode of the first transmission line and an electrode of the second transmission line……“[0055] Referring to FIG . 4A , a driver chip 400 is connected to an optoelectronic chip 402A by a drive signal interconnection structure 404A that is formed by wire – bonds 406 and 408 and metal structures within a single metal layer of the optoelectronic chip 402A . A TW - MZM is formed on the optoelectronic chip 402A by structures that include a center electrode 410, outer electrodes 411 and 412, and a Mach - Zehnder interferometer with waveguide arms 413 and 414. The wire - bond 406 is formed between an S contact pad of the driver chip 400 and an outer electrode contact pad 415 in a metal layer of the optoelectronic chip 402A. A V – shaped metal trace connection 416 in the same metal layer connects to each of the outer electrodes 411 and 412. The wire – bond 408, which is longer than the wire - bond 406, is formed between an S contact pad of the driver chip 400 and a center electrode contact pad 418. The lengths of the wire – bonds 406 and 408 are selected so that the propagation delay across a wide bandwidth for rf signals between the driver and the beginning of the transmission lines of the TW - MZM are substantially equal. This propagation delay matching pre serves relative phase shifts between the S and S signals. In some implementations, wedge - bonds can be installed to achieve relatively precise relative timing for matching the propagation delay. The driver chip 400 can also optionally include ground contacts (G) as shown in this example” [Jacques ¶¶ [0012] - [0014], [0055]; Fig. 4A.]
Further, a person of ordinary skill in the art would have been motivated to connect adjacent ground pours by bonding wires because separated lateral ground structures do not provide the same shielding continuity or low-impedance return path as a more continuous grounded fence. Tavlykaev expressly teaches bridging adjacent ground planes at transitions to provide current return and proper electromagnetic transformation, and Jacques demonstrates practical wire-bond bridges across MZM electrode regions. Using such adjacent ground-pour connections in the Nelson/Tu package would have been an expected design refinement to reduce discontinuities in the ground reference, lower parasitic inductance, and increase containment of electric fields around the modulator transmission structure.
Claim 5
With respect to claim 5, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 5 additionally requires that the set of bonding wires are connected to ground pads of each driver. However, within analogous art, Jacques expressly teaches that the driver chip may include optional ground contacts (G) in the same differential-drive MZM interconnection arrangement “[0048] Some of the described approaches are directed to achieving optimal interconnection between a differential driver and a modulator that has a radio frequency (rf) transmission line electrode configuration of the type S - S – S or G - S - S - S - G (e.g., as shown in FIGS. 1A - 1D). In some of the examples described herein , the S - S - S electrode configuration is used to show implementations of a differential drive electrode configuration for an E - O crystal TW - MZM , but the techniques described herein can also be applied to G - S – S - S - G electrode configuration , and other integrated modulator technologies that may benefit from S - S - S or G - S - S - S – G differential electrode configurations , such as SOH modulators . In some implementations, the S signal from a 2 – port driver is split on - chip in interconnection circuitry that is fabricated on, or bonded to, the same die as the MZM. In other implementations, a 3 - port driver provides an S signal and two S signals at respective driver output ports, and the S signal is split within the driver (e.g., as shown in FIG. 2A), and in some implementations, at the transistor level (e.g., as shown in FIG. 2B). In some implementations, a passive termination circuit can be used to properly bias the driver output signals for an open - collector (OC) architecture. In either the 2 - port or 3 - port driver implementations, the connections between the driver and the modulator can be formed using any of a variety of techniques, including wire - bonds, or a controlled collapse chip connection, also called flip - chip or C4 connection. Also, the output ports of the driver may serve as input ports of the TW - MZM, including any wire - bonds or other structures extending to various portions of the TW – MZM. [0055] Referring to FIG . 4A , a driver chip 400 is connected to an optoelectronic chip 402A by a drive signal interconnection structure 404A that is formed by wire – bonds 406 and 408 and metal structures within a single metal layer of the optoelectronic chip 402A . A TW - MZM is formed on the optoelectronic chip 402A by structures that include a center electrode 410 , outer electrodes 411 and 412 , and a Mach - Zehnder interferometer with waveguide arms 413 and 414. The wire - bond 406 is formed between an S contact pad of the driver chip 400 and an outer electrode contact pad 415 in a metal layer of the optoelectronic chip 402A. A V – shaped metal trace connection 416 in the same metal layer connects to each of the outer electrodes 411 and 412. The wire – bond 408, which is longer than the wire - bond 406, is formed between an S contact pad of the driver chip 400 and a center electrode contact pad 418. The lengths of the wire – bonds 406 and 408 are selected so that the propagation delay across a wide bandwidth for rf signals between the driver and the beginning of the transmission lines of the TW - MZM are substantially equal. This propagation delay matching pre serves relative phase shifts between the S and S signals. In some implementations, wedge - bonds can be installed to achieve relatively precise relative timing for matching the propagation delay. The driver chip 400 can also optionally include ground contacts (G) as shown in this example” [Jacques ¶¶ [0048], [0055]; Fig. 4A].
It would have been obvious to connect corresponding shielding or ground bond wires to the driver-side ground pads or ground contacts because the driver chip is the source and return reference for the high-speed drive signal delivered to the MZM. Connecting the shielding network to the driver ground completes the RF return path, reduces loop area, stabilizes the impedance environment seen by the transmission lines, and lowers common-mode radiation. Jacques expressly shows optional ground contacts (G) in the same driver-to-MZM interconnection environment, so using those known driver-side ground contacts as termination points for the shielding bond wires would have been a routine and predictable implementation choice for improved return-current control and RF integrity. For purposes of this rejection, the claimed “ground pads of each driver” are reasonably read on Jacques’s driver-side ground contacts (G) and equivalent driver grounding terminals in the same differential-drive MZM interconnection architecture. The claim does not require any special pad geometry beyond a driver-side grounded contact usable as the termination point for the shielding or return network.
Claim 6
With respect to claim 6, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 6 additionally requires that a transmitter, of the set of transmitters, is associated with at least one of a driver, a set of interconnects, or an MZM of the set of MZMs. However, within analogous art, Nelson teaches that the transmitter side includes a modulator on the PIC and a corresponding modulator driver on the EIC, connected by short conductive paths, thereby teaching that a transmitter is associated with at least one of a driver, a set of interconnects, or an MZM/modulator “[0034] Referring to FIGS. 1A and 1B, in some embodiments, short electrical connections between ………………...distribution in an optoelectronic device. The electronic integrated circuit 110 may have a length between 5 mm and 15 mm (e.g., a length of 10.2 mm) and a width between 2 mm and 9 mm (e.g., a width of 4.4 mm) and the photonic integrated circuit 105 may have a length between 7 mm and 30 mm (e.g., a length of 15 mm) and a width between 3 mm and 11 mm (e.g., a width of 5.5 mm). [0035] The electronic integrated circuit 110 may be a silicon integrated circuit, and the front surface of the electronic integrated circuit …………. circuit (ASIC)) as discussed in further detail below. Each high-speed channel may further include circuitry for connecting the interface circuit to the serial receiver circuit or serial transmitter circuit (e.g., a clock and data recovery circuit connected to the transimpedance amplifier, in the case of a high-speed channel connected to a photodetector). The circuits on the electronic integrated circuit 110 may occupy a relatively small fraction (e.g., less than one half or less than one quarter) of the area of the electronic integrated circuit 110, and in some embodiments the excess area may be employed, e.g., to fabricate a microcontroller on the first portion 115 of the electronic integrated circuit 110………[0036] In some embodiments, the electrical connection between an optoelectronic device on the photonic integrated circuit 105 and the corresponding interface circuit (e.g., amplifier) on the electronic integrated circuit 110 may have a length of less than 500 microns, or less than 200 microns, or less than 100 microns. In some embodiments, the length may be nearly as small as the height of the metal bumps 140 (e.g., copper pillar bumps, discussed in further detail below) forming connections between the photonic integrated circuit 105 and the electronic integrated circuit 110. In some embodiments, the analog portion of a receiving channel (e.g., a photodetector and a transimpedance amplifier connected to the photodetector) may have a bandwidth (e.g., a 3 dB bandwidth) of at least 10 GHz, or at least 20 GHz, or at least 60 GHz, where the bandwidth is defined in terms of the transfer function from amplitude modulation on light received by the photodetector, to the corresponding signal at the output of the transimpedance amplifier. The bandwidth may be a relatively sensitive function of the aforementioned interconnect length between the PIC 140 an IC 110, e.g., a relatively small increase in the interconnect length may result in a significant decrease in bandwidth. Similarly, the analog portion of a transmitting channel (e.g., a modulator and a drive amplifier in the modulator driver connected to the modulator) may have a bandwidth (e.g., a 3 dB band width) of at least 10 GHz, or at least 20 GHz, or at least 60 GHz, where the bandwidth is defined in terms of the transfer function from an electrical signal at the input of the drive amplifier to the corresponding amplitude modulation produced by the modulator. The bandwidth may be a relatively sensitive function of the aforementioned interconnect length between the PIC 140 an IC……………... [0043] In some embodiments, all of the optoelectronic devices on a photonic integrated circuit 105 are the same. For example, on a photonic integrated circuit 105 that may be referred to as a receiving PIC (Rx PIC), all of the optoelectronic devices are photodetectors, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as an Rx IC), are all transimpedance amplifiers. Similarly, on a photonic integrated circuit 105 that may be referred to as a transmitting PIC (TX PIC), all of the optoelectronic devices may be modulators, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as a Tx IC), are all modulator drivers. [0044] FIG. 4 shows a fabrication flow, in some embodiments. A Tx IC is prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing, and an Rx IC is similarly prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing. Wafer back grinding may be employed to reduce overall thickness of the Tx IC or Rx IC while also reducing case to junction thermal resistance between the IC and ASIC heat sink discussed in further detail below. A TX PIC is prepared using steps including III - V micro - transfer printing (To place the modulators, which may be III - V devices, on the PIC), bumping (with the copper pillar bumps 140), and dicing, and an Rx PIC is prepared using steps including bumping (with the copper pillar bumps 140), and dicing. The Tx IC is then soldered to the Tx PIC to form an assembly that may be referred to as a “Tx sub assembly”, and the Rx IC is then soldered to the Rx PIC to form an assembly that may be referred to as a “Rx sub assembly”. The Tx sub assembly and the Rx sub assembly are then secured to a carrier 315, and fiber pigtails are attached to the PICs, to form an assembly that may be referred to as an optical engine. In these sub-assemblies the PIC may be substantially thicker than the IC especially in the case when the IC is subject to wafer - back grinding during wafer preparation. A thicker PIC reduces warpage to support fine pitch bump assembly in 135 and improves component rigidity after fiber pigtail assembly. In some embodiments, the photonic integrated circuit 105 has a thickness between 500 microns and 1000 microns, e.g., about 680 microns, and the electronic integrated circuit 110 has a thickness between 100 microns and 700 microns, e.g., 580 microns” [Nelson ¶¶ [0034] - [0036], [0043] - [0044]; Figs. 1A-4].
Further, a person of ordinary skill in the art would have understood that, in an optical transmitter channel of the type taught by Nelson, the transmitter is ordinarily and inherently associated with the driver that launches the electrical data, the interconnects that convey that signal, and the MZM that converts the electrical drive into optical modulation. Claim 6 therefore merely recites the normal organization of a known transmitter channel rather than introducing a new or non-conventional structure. To the extent any explicit articulation of that association were considered absent from Nelson, stating the transmitter in terms of those known constituent elements would nevertheless have been obvious because those are the very elements a skilled artisan would recognize as making up the transmitter path in a co-packaged photonic transmitter.
Claim 8
With respect to claim 8, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 8 additionally requires that the ground pours at least partially cover or bracket each MZM associated with a transmitter.
However, within analogous art, Tu teaches a shield-CPW arrangement around the silicon MZI modulator transmission line “Abstract: A silicon Mach-Zehnder Interferometer (MZI) optical modulator with a shield coplanar waveguide (CPW) transmission line electrode design was demonstrated. This shield-CPW electrode suppresses the signal distortion caused by the parasitic slot-line (SL) mode and improves the electrical bandwidth and the electro-optical (EO) bandwidth. With the shield-CPW electrodes and 5.5 mm-long phase shifters, the silicon MZI optical modulator delivered an EO bandwidth of above 24 GHz and a V π = 3.0 V was achieved at λ = 1310nm. When modulated at 28-Gb/s data rate, it achieved an extinction ratio of 5.66 dB under a driving voltage of V pp = 1.3 V, corresponding to a power consumption of 0.8 pJ/bit” [Tu, Abstract; Fig. 1].
Tavlykaev teaches a central signal electrode with ground planes on opposite sides in an MZI modulator arrangement mode “[0005] In the optical waveguide structure of a modulator, and as shown in FIG. 1, a Mach-Zehnder interferometer (MZI)102 is typically disposed. A Mach-Zehnder modulator includes an interferometer 102 having an input waveguide 103 and arms 104,105 that branch from the input waveguide 103, and an output waveguide 106 at the junction of the arms 104, 105. Typically, an optical signal is directed into and propagates in the input waveguide 103, and is split between the arms 104, 105 so that approximately one-half of the input optical Signal propagates in each of the interferometer arms 104,105. A modulating signal is applied to the modulator in order to change the effective refractive indices of the interferometer arms and to introduce a relative phase shift between the two optical Signals. The phase-shifted optical Signals combine at the output waveguide 106 and produce intensity modulation. Depending on the relative phase shift between the two optical Signals, they may interfere either constructively or destructively. The output of the modulator is thus, an intensity modulated optical Signal. A relative phase shift between the optical signals in the arms 104, 105 of approximately It is required to Switch the output of the modulator between adjacent on and off States. [0006] The electrode structure shown in FIG. 1 is a microwave Coplanar Waveguide (CPW) aligned with respect to the waveguide Structure in Such a way that the interferometer arms 104,105 are positioned in the electrode gaps 107 and run alongside the gap edges (in X-cut devices). A CPW electrode structure includes a hot central (signal) electrode 108 and two ground planes or electrodes 109,110 formed on opposite sides of the central electrode 108. Microwave (modulating) signals are provided to the signal electrode 108 from a microwave Source 111, via a connector and a microwave cable. The widths of the gap 107 and hot electrode 108 are tapered at the input and output. Advantageously, a CPW structure with properly chosen widths of the gap 107 and hot electrode 108 at the modulator input has a microwave field distribution closely matching that of a coaxial cable connecting the modulator to the microwave Source 111. [0007] FIG. 1 shows an intensity modulator 100 with the So-called “push-pull configuration, wherein the electric field crossing one interferometer arm 104 is opposite to that crossing the other 105. AS Such, the electro-optic phase shifts induced in the two arms 104, 105 are of equal magnitude but opposite sign. Effectively, the intensity modulator 100 incorporates two phase modulators, represented by the two arms 104, 105, which are driven 180 degrees out of phase with respect to each other. The outputs of the two-phase modulators are combined to result in an intensity modulation that depends on the relative phase difference between the arms 104, 105. In the push-pull configuration, the phase difference doubles compared to the phase shift in each arm and the half-wave Voltage of the modulator is therefore halved, which represents a significant advantage over other Schemes” [Tavlykaev ¶¶ [0005] - [0007]].
Collectively, these references teach ground structures bracketing the MZM transmission path.
Further, a person of ordinary skill in the art would have been motivated to arrange the ground pours so that they at least partially cover or bracket each MZM because placing grounded structures laterally around the driven modulator transmission line is the established way to confine the RF field, suppress slot-line and other parasitic modes, and maintain controlled impedance. Tu teaches a shield-CPW arrangement around the silicon MZI transmission structure, and Tavlykaev teaches opposite-side ground planes in an MZI/CPW arrangement. Applying such bracketing geometry in Nelson's compact transceiver package would therefore have been the technically sensible implementation of the known shielding concept, yielding the expected benefits of improved bandwidth and reduced coupling into adjacent circuitry.
Claim 9
With respect to claim 9, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 9 additionally requires that a bonding wire connects a first ground pour to a second ground pour, crosses without touching a set of signal traces, and that the signal traces are disposed between the first and second ground pours. However, within analogous art, Tavlykaev further teaches bond wires connecting opposite-side/adjacent ground structures in a CPW modulator context “[0036] FIG. 4 illustrates one embodiment of the present invention, which is an optical (phase) modulator 400, including a channel optical waveguide 409 and two CPW segments 401, 402. The CPW segments provide mode symmetry when RF is coupled into and out of the electrode structure. The RF traverses a (i.e., asymmetric) CPS line segment 403, which extends along the interaction length 404 of the modulator 400, and imparts electro-optic modulation to the optical waveguide 409. Each CPW segment 401, 402 includes a hot central (signal) electrode 405 and two ground planes or electrodes 406, 407, 414 formed on opposite sides of the central electrode 405. Bonding wires 411 are used to connect ground plane 407 with ground planes 406, 414 of CPW sections 401, 402 at their interfaces with CPS section 403. This is done, in accordance with the principles of microwave theory, in order to provide current paths from/to the two ground CPW planes 406, 414 to/from the single ground plane 407 of the CPS section and to ensure, in terms of electro-magnetic wave distributions, efficient transformation of the CPW microwave mode to that of the CPS, and Vice versa. [0037] The phase modulator according to one embodiment of the present invention, as shown in FIG. 4, includes advantages previously achieved individually with CPW and CPS structures. Indeed, the CPW segments 401, 402 ensure efficient coupling to an input coaxial cable 408 and a termination circuitry, if any (not shown in FIG. 4). [0038] According to microwave theory, good overlap between the microwave field distribution of a coaxial cable and that of a CPW can be achieved, by a proper choice of the gap and hot electrode width of the CPW segment, which results in efficient electromagnetic coupling. At the same time, the CPS segment 403 can provide efficient modulation through good electro-optical overlap and be made to have impedance close to that of the feed line 408, by a proper choice of the gap 415 and hot electrode 405 width of the CPS Segment. [0039] Furthermore, efficient conversion of the RF power from the gap 412 not used for modulation to the other, can be achieved by employing bond wires (air bridges) 411 at the CPW/CPS transitions, as described above. For optimum operation, the gaps 412,415 and hot electrode 405 widths of the CPS and CPW segments should be designed to provide good impedance and mode matching between them. AS an example, the hot electrode widths for the CPW and CPS Segments can be chosen to be continuous acroSS the transition, as shown in FIG. 4. In this case, CPW gap 412 should be made wider than CPS gap 415, since if they were equal, the CPW segments 401, 402 would have a lower impedance than the CPS Segment 403, causing an impedance discontinuity at the transitions and microwave reflection. If the difference between gapS 412 and 415 is significant enough to cause microwave mode mismatch and radiation loSS, chamfered transitions can be employed, as is well known and detailed in microwave techniques. If the CPW/CPS transition is optimized, following these rules, the conversion efficiency is known to exceed 90%.” [Tavlykaev ¶¶ [0036] - [0039]; Fig. 4].
Additionally, Jacques expressly teaches a third wire-bond between an electrode of a first transmission line and an electrode of a second transmission line, and teaches that the third wire-bond is bonded at an angle while the center electrode/contact remains between the opposite-side electrodes. This is the closest teaching of a bond wire spanning across intermediate signal structure without contact “mission line and an electrode of the second transmission line. [0013] The third - wire bond is bonded at an angle selected to preserve relative phase shifts between the first and second drive signals. [0014] The drive signal interconnection structure comprises a first wire - bond between the first electrical input port and the electrode shared by the first and second transmission lines , a second wire - bond between the second electrical input port and an electrode of the first transmission line , a plurality of wire - bonds between the electrode of the first transmission line and an electrode of the second transmission line…….[0055] Referring to FIG . 4A , a driver chip 400 is connected to an optoelectronic chip 402A by a drive signal interconnection structure 404A that is formed by wire – bonds 406 and 408 and metal structures within a single metal layer of the optoelectronic chip 402A . A TW - MZM is formed on the optoelectronic chip 402A by structures that include a center electrode 410 , outer electrodes 411 and 412 , and a Mach - Zehnder interferometer with waveguide arms 413 and 414. The wire - bond 406 is formed between an S contact pad of the driver chip 400 and an outer electrode contact pad 415 in a metal layer of the optoelectronic chip 402A . A V – shaped metal trace connection 416 in the same metal layer connects to each of the outer electrodes 411 and 412. The wire – bond 408 , which is longer than the wire - bond 406 , is formed between an S contact pad of the driver chip 400 and a center electrode contact pad 418. The lengths of the wire – bonds 406 and 408 are selected so that the propagation delay across a wide bandwidth for rf signals between the driver and the beginning of the transmission lines of the TW - MZM are substantially equal . This propagation delay matching pre serves relative phase shifts between the S and S signals . In some implementations, wedge - bonds can be installed to achieve relatively precise relative timing for matching the propagation delay . The driver chip 400 can also optionally include ground contacts ( G ) as shown in this example” [Jacques ¶¶ [0012] - [0014], [0055]; Fig. 4A].
It would have been obvious to use a spanning bond-wire interconnection across intervening signal traces in order to connect opposite-side shield or ground structures while preserving the desired RF field distribution and return-current path around the modulator. In compact RF-photonic layouts, a grounded bridge above a center signal region is a conventional way to maintain shielding continuity without shorting the signal conductor, and the combined teachings of Tavlykaev and Jacques would have directed a skilled artisan to that exact arrangement for improved mode control, shielding continuity, and reduced parasitic coupling.
For purposes of this rejection, the claimed limitation that the bonding wire “crosses without touching” the signal traces is reasonably read on Jacques’s third wire-bond spanning between opposite-side electrode structures while the intermediate signal structure remains between them and is not contacted by the spanning bond. Tavlykaev supplies the grounded-bridge context, and Jacques supplies the above-trace spanning geometry; together they render the claimed relationship obvious under the broadest reasonable interpretation.
It would have been obvious to use such spanning bond-wire interconnection across intermediate signal traces in order to connect opposite-side shield/ground structures while preserving the desired RF field distribution and return-current path around the modulator.
Further, a person of ordinary skill in the art would have been motivated to route a bonding wire between first and second ground pours so that it crosses above intervening signal traces without touching them because compact RF-photonic layouts frequently require a grounded bridge across a center signal region in order to maintain shielding continuity while preserving the signal path. Jacques shows a bond wire spanning over intermediate electrode structure, and Tavlykaev teaches bridge-style ground connections in an MZM/CPW context. Using such an above-trace grounded bridge in the combined package would have been a routine packaging and layout solution to preserve the lateral ground fence, maintain current continuity, and avoid shorting the signal traces, while predictably improving shielding effectiveness
Claim 10
With respect to claim 10, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 10 additionally requires first, second, and third subsets of bonding wires respectively connecting the set of ground pours to driver ground pads, connecting adjacent ground pours to one another, and connecting the set of ground pours to package/transceiver ground. However, within analogous art, Nelson teaches the package-level co-packaged transceiver architecture providing package/subassembly ground structures. It would have been obvious to distribute the shielding/ground bond-wire network among these known connection points to complete the RF-ground architecture around the transmitter modulator structures “[0034] Referring to FIGS. 1A and 1B, in some embodiments, short electrical connections between (i) a component (e.g., a photodetector and / or modulator) on a photonic integrated circuit 105 (PIC) and (ii) a component or circuit (e.g., a transimpedance amplifier and / or modulator driver) on an electronic integrated circuit 110 may be formed by flip - chip bonding the photonic integrated circuit 105 to the electronic integrated circuit 110 to form a flip - chip assembly. The photonic integrated circuit may include a substrate (e.g., a silicon substrate) having a front surface (the upper surface of the photonic integrated circuit 105, in the orientation of FIG. 1A), on or in which may be V - grooves (for passive alignment to an optical fiber, not shown for ease of illustration), optical waveguides, optoelectronic devices (e.g., photodetectors and modulators), and one or more metal layers forming conductive traces for routing electrical signals to and from the optoelectronic devices. The optical waveguides may include mode converters (e.g., tapered sections) e.g., for converting between a mode that may propagate in a 3 - micron wide waveguide and (i) a mode that may propagate in a single - mode fiber, or (ii) a mode that may produce a useful intensity distribution in an optoelectronic device. The electronic integrated circuit 110 may have a length between 5 mm and 15 mm (e.g., a length of 10.2 mm) and a width between 2 mm and 9 mm (e.g., a width of 4.4 mm) and the photonic integrated circuit 105 may have a length between 7 mm and 30 mm (e.g., a length of 15 mm) and a width between 3 mm and 11 mm (e.g., a width of 5.5 mm) ………. [0045] One or more optical engines may be used to provide optical interfaces to a digital integrated circuit 505 (e.g., a switch ASIC) as shown in FIG. 5. An ASIC heat sink 510 conducts heat away from the digital integrated circuit 505 (e.g., to a heat - pipe - based cooling system). A top clamp 515 (together with a bottom portion 517) secures the optical engine and the compressible membrane connector 305 to the printed circuit board 310 and conducts away heat flowing through the carrier 315 from the optical engine; the top clamp is thermally connected to a removable heat sink section 520 through a layer of compliant thermal interface material 525. In the embodiment of FIG. 5, the carrier 315 lacks the alignment ridges 320 shown in FIG. 3; in other embodiments, however, one or more alignment ridges 320 may be present, and the structure may otherwise be similar to that illustrated in FIG. 5. The printed circuit board 310 may form the substrate of a package, including the elements illustrated in FIG. 5, that may be secured and connected to another printed circuit board (e.g., a motherboard) by an array of conductors 530 on the lower surface of the printed circuit board 310. Such a motherboard may have a hole or cutout to accommodate the bottom portion 517 of the clamp. A second beachfront 540 may be used to accommodate another optical engine (not shown), or, for example, an edge connector for making serial electrical connections to the digital integrated circuit 505 (as discussed in further detail below)” [Nelson ¶¶ [0034] - [0045]].
Additionally, Tavlykaev teaches bond wires connecting adjacent ground structures to one another “[0036] FIG. 4 illustrates one embodiment of the present invention, which is an optical (phase) modulator 400, including a channel optical waveguide 409 and two CPW segments 401, 402. The CPW segments provide mode symmetry when RF is coupled into and out of the electrode structure. The RF traverses a (i.e., asymmetric) CPS line segment 403, which extends along the interaction length 404 of the modulator 400, and imparts electro-optic modulation to the optical waveguide 409. Each CPW segment 401, 402 includes a hot central (signal) electrode 405 and two ground planes or electrodes 406, 407, 414 formed on opposite sides of the central electrode 405. Bonding wires 411 are used to connect ground plane 407 with ground planes 406, 414 of CPW sections 401, 402 at their interfaces with CPS section 403. This is done, in accordance with the principles of microwave theory, in order to provide current paths from/to the two ground CPW planes 406, 414 to/from the single ground plane 407 of the CPS section and to ensure, in terms of electro-magnetic wave distributions, efficient transformation of the CPW microwave mode to that of the CPS, and Vice versa. [0037] The phase modulator according to one embodiment of the present invention, as shown in FIG. 4, includes advantages previously achieved individually with CPW and CPS structures. Indeed, the CPW segments 401, 402 ensure efficient coupling to an input coaxial cable 408 and a termination circuitry, if any (not shown in FIG. 4). [0038] According to microwave theory, good overlap between the microwave field distribution of a coaxial cable and that of a CPW can be achieved, by a proper choice of the gap and hot electrode width of the CPW segment, which results in efficient electromagnetic coupling. At the same time, the CPS segment 403 can provide efficient modulation through good electro-optical overlap and be made to have impedance close to that of the feed line 408, by a proper choice of the gap 415 and hot electrode 405 width of the CPS Segment. [0039] Furthermore, efficient conversion of the RF power from the gap 412 not used for modulation to the other, can be achieved by employing bond wires (air bridges) 411 at the CPW/CPS transitions, as described above. For optimum operation, the gaps 412,415 and hot electrode 405 widths of the CPS and CPW segments should be designed to provide good impedance and mode matching between them. AS an example, the hot electrode widths for the CPW and CPS Segments can be chosen to be continuous acroSS the transition, as shown in FIG. 4. In this case, CPW gap 412 should be made wider than CPS gap 415, since if they were equal, the CPW segments 401, 402 would have a lower impedance than the CPS Segment 403, causing an impedance discontinuity at the transitions and microwave reflection. If the difference between gapS 412 and 415 is significant enough to cause microwave mode mismatch and radiation loSS, chamfered transitions can be employed, as is well known and detailed in microwave techniques. If the CPW/CPS transition is optimized, following these rules, the conversion efficiency is known to exceed 90%.” [Tavlykaev ¶¶ [0036] - [0039]].
Jacques further, teaches driver-chip ground contacts suitable for connection to shielding/return structures “[0048] Some of the described approaches are directed to achieving optimal interconnection between a differential driver and a modulator that has a radio frequency ( rf ) transmission line electrode configuration of the type S - S – S or G - S - S - S - G ( e.g. , as shown in FIGS . 1A - 1D ) . In some of the examples described herein , the S - S - S electrode configuration is used to show implementations of a differential drive electrode configuration for an E - O crystal TW - MZM , but the techniques described herein can also be applied to G - S – S - S - G electrode configuration , and other integrated modulator technologies that may benefit from S - S - S or G - S - S - S – G differential electrode configurations , such as SOH modulators . In some implementations, the S signal from a 2 – port driver is split on - chip in interconnection circuitry that is fabricated on , or bonded to , the same die as the MZM . In other implementations , a 3 - port driver provides an S signal and two S signals at respective driver output ports , and the S signal is split within the driver ( e.g. , as shown in FIG . 2A ) , and in some implementations , at the transistor level ( e.g. , as shown in FIG . 2B ) . In some implementations , a passive termination circuit can be used to properly bias the driver output signals for an open - collector ( OC ) architecture . In either the 2 - port or 3 - port driver implementations, the connections between the driver and the modulator can be formed using any of a variety of techniques, including wire - bonds , or a controlled collapse chip connection , also called flip - chip or C4 connection . Also , the output ports of the driver may serve as input ports of the TW - MZM , including any wire - bonds or other structures extending to various portions of the TW – MZM……….[0055] Referring to FIG . 4A , a driver chip 400 is connected to an optoelectronic chip 402A by a drive signal interconnection structure 404A that is formed by wire – bonds 406 and 408 and metal structures within a single metal layer of the optoelectronic chip 402A . A TW - MZM is formed on the optoelectronic chip 402A by structures that include a center electrode 410 , outer electrodes 411 and 412 , and a Mach - Zehnder interferometer with waveguide arms 413 and 414. The wire - bond 406 is formed between an S contact pad of the driver chip 400 and an outer electrode contact pad 415 in a metal layer of the optoelectronic chip 402A . A V – shaped metal trace connection 416 in the same metal layer connects to each of the outer electrodes 411 and 412. The wire – bond 408 , which is longer than the wire - bond 406 , is formed between an S contact pad of the driver chip 400 and a center electrode contact pad 418. The lengths of the wire – bonds 406 and 408 are selected so that the propagation delay across a wide bandwidth for rf signals between the driver and the beginning of the transmission lines of the TW - MZM are substantially equal . This propagation delay matching pre serves relative phase shifts between the S and S signals . In some implementations , wedge - bonds can be installed to achieve relatively precise relative timing for matching the propagation delay . The driver chip 400 can also optionally include ground contacts ( G ) as shown in this example” [Jacques ¶¶ [0048], [0055]].
More specifically, a skilled artisan would have recognized that the three recited subsets merely distribute known grounding functions among known connection points in the package stack: local driver-ground termination, local adjacent-ground bridging near the MZM, and connection from the local shielding network into the broader package or transceiver ground. Implementing those three categories of ground connections in the combined Nelson, Tavlykaev, and Jacques’s architecture would have been no more than the predictable organization of a continuous RF return network in a dense co-packaged optical transmitter.
Further, a person of ordinary skill in the art would have been motivated to implement multiple subsets of bonding wires that respectively tie the ground pours to driver ground pads, to adjacent ground pours, and to package or transceiver ground because a dense high-speed photonic package ordinarily requires a continuous multi-point ground network rather than an isolated local ground segment. Tavlykaev teaches adjacent-ground bridging, Jacques teaches driver-side ground/contact architecture, and Nelson teaches the package-level PIC/EIC integration environment. Combining those teachings to form a hierarchical ground fence tied locally to the driver and globally to the package ground would have been a predictable way to lower ground impedance, reduce parasitic inductance, stabilize reference potential along the transmitter path, and improve crosstalk suppression.
Claims 2 and 7 are rejected under 35 U.S.C. § 103 as being unpatentable over Nelson et al., in view of Tu et al., further in view of Tavlykaev et al., and Jacques et al., and further in view of Evans et al. (US10026723B2).
Claim 2
With respect to claim 2, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 2 additionally requires that the SiP transceiver includes at least one of a coherent transceiver or an IM-DD transceiver for an amplified or un-amplified optical communication link. However, within analogous art, Evans teaches receiver PICs, transmitter PICs, and a transceiver PIC
“A photonic integrated circuit (PIC) provides a platform for integrating passive and active or multiple active optical devices on a single chip. For example, optical devices for enabling a transmitter, a receiver, or a transceiver may be implemented on a photonic integrated circuit. Active photonic devices are typically controlled by electrical signals, where the electrical signals may be supplied by external circuitry such as an application-specific integrated circuit (ASIC) chip. Conventionally, a single-channel traveling wave modulator may be packaged to an interposer. However, a single-channel configuration may not scale to multiple channels or multiple elements due to constraints such as geometry, electrical/optical routing, excessive PIC size and cost, and/or packaging. Moreover, connections between an ASIC and the interposer to drive a photonic integrated circuit require careful engineering considerations. In addition, an interpose configuration for a traveling wave modulator may not work on a lumped element on the PIC, and it is not obvious that a lumped element could benefit from an interposer. This disclosure is directed to using one or more interposers or substrates including semiconductor or dielectric materials in a PIC package. The interposers may provide electrical interconnects between an ASIC chip and a PIC chip for controlling lumped-based and/or traveling wave-based active optical devices, such as modulators. Interposers may provide compact connections to multi-element (especially multi-active element) and/or multi-channel PICs. Such connections may otherwise be bulky or impractical with conventional wire-bonding technology. Interposers electrically connect radio frequency (RF) ASICs and RF PIC elements in a short distance with controlled impedance, and they may also connect slower-speed (quasi-direct current (DC)) PIC elements to slower speed ASICs or another driver circuitry that may be located in the same package or external to a module package. Radio frequency may range from 3 kHz to 300 GHz. ASICs may be arranged in one or more arrays that match the pitch of one or more of the PIC channel device array or arrays. As described in this disclosure, a channel includes the electrical circuitry and optical devices that are associated with one optical wavelength. A RF channel pitch is the physical spacing on a PIC chip or on an ASIC chip that is associated between two channels, which may include I-Q (in-phase and quadrature) modulators or detectors for both polarizations where these are routed and processed separately…………As another example, the 35 termination resistors for matching an impedance of a conductive trace may be provided off the PIC chip on the interposer or routed elsewhere in the package via the interposer, such that heat dissipation from the termination resistor does not affect the performance of the PIC chip. The PIC, 40 therefore, may be more readily cooled or temperature regulated. As another example, by avoiding wire bonding, an inductance of a conductive trace may be reduced. As another example, in cases where a velocity mismatch between an electrical signal and an optical signal affects a performance 45 of an active optical device, a length of a conductive trace on an interposer may be designed such that the electrical signal and the optical signal may arrive at designed location(s) on the PIC chip at the same time, i.e., matched phase. As another example, test points may be formed on a conductive 50 trace on an interposer to test a frequency response of an active optical device or combined electro-optic ASIC-interposer- PIC performance (or subset thereof). [Evans, col. 2, col. 3, Figs. 13A-13D, 26-29].
Evans further teaches coherent-detection receiver operation in which coherent detectors and TIAs process received optical signals “FIGS. 34 and 35 illustrate example PIC packaging arrangements that show advantages of using an interposer or a bridge chip to electrically couple active optical elements on a PIC chip and circuitry on an ASIC chip. Referring to FIG. 34, the arrangement 3400 includes a TX PIC chip 3410 and a MZMD chip 3420. The TX PIC chip 3410 includes multiple MZM arms 3402 that are in the interior of the TX PIC chip 3410. The MZM arms 3402 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3420. As illustrated in FIG. 34, if wire bonds are used to establish the electrical connections between the MZM arms 3402 and the MZMD circuit, the distance between the MZM arms 3402 and the MZMD chip 3420 may be greater than 1 mm, which may increase complexity in wiring and may negatively impact the device performance at high speed. Flip-chip or wafer bonding between the TX PIC chip 3410 and the MZMD chip 3420 significantly decreases the wiring length, and allows more complex arrangements of the optical elements on the PIC chip. Referring to FIG. 35, the arrangement 3500 includes a TX PIC chip 3510 and a MZMD chip 3520. The TX PIC chip 3510 includes multiple MZM arms 3502 that are arranged along the edge of the TX PIC chip 3510. The MZM arms 3502 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3520. As illustrated in FIG. 35, if wire bonds are used to establish the electrical………... The example layout 305 also includes a portion of an interposer 364 having signal traces 374a and 374b and a ground trace 376. The interposer 364 includes bond contacts 378a-378c, which enable electrical connections from/to the interposer 364 to/from the PIC chip 362. Although not shown, the interposer 364 may be electrically coupled to one or more ASIC chips such as a TIA. The PIC chip 332 may be bonded to the interposer 334 in a manner similar to the implementations described in this specification. Interposer traces may constitute a coplanar waveguide or other transmission line design. During operation, an optical signal is received by the waveguide photodetector 366, where the optical signal is absorbed by the waveguide photodetector 366 and is converted to an electrical signal. The electrical signal is collected through bond contacts to a TIA that is coupled to the interposer 364” [Evans, col. 14, col. 15].
Additionally, Evans teaches a coherent transceiver configuration “……. FIG. 8 shows further examples of signal electrode segments, bond contacts, and signal traces consistent with the present disclosure. Referring to the example PIC layout 801, each signal electrode segment may include a pad portion 802a and a T-shaped portion 802b connected to the pad portion 802a. The pad portion 802a may be aligned with a bond contact 804 formed on an interposer 810, which, in turn, is aligned with a signal trace 806 on a surface of the interposer 810 opposite the PIC 801. The bond contact 804 may be electrically coupled to the signal trace 806 through a via (not shown). As described above in reference to FIGS. 4A-4C, the drive signal may be applied to the signal trace 806, down the via (not shown) to the bond contact 804, to the PIC pad portion 802a, and to the T-shaped portion 802b. At which point, the voltage creates an electric field in an underlying waveguide to change the refractive index of the waveguide 812. As a result, the phase and/or amplitude of light propagating in the waveguide 812 is changed or modulated in accordance with the electrical drive signal and
thus the data to be carried by the optical signal. Although not shown in the figure, there may be gold or solder bumps, termination resistors and so forth. FIG. 9A shows an example packaging arrangement 900 including a substrate or package floor 902 upon which a first heat sink 904, a thermal-electric cooler (TEC) 906, and…...” [Evans, col. 2, col. 3, col. 14, col. 15, col. 24, Figs. 13A-13D, 26-29].
A person of ordinary skill in the art would have been motivated to employ Nelson’s transceiver package in a coherent-transceiver implementation such as Evans because both references address high-speed optical transmitter/receiver integration on PIC-based platforms and seek to shorten electrical paths between modulators/photodiodes and associated driver/TIA circuitry. The substitution would have been no more than the predictable application of a known optical transceiver architecture to Nelson’s co-packaged platform.
Further, a person of ordinary skill in the art would have been motivated to use a coherent-transceiver or IM-DD transceiver implementation such as that taught by Evans in Nelson's co-packaged optical platform because both references are directed to high-speed optical transceivers that place modulators, photodiodes, drivers, and TIAs in close physical association in order to shorten electrical paths and preserve signal integrity. Evans demonstrates that coherent receiver and transmitter functionality was already conventionally implemented on PIC-based transceiver packages, and applying that known coherent architecture to Nelson's overlap-region package would have been a routine adaptation yielding the expected benefits of compactness, lower parasitics, and higher bandwidth. Because claim 2 is written in the alternative ('at least one of'), satisfaction by the coherent-transceiver embodiment alone is sufficient, and the selection of that known transceiver type would have been an obvious design choice.
Claim 7
Claim 7 is addressed on its intended interpretation notwithstanding the rejection under 35 U.S.C. 112(b). With respect to claim 7, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein that claim 7 additionally recites a receiver being associated with at least one of a transimpedance amplifier, a set of interconnects, or a differential high-speed photodiode. However, within analogous art, Nelson teaches receiver-side photodetectors and transimpedance amplifiers on corresponding PIC and IC structures “[0034] Referring to FIGS. 1A and 1B, in some embodiments, short electrical connections between ………………...distribution in an optoelectronic device. The electronic integrated circuit 110 may have a length between 5 mm and 15 mm (e.g., a length of 10.2 mm) and a width between 2 mm and 9 mm (e.g., a width of 4.4 mm) and the photonic integrated circuit 105 may have a length between 7 mm and 30 mm (e.g., a length of 15 mm) and a width between 3 mm and 11 mm (e.g., a width of 5.5 mm). [0035] The electronic integrated circuit 110 may be a silicon integrated circuit, and the front surface of the electronic integrated circuit …………. circuit (ASIC)) as discussed in further detail below. Each high-speed channel may further include circuitry for connecting the interface circuit to ………. small fraction (e.g., less than one half or less than one quarter) of the area of the electronic integrated circuit 110, and in some embodiments the excess area may be employed, e.g., to fabricate a microcontroller on the first portion 115 of the electronic integrated circuit 110……… [0036] In some embodiments, the electrical connection between an optoelectronic device on the photonic integrated ………………. electronic integrated circuit 110. In some embodiments, the analog portion of a receiving channel (e.g., a photodetector and a transimpedance amplifier connected to the photodetector) may have a bandwidth (e.g., a 3 dB bandwidth) of at least 10 GHz, or at least 20 GHz, or at least 60 GHz, where the bandwidth is defined in terms of the transfer function from …… at least 20 GHz, or at least 60 GHz, where the bandwidth is defined in terms of the transfer function from an electrical signal at the input of the drive amplifier to the corresponding amplitude modulation produced by the modulator. The bandwidth may be a relatively sensitive function of the aforementioned interconnect length between the PIC 140 an IC……………... [0043] In some embodiments, all of the optoelectronic devices on a photonic integrated circuit 105 are the same. For example, on a photonic integrated circuit 105 that may be referred to as a receiving PIC (Rx PIC), all of the optoelectronic devices are photodetectors, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as an Rx IC), are all transimpedance amplifiers. Similarly, on a photonic integrated circuit 105 that may be referred to as a transmitting PIC (TX PIC), all of the optoelectronic devices may be modulators, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as a Tx IC), are all modulator drivers. [0044] FIG. 4 shows a fabrication flow, in some embodiments. A Tx IC is prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing, and an Rx IC is similarly prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing. Wafer back grinding may be employed to reduce overall thickness of the Tx IC or Rx IC while also reducing case to junction thermal resistance between the IC and ASIC heat sink discussed in further detail below. A TX PIC is prepared using steps including III - V micro - transfer printing (To place the modulators, which may be III - V devices, on the PIC), bumping (with the copper pillar bumps 140), and dicing, and an Rx PIC is prepared using steps including bumping (with the copper pillar bumps 140), and dicing. The Tx IC is then soldered to the Tx PIC to form an assembly that may be referred to as a “Tx sub assembly”, and the Rx IC is then soldered to the Rx PIC to form an assembly that may be referred to as a “Rx sub assembly”. The Tx sub assembly and the Rx sub assembly are then secured to a carrier 315, and fiber pigtails are attached to the PICs, to form an assembly that may be referred to as an optical engine. In these sub-assemblies the PIC may be substantially thicker than the IC especially in the case when the IC is ……...” [Nelson ¶¶ [0034] - [0036], [0043] - [0044]].
Additionally, Evans further teaches receiver PICs, transceiver PICs, waveguide photodiodes, balanced photodetectors, and TIAs for coherent receiver operation “……. FIG. 8 shows further examples of signal electrode segments, bond contacts, and signal traces consistent with the present disclosure. Referring to the example PIC layout 801, each signal electrode segment may include a pad portion 802a and a T-shaped portion 802b connected to the pad portion 802a. The pad portion 802a may be aligned with a bond contact 804 formed on an interposer 810, which, in turn, is aligned with a signal trace 806 on a surface of the interposer 810 opposite the PIC 801. The bond contact 804 may be electrically coupled to the signal trace 806 through a via (not shown). As described above in reference to FIGS. 4A-4C, the drive signal may be applied to the signal trace 806, down the via (not shown) to the bond contact 804, to the PIC pad portion 802a, and to the T-shaped portion 802b. At which point, the voltage creates an electric field in an underlying waveguide to change the refractive index of the waveguide 812. As a result, the phase and/or amplitude of light propagating in the waveguide 812 is changed or modulated in accordance with the electrical drive signal and
thus, the data to be carried by the optical signal. Although not shown in the figure, there may be gold or solder bumps, termination resistors and so forth. FIG. 9A shows an example packaging arrangement 900 including a substrate or package floor 902 upon which a first heat sink 904, a thermal-electric cooler (TEC) 906, and…...” [Evans, col. 2, col. 3, col. 14, col. 15, col. 24].
Further, on the intended interpretation, a person of ordinary skill in the art would have understood that a receiver channel in a high-speed optical transceiver is conventionally associated with the photodiode that performs optical-to-electrical conversion, the TIA that amplifies the received electrical signal, and the short interconnect path between those elements. Nelson teaches receiver-side photodetectors and TIAs, and Evans further teaches balanced/differential photodiode and TIA arrangements in transceiver PIC environments. Thus, even if claim 7 is indefinite for lack of antecedent basis, the substance of the limitation merely reflects the known structure of a receiver chain and would have been obvious on the intended interpretation.
Claims 3 and 11 are rejected under 35 U.S.C. § 103 as being unpatentable over Nelson et al., in view of Tu et al., further in view of Tavlykaev et al., and Jacques et al., and further in view of Chen et al. (EP4403987A1).
Claim 3
With respect to claim 3, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 3 additionally requires that the ground pours and bonding wires are positioned to electromagnetically shield transmission from each transmitter relative to another transmission or relative to a reception by a receiver. However, within analogous art, Chen expressly teaches that RF crosstalk between one integrated circuit and another on the same silicon substrate is particularly problematic, especially from a driver output to a TIA input, and further teaches that even crosstalk levels around -70 dB may induce notable receiver-sensitivity penalty “[0008] One solution to avoid the undesired RF absorption loss induced by the silicon substrate is to use high resistivity silicon substrates (e.g., with a resistivity of 750 ohm-cm). Using a high-resistivity silicon substrate poses two possible problems. First, a high-resistivity substrate may become a limitation in wafer availability or foundry fabrication processes (such as through silicon via processes). Second, while the high-resistivity substrate avoids RF absorption loss of the driving signals of the modulators, RF crosstalk between one integrated circuit to another integrated circuit on the same silicon substrate is significantly degraded, particularly with regard to long-range crosstalk. This is because radiated electromagnetic energy is freely propagating inside the substrate without any damping, from one circuit to another even if the two circuits are separated by more than 2 millimeters. Such long-range RF crosstalk is particularly problematic from an output of a driver circuit to the input of a transimpedance- amplifier (TIA) circuit because of the large gain of the driver and TIA. In many cases, even a crosstalk level of -70 decibels between driver output to TIA input would induce notable penalty in receiver sensitivity. [0009] Another solution is to engineer silicon substrates to have two types of resistivity - high resistivity in the immediate area near the traveling-wave modulator and a low resistivity in other regions. However, this solution requires complex fabrication cycles in the silicon substrate. [0010] Embodiments described herein provide for inserting one or more metal layers between the optical modulator and the silicon substrates as an RF shield. The metal shield stops the electromagnetic field of the driving signal from reaching the silicon substrate and may reduce or eliminate the substrate RF absorption loss over a wide range of silicon substrate resistivities (e.g., from 0.1 ohm-cm and > 1000 ohm-cm). In addition, the metal shield allows the use of a low resistivity substrate (e.g., between 1 ohm-cm and 20 ohm-cm), when the RF absorption loss can be very high outside the RF shield region, which can be used to considerably suppress the long-range RF crosstalk from one circuit to another circuit on the same substrate. RF simulation shows that the long-range RF crosstalk can be suppressed by more than 10 decibels with proper design parameters compared with high-resistivity substrates” [Chen, ¶¶ [0008] - [0010]].
Chen further, teaches providing a metal shield to stop the electromagnetic field of the driving signal from reaching the substrate “[0015] Semiconductor device 100 includes a metal shield 110 formed/embedded in the dielectric 140. Metal shield 110 may be referred to herein as an RF shield, a metal layer, or a metal shield layer. Metal shield 110 may block the electromagnetic field of the modulator 180 from reaching substrate 150. Substrate 150 may include a silicon substrate. In some embodiments, substrate 150 may be a low resistivity silicon substrate. Embedding metal shield 110 between modulator 180 and substrate 150 allows the use of a low resistivity substrate without degrading the performance of modulator 180 and, at the same time, significantly improving the RF crosstalk between transmitter and receiver circuits. Using the low resistivity substrate allows for regions where low RF losses are desired to be shielded with the metal while leaving other regions without shielding to attenuate stray fields and reduce RF crosstalk. Away from transmission lines, particular in power/ground planes, the use of a low resistivity silicon substrate 150 maximizes damping and suppression of RF crosstalk. [0016] In some embodiments, the metal shield 110 may be a solid metal layer or a series of solid metal blocks underneath modulator 180. In some embodiments, metal shield 110 may be patterned. For example, under transmission lines, a pattern may be added to metal shield 110 to insulate the electromagnetic field from substrate 150 to avoid extra RF loss. In some embodiments, metal shield 110 may be patterned with slots or patterned into connected or isolated bars across the differential electrodes 130 at various intervals. Patterning the metal shield 110 into discrete bars provides RF shielding by terminating the RF shield lines without carrying current along the transmission line (and, therefore, without suffering the extra RF loss typically associated with, for example, a solid metal shield). [0017] In some embodiments, metal shield 110 may be floating and not connected to any other electrodes. In other embodiments, metal shield may be electrically coupled to other metals or electrodes… Claims 1. A device comprising:
an optical modulator formed in a dielectric material; a silicon substrate adjacent the dielectric material; and a metal shield formed in the dielectric material between the optical modulator and the silicon substrate, the metal shield blocking an electromagnetic field of a driving signal of the optical modulator from extending into the silicon substrate” [Chen, ¶¶ [0015] - [0017]; claim 1].
Accordingly, Chen expressly provides the missing shielding-relative-to-other-transmissions/receiver-reception teaching and confirms the known benefit of shielding transmitter RF energy from receiver circuitry. It would have been obvious to employ such shielding in the Nelson/Tu/Tavlykaev/Jacques combination for the same reason taught by Chen, namely to reduce transmitter-to-transmitter and transmitter-to-receiver crosstalk and preserve receiver sensitivity. Accordingly, claim 3 is unpatentable over Nelson in view of Tu, Tavlykaev, Jacques, and Chen.
Further, a person of ordinary skill in the art would have had a clear reason to position the shielding structures so as to isolate one transmitter path from another transmitter path and from receiver reception because the cited art expressly recognizes that the principal problem in dense photonic transceivers is coupling of transmitter-drive RF energy into neighboring channels and especially into receiver/TIA circuitry. Chen explains that such coupling can create receiver-sensitivity penalty, while Tu teaches that shielded MZM transmission structures suppress unwanted modes and improve bandwidth. Accordingly, extending the known MZM shielding/fencing architecture of Tu, Tavlykaev, and Jacques into Nelson's compact transceiver package for the express purpose of transmitter-to-transmitter and transmitter-to-receiver isolation would have been the straightforward application of known RF-isolation techniques to a known and recognized crosstalk problem.
Claim 11
With respect to claim 11, all limitations of claim 1 are taught by Nelson, Tu, Tavlykaev, and Jacques, except wherein claim 11 additionally requires that the set of ground pours and the set of bonding wires suppress crosstalk between transmitter transmissions or between transmitters and receivers at a configured frequency range. However, within analogous art, Tu teaches suppression of parasitic slot-line mode and improved bandwidth using the shield-CPW silicon MZI structure “With a shield coplanar waveguide (CPW) transmission line electrode design was demonstrated. This shield-CPW electrode suppresses the signal distortion caused by the parasitic slot-line (SL) mode and improves the electrical bandwidth and the electro-optical (EO) bandwidth. With the shield-CPW electrodes and 5.5 mm-long phase shifters, the silicon MZI optical modulator delivered an EO bandwidth of above 24 GHz and a V π = 3.0 V was achieved at λ = 1310nm. When modulated at 28-Gb/s data rate, it achieved an extinction ratio of 5.66 dB under a driving voltage of V pp = 1.3 V, corresponding to a power consumption of 0.8 pJ/bit……. The emerging silicon photonics technology has received intense research and development efforts by the optical communication industry due to its superior advantages such as small die sizes, low cost and high integration capability [1–4]. Silicon modulator is one of the most important components for high quality and large volume of data uploading in the future fiberoptic network. Since the comprehensive study of electro-optical (EO) effect in silicon material in 1987 [5], silicon EO modulator has achieved remarkable progress. Recently with reverse biased p-n junction, the data rate of silicon optical modulator has reached over 50-Gb/s for both of 1310 nm and 1550 nm [6–10]. The aggregated data rate and modulation efficiency may be further increased by utilizing the amplitude-shift keying (ASK) and phase-shift keying (PSK) technologies [11, 12]. Chip-scale integration of silicon modulators with wavelength division multiplexing (WDM) multiplexers as well as III-V lasers were also demonstrated [13,14]. For all practical applications, low power consumption and driving voltage are critical performance requitement. That is why in the past, optical modulator fabricated by LiNbO3 and compound material was usually made to have a long phase shifting length. However, such long phase shifter also introduces high microwave loss and velocity mismatching which limit the EO bandwidth. Typically, travelling-wave electrode is implemented to reduce the driving voltage while maintain high EO bandwidth. Coplanar waveguide (CPW) and slot-line (SL) waveguide are two of the most common travelling-wave electrode designs. Between them, CPW is more popular for the advantages of low dispersion, low radiation and the ease of shunt and series connections. However, SL mode can be triggered by the asymmetric CPW electrodes, which in turn becomes the main obstacle for its implementation in practice [15]. When applying CPW electrodes onto optical modulator, the parasitic SL mode can induce strong microwave reflection which suppresses the bandwidth of the modulator. A simple wire-bonding method has been utilized to eliminate this parasitic SL mode [16], but it is not effective and also this approach is not compatible with CMOS process [17]. An air bridge technique, where a shield metal layer is added on top of CPW, has been demonstrated to be more effective for suppressing of this parasitic SL mode [18]. Based on this, shield-CPW electrode has been utilized on LiNbO3 modulators [19]. Nevertheless, there is no report on applying this shield-CPW electrode on silicon modulators. In this work, we implemented a shield-CPW electrode to suppress the unwanted SL modes in silicon modulator. For illustration, with a 5.5 mm-long phase shifter, the driving voltage V pp is reduced to be less than 1.3 V in a single-end MZI silicon modulator to achieve a 28-Gb/s data rate and above 24 GHz EO-S21 −3 dB bandwidth with a power consumption of 0.8 pJ/bit……...” [Tu, Abstract, p. 2-3, Fig. 1.].
Further, Chen teaches that shielding limits substrate propagation of RF energy and addresses long-range crosstalk between transmitter-driver circuitry and receiver/TIA circuitry, thereby reducing receiver-sensitivity penalty “[0008] One solution to avoid the undesired RF absorption loss induced by the silicon substrate is to use high resistivity silicon substrates (e.g., with a resistivity of 750 ohm-cm). Using a high-resistivity silicon substrate poses two possible problems. First, a high-resistivity substrate may become a limitation in wafer availability or foundry fabrication processes (such as through silicon via processes). Second, while the high-resistivity substrate avoids RF absorption loss of the driving signals of the modulators, RF crosstalk between one integrated circuit to another integrated circuit on the same silicon substrate is significantly degraded, particularly with regard to long-range crosstalk. This is because radiated electromagnetic energy is freely propagating inside the substrate without any damping, from one circuit to another even if the two circuits are separated by more than 2 millimeters. Such long-range RF crosstalk is particularly problematic from an output of a driver circuit to the input of a transimpedance- amplifier (TIA) circuit because of the large gain of the driver and TIA. In many cases, even a crosstalk level of -70 decibels between driver output to TIA input would induce notable penalty in receiver sensitivity. [0009] Another solution is to engineer silicon substrates to have two types of resistivity - high resistivity in the immediate area near the traveling-wave modulator and a low resistivity in other regions. However, this solution requires complex fabrication cycles in the silicon substrate. [0010] Embodiments described herein provide for inserting one or more metal layers between the optical modulator and the silicon substrates as an RF shield. The metal shield stops the electromagnetic field of the driving signal from reaching the silicon substrate and may reduce or eliminate the substrate RF absorption loss over a wide range of silicon substrate resistivities (e.g., from 0.1 ohm-cm and > 1000 ohm-cm). In addition, the metal shield allows the use of a low resistivity substrate (e.g., between 1 ohm-cm and 20 ohm-cm), when the RF absorption loss can be very high outside the RF shield region, which can be used to considerably suppress the long-range RF crosstalk from one circuit to another circuit on the same substrate. RF simulation shows that the long-range RF crosstalk can be suppressed by more than 10 decibels with proper design parameters compared with high-resistivity substrates. [0015] Semiconductor device 100 includes a metal shield 110 formed/embedded in the dielectric 140. Metal shield 110 may be referred to herein as an RF shield, a metal layer, or a metal shield layer. Metal shield 110 may block the electromagnetic field of the modulator 180 from reaching substrate 150. Substrate 150 may include a silicon substrate. In some embodiments, substrate 150 may be a low resistivity silicon substrate. Embedding metal shield 110 between modulator 180 and substrate 150 allows the use of a low resistivity substrate without degrading the performance of modulator 180 and, at the same time, significantly improving the RF crosstalk between transmitter and receiver circuits. Using the low resistivity substrate allows for regions where low RF losses are desired to be shielded with the metal while leaving other regions without shielding to attenuate stray fields and reduce RF crosstalk. Away from transmission lines, particular in power/ground planes, the use of a low resistivity silicon substrate 150 maximizes damping and suppression of RF crosstalk. [0016] In some embodiments, the metal shield 110 may be a solid metal layer or a series of solid metal blocks underneath modulator 180. In some embodiments, metal shield 110 may be patterned. For example, under transmission lines, a pattern may be added to metal shield 110 to insulate the electromagnetic field from substrate 150 to avoid extra RF loss. In some embodiments, metal shield 110 may be patterned with slots or patterned into connected or isolated bars across the differential electrodes 130 at various intervals. Patterning the metal shield 110 into discrete bars provides RF shielding by terminating the RF shield lines without carrying current along the transmission line (and, therefore, without suffering the extra RF loss typically associated with, for example, a solid metal shield). [0017] In some embodiments, metal shield 110 may be floating and not connected to any other electrodes. In other embodiments, metal shield may be electrically coupled to other metals or electrodes” [Chen, ¶¶ [0008] - [0010], [0015] - [0017]].
Further, a person of ordinary skill in the art would have been motivated to configure the ground pours and bonding wires to suppress crosstalk in the relevant operating frequency range because the cited art explicitly addresses high-speed RF performance as a frequency-dependent phenomenon. Tu discusses suppression of parasitic mode behavior and bandwidth improvement in the MZM electrode design, and Chen explains that RF-field propagation and crosstalk into receiver circuitry produce measurable penalties. A skilled artisan therefore would have optimized the geometry, spacing, and grounding of the shielding network for the intended operating band of the transceiver, which is no more than routine optimization of result-effective variables in order to obtain the expected reduction in crosstalk over the configured frequency range.
Claims 12,13,14 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over Nelson et al., in view of Evans et al., and further in view of Chen et al.
Claim 12
Nelson teaches an optical communications device in a co-packaged optics/transceiver environment including a photonic integrated circuit disposed in close relation with an electronic integrated circuit. Nelson teaches transmitter-side modulators, receiver-side photodetectors, modulator drivers, TIAs, and a plurality of metal bumps—including solder-topped copper pillar bumps—between the PIC and EIC in an overlap region. Nelson therefore teaches a SiP-type transceiver package including a substrate/PIC package environment, modulators, photodiodes, driver circuitry, TIA circuitry, and micro-bump style interconnection between optical and electronic chips “……... [0039] Each of the copper pillar bumps 140 may have a diameter of between 25 um (microns) and 100 um and a height of between 25 um and 100 um. Each of the copper pillar bumps 140 may be formed on a pad opening (e.g., an opening in an insulating (e.g., silicon dioxide) layer on the front surface of the photonic integrated circuit 105) having a diameter of between 10 um and 70 um.…...[0043] In some embodiments, all of the optoelectronic devices on a photonic integrated circuit 105 are the same. For example, on a photonic integrated circuit 105 that may be referred to as a receiving PIC (Rx PIC), all of the optoelectronic devices are photodetectors, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as an Rx IC), are all transimpedance amplifiers. Similarly, on a photonic integrated circuit 105 that may be referred to as a transmitting PIC (TX PIC), all of the optoelectronic devices may be modulators, and the interface circuits, on the electronic integrated circuit 110 connected to the PIC (which may be referred to as a Tx IC), are all modulator drivers. [0044] FIG. 4 shows a fabrication flow, in some embodiments. A Tx IC is prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing, and an Rx IC is similarly prepared using steps including bumping (with the Ni / Au pads 145), wafer - back grinding, and dicing. Wafer back grinding may be employed to reduce overall thickness of the Tx IC or Rx IC while also reducing case to junction thermal resistance between the IC and ASIC heat sink discussed in further detail below. A TX PIC is prepared using steps including III - V micro - transfer printing (To place the modulators, which may be III - V devices, on the PIC), bumping (with the copper pillar bumps 140), and dicing, and an Rx PIC is prepared using steps including bumping (with the copper pillar bumps 140), and dicing. The Tx IC is then soldered to the Tx PIC to form an assembly that may be referred to as a “Tx sub assembly”, and the Rx IC is then soldered to the Rx PIC to form an assembly that may be referred to as a “Rx sub assembly”. The Tx sub assembly and the Rx sub assembly are then secured to a carrier 315, and fiber pigtails are attached to the PICs, to form an assembly that may be referred to as an optical engine. In these sub-assemblies the PIC may be substantially thicker than the IC especially in the case when the IC is subject to wafer - back grinding during wafer preparation. A thicker PIC reduces warpage to support fine pitch bump assembly in 135 and improves component rigidity after fiber pigtail assembly. In some embodiments, the photonic integrated circuit 105 has a thickness between 500 microns and 1000 microns, e.g., about 680 microns, and the electronic integrated circuit 110 has a thickness between 100 microns and 700 microns, e.g., 580 microns……...” [Nelson ¶¶ [0034] - [0040], [0043] - [0045]; Figs. 1A-5.]
However, within analogous art, Evans teaches a photonic integrated circuit package including a PIC chip, a driver circuit/ASIC, an interposer, conductive traces, ground traces, and conductive vias/bonded interconnections that provide electrical signals from the driver circuitry to the PIC “……FIGS. lA-lD illustrate example arrangements where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having an optical device. FIGS. 2A-2C illustrate a package where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having an optical device. FIGS. 3A-3E illustrate example PIC and interposer lay- 50 outs. FIGS. 4A-4E illustrate example arrangements where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having a traveling wave optical device. FIG. 5 illustrates a package where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having a traveling wave optical device. FIGS. 6A-6C illustrate example PIC and interposer layouts. FIGS. 7A-7B illustrate example PIC and interposer layouts for matching electrical and optical waves. FIG. 8 illustrates example PIC and interposer layouts. FIGS. 9A, 9B, l0A-lOC, llA-llC, 12A-12C, 13A-13D, 14A-14C, and 15A-15C show example packaging arrangements. FIG. 16 illustrates a block diagram of an example multichannel transmitter PIC……... FIGS. 20A-20E show example PIC signal electrode or interposer signal trace configurations FIG. 21 shows a longitudinal cross-sectional view of a portions of an example PIC waveguide……. FIG. 26 illustrates an example layout for a receiver PIC. FIG. 27 illustrates an example layout for a receiver PIC…… FIGS. 32A and 32B illustrate example arrangements where an interposer or a bridge chip provides electrical
interconnects between a lumped TIA and a receiver PIC chip. FIGS. 33A and 33B illustrate example arrangements where an interposer or a bridge chip provides electrical interconnects between a TW TIA and a receiver PIC chip. FIGS. 34 and 35 illustrate example arrangements of a PIC package……… A photonic integrated circuit (PIC) provides a platform for integrating passive and active or multiple active optical devices on a single chip. For example, optical devices for enabling a transmitter, a receiver, or a transceiver may be implemented on a photonic integrated circuit. Active photonic devices are typically controlled by electrical signals, where the electrical signals may be supplied by external circuitry such as an application-specific integrated circuit (ASIC) chip. Conventionally, a single-channel traveling wave modulator may be packaged to an interposer. However, a single-channel configuration may not scale to multiple channels or multiple elements due to constraints such as geometry, electrical/optical routing, excessive PIC size and cost, and/or packaging. Moreover, connections between an ASIC and the interposer to drive a photonic integrated circuit require careful engineering considerations. In addition, an interpose configuration for a traveling wave modulator may not work on a lumped element on the PIC…... rials in a PIC package. The interposers may provide electrical interconnects between an ASIC chip and a PIC chip for controlling lumped-based and/or traveling wave-based active optical devices, such as modulators. Interposers may provide compact connections to multi-element (especially multi-active element) and/or multi-channel PICs……. connect radio frequency (RF) ASICs and RF PIC elements in a short distance with controlled impedance, and they may also connect slower-speed (quasi-direct current (DC)) PIC elements to slower speedASICs…… RF channel pitch
is the physical spacing on a PIC chip or on an ASIC chip that is associated between two channels, which may include I-Q (in-phase and quadrature) modulators or detectors for both polarizations where these are routed and processed separately…... the PIC chip at the same time, i.e., matched phase. As another example, test points may be formed on a conductive 50 trace on an interposer to test a frequency response of an active optical device or combined electro-optic ASIC-interposer-
PIC performance (or subset thereof) …...” [Evans, col. 1, col. 2, col. 3].
Evans also teaches package arrangements for transmitter PICs, receiver PICs, and transceiver PICs, with driver circuits and TIAs associated with those PICs “………The optical signal of each wavelength, or for each channel, is guided to a corresponding photodetector or 15 balanced photodetector that converts the optical signal to an electrical signal. The electrical signal may be provided to a transimpedance amplifier (TIA), which, in turn, provides an electrical output for further processing, such as analog to digital conversion, carrier recovery, and forward error correction. The wavelength-selecting or power splitting functions may be located on the receiver PIC or not on the receiver PIC, depending on the optical system functionality
requirements and intended use. Although optical signal demultiplexing or power splitting are shown located on PIC……… the phase of light propagating in the waveguide in accordance with the applied electrical signal. The capacitance of a traveling wave MZM is distributed along the length of the device, and, therefore, traveling wave MZMs can output optical signals having frequencies higher than those associated with lumped MZMs. However, the length of a traveling wave MZM may be longer than that of a lumped MZM…… The maximum response frequency of lumped photodetectors is generally approximately limited to a value based on an RC time constant, where R and C are the resistance and capacitance of the 25 lumped photodetector, but the impedance associated with an amplifier circuit ( e.g., TIA) and interconnection between the circuit and probe will change the circuit and may reduce or enhance the overall bandwidth of the detection circuit. For instance, the use of a 50-ohm probe may degrade the apparent bandwidth of the photodetector, but the bandwidth may be extended beyond the nominal RC….. FIGS. 34 and 35 illustrate example PIC packaging arrangements that show advantages of using an interposer or a bridge chip to electrically couple active optical elements on a PIC chip and circuitry on an ASIC chip. Referring to FIG. 34, the arrangement 3400 includes a TX PIC chip 3410 and a MZMD chip 3420. The TX PIC chip 3410 includes multiple MZM arms 3402 that are in the interior of the TX PIC chip 3410. The MZM arms 3402 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3420. As illustrated in FIG. 34, if wire bonds are used to establish the electrical connections between the MZM arms 3402 and the MZMD circuit, the distance between the MZM arms 3402 and the MZMD chip 3420 may be greater than 1 mm, which may increase complexity in wiring and may negatively impact the device performance at high speed. Flip-chip or wafer bonding between the TX PIC chip 3410 and the MZMD chip 3420 significantly decreases the wiring length, and allows more complex arrangements of the optical elements on the PIC chip…...” [Evans, col. 4, col. 5, col. 14, Figs. 1A-1C, 5, 11-13].
Further, Chen teaches the explicit shielding rationale that a metal shield is positioned between an optical modulator and the substrate to block the electromagnetic field of the driving signal from extending into the substrate. “[0004] In one embodiment, a device is provided that includes a metal shield to block an electromagnetic field from an optical modulator from extending into a substrate. The device includes an optical modulator formed in a dielectric material; a silicon substrate adjacent the dielectric material; and a metal shield formed in the dielectric material between the optical modulator and the silicon substrate, the metal shield blocking an electromagnetic field of a driving signal of the optical modulator from extending into the silicon substrate…... [0010] Embodiments described herein provide for inserting one or more metal layers between the optical modulator and the silicon substrates as an RF shield. The metal shield stops the electromagnetic field of the driving signal from reaching the silicon substrate and may reduce or eliminate the substrate RF absorption loss over a wide range of silicon substrate resistivities (e.g., from 0.1 ohm-cm and > 1000 ohm-cm). In addition, the metal shield allows the use of a low resistivity substrate (e.g., between 1 ohm-cm and 20 ohm-cm), when the RF absorption loss can be very high outside the RF shield region, which can be used to considerably suppress the long-range RF crosstalk from one circuit to another circuit on the same substrate. RF simulation shows that the long-range RF crosstalk can be suppressed by more than 10 decibels with proper design parameters compared with high-resistivity substrates…...[0015] Semiconductor device 100 includes a metal shield 110 formed/embedded in the dielectric 140. Metal shield 110 may be referred to herein as an RF shield, a metal layer, or a metal shield layer. Metal shield 110 may block the electromagnetic field of the modulator 180 from reaching substrate 150. Substrate 150 may include a silicon substrate. In some embodiments, substrate 150 may be a low resistivity silicon substrate. Embedding metal shield 110 between modulator 180 and substrate 150 allows the use of a low resistivity substrate without degrading the performance of modulator 180 and, at the same time, significantly improving the RF crosstalk between transmitter and receiver circuits. Using the low resistivity substrate allows for regions where low RF losses are desired to be shielded with the metal while leaving other regions without shielding to attenuate stray fields and reduce RF crosstalk. Away from transmission lines, particular in power/ground planes, the use of a low resistivity silicon substrate 150 maximizes damping and suppression of RF crosstalk. [0016] In some embodiments, the metal shield 110 may be a solid metal layer or a series of solid metal blocks underneath modulator 180. In some embodiments, metal shield 110 may be patterned. For example, under transmission lines, a pattern may be added to metal shield 110 to insulate the electromagnetic field from substrate 150 to avoid extra RF loss. In some embodiments, metal shield 110 may be patterned with slots or patterned into connected or isolated bars across the differential electrodes 130 at various intervals. Patterning the metal shield 110 into discrete bars provides RF shielding by terminating the RF shield lines without carrying current along the transmission line (and, therefore, without suffering the extra RF loss typically associated with, for example, a solid metal shield). [0017] In some embodiments, metal shield 110 may be floating and not connected to any other electrodes. In other embodiments, metal shield may be electrically coupled to other metals or electrodes. [0018] Substrate 150 may be coupled to packaging substrate 170 with interface material 160. Packaging
substrate 170 may protect semiconductor device 100 from an outside environment and may allow electrical connection to the elements in the semiconductor device 100” [Chen ¶¶ [0004], [0010], [0015] - [0018]].
For purposes of this rejection, the claim phrase that the micro-bumps are “associated with electromagnetically confining transmissions associated with the driver chip” is satisfied because the micro-bumps are part of the short controlled-impedance driver-to-PIC electrical and ground architecture used together with Evans’s ground traces and vias and Chen’s shielding arrangement. The claim does not require that the micro-bumps, standing alone, perform all of the confinement; it is sufficient that they participate in the conductive launch and return structure by which the driver signal is delivered into a shielded or electromagnetically confined modulator region.
It would have been obvious to combine Nelson with Evans and Chen because Nelson already teaches the co-packaged optics/transceiver platform with copper pillar bumps and driver/TIA associations, Evans teaches a PIC package architecture using interposer traces, ground traces, and conductive vias for delivering driver signals and grounds to PIC optical devices, and Chen provides the known reason to arrange such conductive structures as part of an electromagnetic-confinement architecture for modulator drive signals. The combination would have predictably yielded a SiP transceiver comprising a substrate, a PIC disposed on the substrate, a set of MZMs, a set of photodiodes, a driver chip, a TIA chip, and micro-bumps connected to the driver chip, where the micro-bumps participate in a driver-to-PIC architecture used in conjunction with electromagnetic confinement/shielding of modulator transmissions.
Further, a person of ordinary skill in the art would have been motivated to combine Nelson, Evans, and Chen because Nelson already teaches the core co-packaged PIC/EIC transceiver structure with micro-bump-type interconnects, Evans teaches how such packages use conductive traces, ground traces, and conductive vias/interposer structures to couple driver circuitry to PIC optical devices, and Chen provides the explicit reason to arrange conductive package structures as part of an electromagnetic-confinement architecture for modulator drive signals. In such a package, the micro-bumps are not merely mechanical attachment features; they are part of the electrical path between the driver chip and the PIC. A skilled artisan would therefore have found it obvious to use the known micro-bump interconnect architecture in conjunction with known grounding and shielding practices to shorten electrical paths, control impedance, and suppress substrate-coupled or adjacent-channel RF leakage.
Claim 13
With respect to claim 13, all limitations of claim 12 are taught by Nelson, Evans, and Chen, except wherein claim 13 additionally requires that the driver chip is disposed on the substrate and that the set of micro-bumps is disposed between the driver circuit and the substrate. However, within analogous art, Evans teaches packages in which the driver IC is provided on a substrate with solder bumps/interposer connections in the package architecture “……. FIG. l0C illustrates an example packaging arrangement 1013. The example shown in FIG. l0C is similar to that shown in FIG. 10B, but the segmented signal electrodes on the PIC 1026 are bonded to a bridge chip 1022 without an interposer. FIG. l0C further shows a plan view 1015 of the bottom surface of the bridge chip 1022. Since the signal electrodes on the PIC 1026 are segmented, each segment is contacted by a corresponding metal bumps or connections. The segments are provided along a length corresponding to the interposer signal traces. Accordingly, bond contacts are likewise provided along the length of the signal trace of the bridge chip 1022. In some implementations, the DC control for the PIC 1026 may be wire-bonded to the PIC 1026. FIG. llA shows a simplified plan view of an example package 1100 consistent with a further aspect of the present disclosure. The package 1100 shown in FIG. llA includes a mounting substrate 1102, upon which two control circuit
integrated circuits (ICs) 1104 and 1106, a driver IC 1108, and a transmitter PIC 1110 including integrated widely tunable lasers (WTLs) and modulators are provided. The modulators may be lumped MZMs or TW MZMs. FIG. 11B shows a cross section of the package 1100 consistent with an aspect of the present disclosure. As shown in FIG. 11B, the package 1100 further includes a top covering or package floor 1112. The substrate 1114 shown in FIG. 11B constitutes
a base or mount having first gold or solder bumps 1116 that receive and output electrical signals for the control and driver ICs from external circuitry (not shown). Hereafter, whenever solder bumps are mentioned, they may refer to either gold or solder bumps inclusively. The package 1110 also includes a DC ASIC 1118 that provides DC voltages to appropriately bias certain PIC elements. The DC ASIC 1118, as well as the driver IC 1108 and the interposer 1120 may be flip chip or solder bonded via second solder bumps 1122 to the substrate 1114. The second solder bumps 1122 may be micro-solder bumps. Drive signals output from the driver IC 1108 are supplied to selected second solder bumps 1122 adjacent to the driver IC 1108 and are then transmitted on traces on the substrate 1114 to second solder bumps 1122 that connect to signal traces on the interposer 1120. The
second solder bumps may include either gold, copper, indium, or other metal. The signal traces supply the drive signals to the MZM signal electrodes in a manner similar to that described above. Electrical contacts on the interposer are aligned to the underlying solder bumps. As further shown in the cross-sectional view of FIG. 11B, a heat spreader or heat sink 1124 is provided for the driver IC 1108, and a TEC 1126 is provided to cool the transmitter PIC 1110. A compliant thermal filler 1128a and 1128b may also be provided to fill the space between the heat spreader…….” [Evans, col. 14, col. 15, col. 26, Figs. 11A-11C, 13A-13D].
Further, a person of ordinary skill in the art would have been motivated to place the driver chip on the substrate with the micro-bumps between the driver chip and the substrate because substrate-side flip-chip or bump-bond mounting is a conventional way to achieve a short electrical path, good mechanical support, and favorable thermal dissipation for high-speed driver circuitry. Evans expressly teaches substrate/interposer-based driver-to-PIC package architectures, and adapting Nelson's transceiver package to use that known mounting option would have been a routine packaging decision yielding the expected benefits of lower parasitic inductance and improved RF launch into the PIC-side modulator region.
Claim 14
With respect to claim 14, all limitations of claim 12 are taught by Nelson, Evans, and Chen, except wherein claim 14 additionally requires that the driver chip is disposed on the PIC and that the set of micro-bumps is disposed between the driver circuit and the PIC.
However, within analogous art, Nelson expressly teaches that the photonic integrated circuit and electronic integrated circuit overlap and are electrically connected through a plurality of metal bumps, including solder-topped copper pillar bumps, thereby teaching a chip-on-chip bump-bond arrangement meeting this limitation “[0037] The photonic integrated circuit 105 and the electronic integrated circuit 110 may be offset from each other so that each of the photonic integrated circuit 105 and the electronic integrated circuit 110 overhangs the other , as illustrated in FIG . 1A . In particular , a first portion 115 of the electronic integrated circuit 110 may overhang a first edge 120 of the photonic integrated circuit 105 and a first portion 125 of the photonic integrated circuit 105 may overhang a first edge 130 of the electronic integrated circuit 110. Refer ring to FIG . 1B , the photonic integrated circuit 105…….. [0038] In the area of overlap 135 the photonic integrated circuit 105 and the electronic integrated circuit 110 may be secured together and electrically connected through a plurality of metal bumps . For example , a plurality of solder topped copper pillar bumps 140 (e.g. Cu / Ni / SnAg bumps) may be formed on the front surface of the photonic integrated circuit 105 , and a corresponding plurality of pads 145 ( e.g. , Ni / Au pads ) may be formed on the front surface of the electronic integrated circuit 110…………… [ 0039 ] Each of the copper pillar bumps 140 may have a diameter of between 25 um ( microns ) and 100 um and a height of between 25 um and 100 um . Each of the copper pillar bumps 140 may be formed on a pad opening ( e.g. , an opening in an insulating ( e.g. , silicon dioxide ) layer on the front surface of the photonic integrated circuit 105 ) having a diameter of between 10 um and 70 um . [0040] Referring to FIG . 2A , the copper pillar bumps 140 in the area of overlap 135 may be on a grid ( e.g. , a grid with a pitch between 50 um and 150 um ) substantially filling the area of overlap 135 , which may be rectangular as shown . In some embodiments, the corner bumps may be omitted as shown, for stress relief . The pads 145 ( e.g. , Ni / Au pads ) on the electronic integrated circuit 110 may have a diameter exceeding 100 um ( in an embodiment in which the pitch of the grid exceeds 100 um ) . The pitch of the copper pillar bumps 140 may be chosen based on design channel count and density. For example , reducing bump pitch ( and channel pitch accordingly ) reduces the width of the PIC 105 and electronic integrated circuit 110” [Nelson, ¶¶ [0037] - [0040]; Figs. 1A-2A].
Further, a person of ordinary skill in the art would have been motivated to dispose the driver chip on the PIC with the micro-bumps between the driver chip and the PIC because Nelson's overlap-region copper-pillar-bump architecture already teaches extremely close optical/electrical chip coupling. Mounting the driver directly on the PIC would have been recognized as a known alternative packaging option for further shortening the drive path to the MZMs, reducing interconnect discontinuity, and improving bandwidth and signal integrity. Selecting that known direct-on-PIC mounting arrangement therefore would have been an obvious design choice within the same high-speed silicon-photonics packaging space.
Claim 15
With respect to claim 15, all limitations of claim 12 are taught by Nelson, Evans, and Chen, except wherein claim 15 additionally requires that the set of micro-bumps includes a set of copper pillar micro-bumps. However, within analogous art, Nelson expressly teaches solder-topped copper pillar bumps used to connect the PIC and EIC “[0037] The photonic integrated circuit 105 and the electronic integrated circuit 110 may be offset from each other so that each of the photonic integrated circuit 105 and the electronic integrated circuit 110 overhangs the other , as illustrated in FIG . 1A . In particular , a first portion 115 of the electronic integrated circuit 110 may overhang a first edge 120 of the photonic integrated circuit 105 and a first portion 125 of the photonic integrated circuit 105 may overhang a first edge 130 of the electronic integrated circuit 110. Refer ring to FIG . 1B , the photonic integrated circuit 105…….. [0038] In the area of overlap 135 the photonic integrated circuit 105 and the electronic integrated circuit 110 may be secured together and electrically connected through a plurality of metal bumps . For example , a plurality of solder topped copper pillar bumps 140 (e.g. Cu / Ni / SnAg bumps) may be formed on the front surface of the photonic integrated circuit 105 , and a corresponding plurality of pads 145 ( e.g. , Ni / Au pads ) may be formed on the front surface of the electronic integrated circuit 110……………” [Nelson ¶¶ [0038] - [0040]; Fig. 3.].
Further, a person of ordinary skill in the art would have been motivated to use copper pillar micro-bumps because Nelson expressly teaches solder-topped copper pillar bumps, and such bumps were well known in high-speed packaging to provide fine pitch, low parasitic inductance, good current-carrying capability, and robust mechanical attachment. Selecting that known bump technology for the micro-bumps of claim 12 would have been an ordinary packaging choice made for its predictable and established electrical and manufacturing advantages.
Claim 16 is rejected under 35 U.S.C. § 103 as being unpatentable over Nelson et al., in view of Evans et al., and further in view of Chen et al. and further in view of Tu et al., and Tavlykaev et al., and further in view of Jacques et al.
Claim 16
It would have been obvious to provide such grounded conductive regions within the PIC-side modulator region of the Nelson and Evans package because the cited art teaches that shielding is most effective when positioned where the high-speed drive field is launched and where the return current must be controlled. Locating PIC-side ground pours adjacent the MZMs would have been the natural implementation of the known RF-fence concept in a compact SiP package, with the predictable benefits of reduced field spreading, improved impedance control, and reduced crosstalk into neighboring structures.
“…… [0006] The electrode structure shown in FIG. 1 is a microwave Coplanar Waveguide (CPW) aligned with respect to the waveguide Structure in Such a way that the interferometer arms 104,105 are positioned in the electrode gaps 107 and run alongside the gap edges (in X-cut devices). A CPW electrode structure includes a hot central (signal) electrode 108 and two ground planes or electrodes 109,110 formed on opposite sides of the central electrode 108. Microwave (modulating) signals are provided to the signal electrode 108 from a microwave Source 111, via a connector and a microwave cable. The widths of the gap 107 and hot electrode 108 are tapered at the input and output. Advantageously, a CPW structure with properly chosen widths of the gap 107 and hot electrode 108 at the modulator input has a microwave field distribution closely matching that of a coaxial cable connecting the modulator to the microwave Source 111. [0007] FIG. 1 shows an intensity modulator 100 with the So-called “push-pull configuration, wherein the electric field crossing one interferometer arm 104 is opposite to that crossing the other 105. AS Such, the electro-optic phase shifts induced in the two arms 104, 105 are of equal magnitude but opposite sign. Effectively, the intensity modulator 100 incorporates two phase modulators, represented by the two arms 104, 105, which are driven 180 degrees out of phase with respect to each other. The outputs of the two phase modulators are combined to result in an intensity modulation that depends on the relative phase difference between the arms 104, 105. In the push-pull configuration, the phase difference doubles compared to the phase shift in each arm and the half-wave Voltage of the modulator is therefore halved, which represents a significant advantage over other Schemes……” [Tavlykaev, ¶¶ [0005] - [0007], [0036] - [0039]].
For purposes of this rejection, the claimed “ground pours” are reasonably read on PIC-side grounded conductive regions or ground-plane portions associated with the MZM transmission structure, not merely on any particular polygonal layout convention. Under the broadest reasonable interpretation, the claim is satisfied so long as those grounded conductive regions are disposed in the PIC and participate in confining the driver-launched electromagnetic field around the MZM path.
Additionally, Jacques teaches G-S-S-S-G/ground-electrode differential-drive implementations with driver-chip ground contacts “[0048] Some of the described approaches are directed to achieving optimal interconnection between a differential driver and a modulator that has a radio frequency ( rf ) transmission line electrode configuration of the type S - S – S or G - S - S - S - G ( e.g. , as shown in FIGS . 1A - 1D ) . In some of the examples described herein , the S - S - S electrode configuration is used to show implementations of a differential drive electrode configuration for an E - O crystal TW - MZM , but the techniques described herein can also be applied to G - S – S - S - G electrode configuration , and other integrated modulator technologies that may benefit from S - S - S or G - S - S - S – G differential electrode configurations , such as SOH modulators . In some implementations, the S signal from a 2 – port driver is split on - chip in interconnection circuitry that is fabricated on , or bonded to , the same die as the MZM . In other implementations , a 3 - port driver provides an S signal and two S signals at respective driver output ports , and the S signal is split within the driver ( e.g. , as shown in FIG . 2A ) , and in some implementations , at the transistor level ( e.g. , as shown in FIG . 2B ) . In some implementations , a passive termination circuit can be used to properly bias the driver output signals for an open - collector ( OC ) architecture . In either the 2 - port or 3 - port driver implementations, the connections between the driver and the modulator can be formed using any of a variety of techniques, including wire - bonds , or a controlled collapse chip connection , also called flip - chip or C4 connection . Also , the output ports of the driver may serve as input ports of the TW - MZM , including any wire - bonds or other structures extending to various portions of the TW – MZM. [0055] Referring to FIG . 4A , a driver chip 400 is connected to an optoelectronic chip 402A by a drive signal interconnection structure 404A that is formed by wire – bonds 406 and 408 and metal structures within a single metal layer of the optoelectronic chip 402A . A TW - MZM is formed on the optoelectronic chip 402A by structures that include a center electrode 410 , outer electrodes 411 and 412 , and a Mach - Zehnder interferometer with waveguide arms 413 and 414. The wire - bond 406 is formed between an S contact pad of the driver chip 400 and an outer electrode contact pad 415 in a metal layer of the optoelectronic chip 402A . A V – shaped metal trace connection 416 in the same metal layer connects to each of the outer electrodes 411 and 412. The wire – bond 408 , which is longer than the wire - bond 406 , is formed between an S contact pad of the driver chip 400 and a center electrode contact pad 418. The lengths of the wire – bonds 406 and 408 are selected so that the propagation delay across a wide bandwidth for rf signals between the driver and the beginning of the transmission lines of the TW - MZM are substantially equal . This propagation delay matching pre serves relative phase shifts between the S and S signals . In some implementations , wedge - bonds can be installed to achieve relatively precise relative timing for matching the propagation delay . The driver chip 400 can also optionally include ground contacts ( G ) as shown in this example . [0056] Between the contact pad 418 and the center electrode 410 is an impedance buffer 420 , which compensates for an impedance difference between the impedance for the parallel combination of split S signals and the impedance of the single S signal at the input ports of the optoelectronic chip 402A , where the input ports are defined at the beginning of the wire - bonds 406 and 408 , respectively . Alternatively , in other examples , there can be impedance buffers between the ends of the v - shaped metal trace connection 416 and the outer electrodes 411 and 412 , instead of , or in addition to the location shown in this example . The change in impedance that is provided by the impedance buffer 420 can be configured based on various structural factors , including the exact coplanar waveguide geometry of the transmission lines , such as the width and / or spacing of the three metal traces that form the electrodes of the transmission lines . The impedance buffer 420 can be formed from one or more layers of resistive material , and / or conductive material , and can include circuit components such as resonant stubs or transformers . The components , materials and / or structural geometries can be configured to provide inductance and / or capacitance that may be needed to compensate for any impedance mismatch over a broad rf signal band width . An impedance buffer 420 may not be needed in some implementations if the input impedances are matched based on the geometries of the electrodes 410 , 411 , and 412. For example , if the outer electrodes 411 and 412 are each half the width of the center electrode 410 so that their resistance is about twice as high , then their equivalent combined parallel impedance at the input port for the S signal may be substantially equal to the impedance at the input port for the S signal . Or , more generally , the outer electrodes 411 and 412 may have an equivalent parallel characteristic impedance Z that is substantially equal to the characteristic impedance Zo of the center electrode 410” [Jacques, ¶¶ [0048], [0055]-[0056]].
Within analogous art, Chen teaches that the shield/ground metal associated with the modulator is used to confine the electromagnetic field of the driver signal and improve transmitter/receiver isolation “[0010] Embodiments described herein provide for inserting one or more metal layers between the optical modulator and the silicon substrates as an RF shield. The metal shield stops the electromagnetic field of the driving signal from reaching the silicon substrate and may reduce or eliminate the substrate RF absorption loss over a wide range of silicon substrate resistivities (e.g., from 0.1 ohm-cm and > 1000 ohm-cm). In addition, the metal shield allows the use of a low resistivity substrate (e.g., between 1 ohm-cm and 20 ohm-cm), when the RF absorption loss can be very high outside the RF shield region, which can be used to considerably suppress the long-range RF crosstalk from one circuit to another circuit on the same substrate. RF simulation shows that the long-range RF crosstalk can be suppressed by more than 10 decibels with proper design parameters compared with high-resistivity substrates…...[0015] Semiconductor device 100 includes a metal shield 110 formed/embedded in the dielectric 140. Metal shield 110 may be referred to herein as an RF shield, a metal layer, or a metal shield layer. Metal shield 110 may block the electromagnetic field of the modulator 180 from reaching substrate 150. Substrate 150 may include a silicon substrate. In some embodiments, substrate 150 may be a low resistivity silicon substrate. Embedding metal shield 110 between modulator 180 and substrate 150 allows the use of a low resistivity substrate without degrading the performance of modulator 180 and, at the same time, significantly improving the RF crosstalk between transmitter and receiver circuits. Using the low resistivity substrate allows for regions where low RF losses are desired to be shielded with the metal while leaving other regions without shielding to attenuate stray fields and reduce RF crosstalk. Away from transmission lines, particular in power/ground planes, the use of a low resistivity silicon substrate 150 maximizes damping and suppression of RF crosstalk. [0016] In some embodiments, the metal shield 110 may be a solid metal layer or a series of solid metal blocks underneath modulator 180. In some embodiments, metal shield 110 may be patterned. For example, under transmission lines, a pattern may be added to metal shield 110 to insulate the electromagnetic field from substrate 150 to avoid extra RF loss. In some embodiments, metal shield 110 may be patterned with slots or patterned into connected or isolated bars across the differential electrodes 130 at various intervals. Patterning the metal shield 110 into discrete bars provides RF shielding by terminating the RF shield lines without carrying current along the transmission line (and, therefore, without suffering the extra RF loss typically associated with, for example, a solid metal shield). [0017] In some embodiments, metal shield 110 may be floating and not connected to any other electrodes. In other embodiments, metal shield may be electrically coupled to other metals or electrodes” [Chen ¶¶ [0010], [0015] - [0017]].
It would have been obvious to provide such ground structures within the PIC-side modulator region of the Nelson/Evans package for the same known purpose.
Further, a person of ordinary skill in the art would have been motivated to provide a set of ground pours in the PIC associated with the MZMs and the driver chip because the cited modulator-shielding references teach that shielding is most effective when positioned at the driven modulator region and tied into the driver-side ground architecture. In the Nelson/Evans package, incorporating PIC-side ground pours near the MZMs would have been the logical location for implementing the known RF fence while maintaining a short connection to the driver-side return network. The resulting arrangement predictably confines the electromagnetic field where it is generated, reduces propagation into neighboring channels or the substrate, and improves the electrical environment of the driver-to-MZM path.
Claim 17 is rejected under 35 U.S.C. § 103 as being unpatentable over Nelson et al., in view of Evans et al., and further in view of Chen et al. and further in view of Tavlykaev et al.
Claim 17
For purposes of this rejection, the recited “ground plane within the substrate” is reasonably read on the package or interposer ground-plane or ground-trace region within the substrate stack of Evans and Nelson, and the listed connection options are satisfied by the known use of vias, bumps, copper pillars, and bond-wire style grounded interconnects to couple local PIC shielding structures into the broader package ground. The claim does not require a single exclusive vertical interconnect type, and the cited references collectively teach the ordinary menu of known grounding connections recited in the claim.
Claim 17 is addressed on its intended interpretation notwithstanding the rejection under 35 U.S.C. 112(b). With respect to claim 17, all limitations of claim 12 are taught by Nelson, Evans and Chen, except wherein claim 17 additionally requires a ground plane within the substrate, wherein the set of ground pours is connected to the ground plane via at least one of one or more bonding wires, one or more copper pillars, one or more through-silicon vias (TSVs), or the set of micro-bumps. However, within analogous art, Nelson teaches copper pillar bumps “…. [0039] Each of the copper pillar bumps 140 may have a diameter of between 25 um (microns) and 100 um and a height of between 25 um and 100 um. Each of the copper pillar bumps 140 may be formed on a pad opening (e.g., an opening in an insulating (e.g., silicon dioxide) layer on the front surface of the photonic integrated circuit 105) having a diameter of between 10 um and 70 um. [0040] Referring to FIG. 2A, the copper pillar bumps 140 in the area of overlap 135 may be on a grid (e.g., a grid with a pitch between 50 um and 150 um) substantially filling the area of overlap 135, which may be rectangular as shown. In some embodiments, the corner bumps may be omitted as shown, for stress relief. The pads 145 (e.g., Ni / Au pads) on the electronic integrated circuit 110 may have a diameter exceeding 100 um (in an embodiment in which the pitch of the grid exceeds 100 um). The pitch of the copper pillar bumps 140 may be chosen based on design channel count and density. For example, reducing bump pitch (and channel pitch accordingly) reduces the width of the PIC 105 and electronic integrated circuit 110. A reduction in chip width increases bandwidth density and reduces overall product form factor within high volume manufacturing limits. For example, in some embodiments the optical engines dis cussed herein are populated on the edge of the printed circuit board 310 which may form the substrate of the switch ASIC package (FIG. 5. This substrate form factor is ultimately determined by the widths of the PIC 105 and the electronic integrated circuit 110, which is dependent on bump pitch. Furthermore, reducing the substrate form factor improves the aforementioned serializer - deserializer performance and reduces cost in high volume. This is discussed in further detail below. Each of the high-speed channels 150 may be connected by a pair of conductive traces on the front surface of the electronic integrated circuit 110 to a respective pair of pads, or "connector bumps” (e.g., Ni / Au pads) in the first portion 115 of the front surface of the electronic integrated circuit 110 as part of a connection (e.g., an XSR or USR connection, or other suitable serial electrical connection) to, e.g., a switch ASIC, as discussed in further detail below. The pads in the first portion 115 of the front surface of the electronic integrated circuit 110 may be similar to, although they may have different dimensions from, the pads on the front surface of the electronic integrated circuit 110 in the area of overlap 135. FIG. 2B shows an example of a candidate pin assignment for the connector bumps. The corner connector bumps may be absent (as shown in FIG. 2A) or present (as shown in FIG. 2B) ……” [Nelson ¶¶ [0038] - [0040]].
Evans teaches ground traces and conductive vias in an interposer/PIC package to provide signal and ground connectivity between driver-side circuitry and PIC-side electrodes/grounds, including package arrangements with transceiver PICs “……FIGS. lA-lD illustrate example arrangements where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having an optical device. FIGS. 2A-2C illustrate a package where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having an optical device. FIGS. 3A-3E illustrate example PIC and interposer lay- 50 outs. FIGS. 4A-4E illustrate example arrangements where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having a traveling wave optical device. FIG. 5 illustrates a package where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having a traveling wave optical device. FIGS. 6A-6C illustrate example PIC and interposer layouts. FIGS. 7A-7B illustrate example PIC and interposer layouts for matching electrical and optical waves. FIG. 8 illustrates example PIC and interposer layouts. FIGS. 9A, 9B, l0A-lOC, llA-llC, 12A-12C, 13A-13D, 14A-14C, and 15A-15C show example packaging arrangements. FIG. 16 illustrates a block diagram of an example multichannel transmitter PIC……...FIGS. 34 and 35 illustrate example PIC packaging arrangements that show advantages of using an interposer or a bridge chip to electrically couple active optical elements on a PIC chip and circuitry on an ASIC chip. Referring to FIG. 34, the arrangement 3400 includes a TX PIC chip 3410 and a MZMD chip 3420. The TX PIC chip 3410 includes multiple MZM arms 3402 that are in the interior of the TX PIC chip 3410. The MZM arms 3402 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3420. As illustrated in FIG. 34, if wire bonds are used to establish the electrical connections between the MZM arms 3402 and the MZMD circuit, the distance between the MZM arms 3402 and the MZMD chip 3420 may be greater than 1 mm, which may increase complexity in wiring and may negatively impact the device performance at high speed. Flip-chip or wafer bonding between the TX PIC chip 3410 and the MZMD chip 3420 significantly decreases the wiring length, and allows more complex arrangements of the optical elements on the PIC chip. Referring to FIG. 35, the arrangement 3500 includes a TX PIC chip 3510 and a MZMD chip 3520. The TX PIC chip 3510 includes multiple MZM arms 3502 that are arranged along the edge of the TX PIC chip 3510. The MZM arms 3502 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3520. As illustrated in FIG. 35, if wire bonds are used to establish the electrical…….” [Evans, col. 1, col. 4, col. 5, col. 14, Figs. 1A-1C, 5, 13A-13D].
Further, Tavlykaev teaches bonding wires joining ground structures. Thus, on the intended interpretation, the cited art collectively teaches connection of PIC-side grounded shield structures to substrate/package ground through vias, bumps, and bond-wire style grounded interconnections “[0036] FIG. 4 illustrates one embodiment of the present invention, which is an optical (phase) modulator 400, including a channel optical waveguide 409 and two CPW segments 401, 402. The CPW segments provide mode symmetry when RF is coupled into and out of the electrode structure. The RF traverses a (i.e., asymmetric) CPS line segment 403, which extends along the interaction length 404 of the modulator 400, and imparts electro-optic modulation to the optical waveguide 409. Each CPW segment 401, 402 includes a hot central (signal) electrode 405 and two ground planes or electrodes 406, 407, 414 formed on opposite sides of the central electrode 405. Bonding wires 411 are used to connect ground plane 407 with ground planes 406, 414 of CPW sections 401, 402 at their interfaces with CPS section 403. This is done, in accordance with the principles of microwave theory, in order to provide current paths from/to the two ground CPW planes 406, 414 to/from the single ground plane 407 of the CPS section and to ensure, in terms of electro-magnetic wave distributions, efficient transformation of the CPW microwave mode to that of the CPS, and Vice versa. [0037] The phase modulator according to one embodiment of the present invention, as shown in FIG. 4, includes advantages previously achieved individually with CPW and CPS structures. Indeed, the CPW segments 401, 402 ensure efficient coupling to an input coaxial cable 408 and a termination circuitry, if any (not shown in FIG. 4). [0038] According to microwave theory, good overlap between the microwave field distribution of a coaxial cable and that of a CPW can be achieved…...” [Tavlykaev, ¶¶ [0036] - [0039]].
Further, on the intended interpretation, a person of ordinary skill in the art would have been motivated to connect PIC-side ground pours to a substrate ground plane through one or more bonding wires, copper pillars, TSVs, or micro-bumps because Evans teaches that the package already employs conductive vias and ground traces to couple electronic and photonic structures across the interposer/substrate stack, Nelson teaches copper pillar bumps, and Tavlykaev teaches bond-wire ground bridges. A skilled artisan would have selected one or more of those known vertical or interlevel interconnect structures to tie the local PIC shielding network into the broader substrate ground plane, thereby lowering ground impedance, improving shielding continuity, and giving the high-speed return current a controlled path. Doing so would have been a predictable packaging refinement rather than a patentably distinct departure from the known art.
Claims 18 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over Evans et al., in view of Tu et al., and further in view of Chen et al.
Claim 18
Further, at least one confinement component is reasonably read as grounded in the combined teachings because Tu’s shielded CPW/MZM structure employs grounded shield conductors and Chen teaches a metal shield that may be electrically coupled to other metals or electrodes in the package. A skilled artisan would have understood that tying at least one shielding component to the transceiver ground is the ordinary way to make the shielding structure an effective RF return and confinement element rather than a merely decorative conductor.
Evans teaches transceiver PICs including transmitter and receiver functions on the same chip, and teaches that such transceiver PICs include modulators and waveguide photodiodes “FIG. 3B illustrates an example layout 303. FIG. 3B illustrates a portion of a PIC chip 332 that includes alternative configuration to the lumped "push-pull" MZM. Note that in the layout 303, the portions of the MZM in which light is split and combined are not shown. The lumped MZM includes a pair of waveguides 336a and 336b. The lumped MZM further includes lumped signal electrodes 330a and 330b that overlay each waveguide. The PIC chip 332……… the PIC chip 332. Although not shown, the interposer 334 may be electrically coupled to one or more ASIC chips such as a MZM driver. The PIC chip 332 may………. FIGS. 34 and 35 illustrate example PIC packaging arrangements that show advantages of using an interposer or a bridge chip to electrically couple active optical elements on a PIC chip and circuitry on an ASIC chip. Referring to FIG. 34, the arrangement 3400 includes a TX PIC chip 3410 and a MZMD chip 3420. The TX PIC chip 3410 includes multiple MZM arms 3402 that are in the interior of the TX PIC chip 3410………… between the TX PIC chip 3510 and the MZMD chip 3520 allows more complex arrangements of the optical elements on the PIC chip. FIG. 3C illustrates an example layout 305. FIG. 3C illustrates a portion of a PIC chip 362 that includes a lumped waveguide photodiode. The lumped waveguide photodiode includes a waveguide 366. The lumped waveguide photodiode further includes lumped signal electrodes 368a and 368b. The PIC chip 302………... The interposer 364 includes bond contacts 378a-378c, which enable electrical connections from/to the interposer 364 to/from the PIC chip 362. Although not shown, the interposer 364 may be electrically coupled to one or more ASIC chips such as a TIA. The PIC chip 332……… connections to the PIC chip 662. Although not shown, the interposer 664 may be electrically coupled to one or more ASIC chips such as a TIA. The PIC chip 662 may be bonded to the interposer 664 in a marmer similar……... 724 shown in the example interposer layout 701 in FIG. 7B may be provided to supply non-push-pull velocity mismatched drive signals to the electrode segments 636a and 636b in PIC 632 as shown in FIG. 6B, for example. FIG. 8 shows further examples of signal electrode segments, bond contacts, and signal traces consistent with the present disclosure. Referring to the example PIC layout 801, each signal electrode segment may include a pad portion 802a and a T-shaped portion 802b connected to the pad portion 802a. The pad portion 802a may be aligned with a bond contact 804 formed on an interposer 810, which, in turn, is aligned with a signal trace 806 on a surface of the interposer 810 opposite the PIC 801. The bond contact 804 may be electrically coupled to the signal trace 806 through a via (not shown). As described above in reference to FIGS. 4A-4C, the drive signal may be applied to the signal trace 806, down the via (not shown) to the bond contact 804, to the PIC pad portion 802a……” [Evans, col. 14, col. 15, col. 24, Figs. 13A-13D, 28-29].
However, within analogous art, Tu teaches silicon Mach-Zehnder modulators with shield-CPW structures that suppress parasitic slot-line mode and improve bandwidth “With a shield coplanar waveguide (CPW) transmission line electrode design was demonstrated. This shield-CPW electrode suppresses the signal distortion caused by the parasitic slot-line (SL) mode and improves the electrical bandwidth and the electro-optical (EO) bandwidth. With the shield-CPW electrodes and 5.5 mm-long phase shifters, the silicon MZI optical modulator delivered an EO bandwidth of above 24 GHz and a V π = 3.0 V was achieved at λ = 1310nm. When modulated at 28-Gb/s data rate, it achieved an extinction ratio of 5.66 dB under a driving voltage of V pp = 1.3 V, corresponding to a power consumption of 0.8 pJ/bit……. The emerging silicon photonics technology has received intense research and development efforts by the optical communication industry due to its superior advantages such as small die sizes, low cost and high integration capability [1–4]. Silicon modulator is one of the most important components for high quality and large volume of data uploading in the future fiberoptic network. Since the comprehensive study of electro-optical (EO) effect in silicon material in 1987 [5], silicon EO modulator has achieved remarkable progress. Recently with reverse biased p-n junction, the data rate of silicon optical modulator has reached over 50-Gb/s for both of 1310 nm and 1550 nm [6–10]. The aggregated data rate and modulation efficiency may be further increased by utilizing the amplitude-shift keying (ASK) and phase-shift keying (PSK) technologies [11, 12]. Chip-scale integration of silicon modulators with wavelength division multiplexing (WDM) multiplexers as well as III-V lasers were also demonstrated [13,14]. For all practical applications, low power consumption and driving voltage are critical performance requitement. That is why in the past, optical modulator fabricated by LiNbO3 and compound material was usually made to have a long phase shifting length. However, such long phase shifter also introduces high microwave loss and velocity mismatching which limit the EO bandwidth. Typically, travelling-wave electrode is implemented to reduce the driving voltage while maintain high EO bandwidth. Coplanar waveguide (CPW) and slot-line (SL) waveguide are two of the most common travelling-wave electrode designs. Between them, CPW is more popular for the advantages of low dispersion, low radiation and the ease of shunt and series connections. However, SL mode can be triggered by the asymmetric CPW electrodes, which in turn becomes the main obstacle for its implementation in practice [15]. When applying CPW electrodes onto optical modulator, the parasitic SL mode can induce strong microwave reflection which suppresses the bandwidth of the modulator. A simple wire-bonding method has been utilized to eliminate this parasitic SL mode [16], but it is not effective and also this approach is not compatible with CMOS process [17]. An air bridge technique, where a shield metal layer is added on top of CPW, has been demonstrated to be more effective for suppressing of this parasitic SL mode [18]. Based on this, shield-CPW electrode has been utilized on LiNbO3 modulators [19]. Nevertheless, there is no report on applying this shield-CPW electrode on silicon modulators. In this work, we implemented a shield-CPW electrode to suppress the unwanted SL modes in silicon modulator. For illustration, with a 5.5 mm-long phase shifter, the driving voltage V pp is reduced to be less than 1.3 V in a single-end MZI silicon modulator to achieve a 28-Gb/s data rate and above 24 GHz EO-S21 −3 dB bandwidth with a power consumption of 0.8 pJ/bit……...” [Tu, Abstract, p. 2-3, Fig. 1.].
Additionally, Chen teaches a metal shield associated with an optical modulator and positioned to block the electromagnetic field of the driving signal from extending into the substrate, and further teaches the receiver-sensitivity and crosstalk problems associated with driver-to-TIA coupling “[0008] One solution to avoid the undesired RF absorption loss induced by the silicon substrate is to use high resistivity silicon substrates (e.g., with a resistivity of 750 ohm-cm). Using a high-resistivity silicon substrate poses two possible problems. First, a high-resistivity substrate may become a limitation in wafer availability or foundry fabrication processes (such as through silicon via processes). Second, while the high-resistivity substrate avoids RF absorption loss of the driving signals of the modulators, RF crosstalk between one integrated circuit to another integrated circuit on the same silicon substrate is significantly degraded, particularly with regard to long-range crosstalk. This is because radiated electromagnetic energy is freely propagating inside the substrate without any damping, from one circuit to another even if the two circuits are separated by more than 2 millimeters. Such long-range RF crosstalk is particularly problematic from an output of a driver circuit to the input of a transimpedance- amplifier (TIA) circuit because of the large gain of the driver and TIA. In many cases, even a crosstalk level of -70 decibels between driver output to TIA input would induce notable penalty in receiver sensitivity. [0009] Another solution is to engineer silicon substrates to have two types of resistivity - high resistivity in the immediate area near the traveling-wave modulator and a low resistivity in other regions. However, this solution requires complex fabrication cycles in the silicon substrate. [0010] Embodiments described herein provide for inserting one or more metal layers between the optical modulator and the silicon substrates as an RF shield. The metal shield stops the electromagnetic field of the driving signal from reaching the silicon substrate and may reduce or eliminate the substrate RF absorption loss over a wide range of silicon substrate resistivities (e.g., from 0.1 ohm-cm and > 1000 ohm-cm). In addition, the metal shield allows the use of a low resistivity substrate (e.g., between 1 ohm-cm and 20 ohm-cm), when the RF absorption loss can be very high outside the RF shield region, which can be used to considerably suppress the long-range RF crosstalk from one circuit to another circuit on the same substrate. RF simulation shows that the long-range RF crosstalk can be suppressed by more than 10 decibels with proper design parameters compared with high-resistivity substrates. [0015] Semiconductor device 100 includes a metal shield 110 formed/embedded in the dielectric 140. Metal shield 110 may be referred to herein as an RF shield, a metal layer, or a metal shield layer. Metal shield 110 may block the electromagnetic field of the modulator 180 from reaching substrate 150. Substrate 150 may include a silicon substrate. In some embodiments, substrate 150 may be a low resistivity silicon substrate. Embedding metal shield 110 between modulator 180 and substrate 150 allows the use of a low resistivity substrate without degrading the performance of modulator 180 and, at the same time, significantly improving the RF crosstalk between transmitter and receiver circuits. Using the low resistivity substrate allows for regions where low RF losses are desired to be shielded with the metal while leaving other regions without shielding to attenuate stray fields and reduce RF crosstalk. Away from transmission lines, particular in power/ground planes, the use of a low resistivity silicon substrate 150 maximizes damping and suppression of RF crosstalk. [0016] In some embodiments, the metal shield 110 may be a solid metal layer or a series of solid metal blocks underneath modulator 180. In some embodiments, metal shield 110 may be patterned. For example, under transmission lines, a pattern may be added to metal shield 110 to insulate the electromagnetic field from substrate 150 to avoid extra RF loss. In some embodiments, metal shield 110 may be patterned with slots or patterned into connected or isolated bars across the differential electrodes 130 at various intervals. Patterning the metal shield 110 into discrete bars provides RF shielding by terminating the RF shield lines without carrying current along the transmission line (and, therefore, without suffering the extra RF loss typically associated with, for example, a solid metal shield). [0017] In some embodiments, metal shield 110 may be floating and not connected to any other electrodes. In other embodiments, metal shield may be electrically coupled to other metals or electrodes… Claims 1. A device comprising: an optical modulator formed in a dielectric material; a silicon substrate adjacent the dielectric material; and a metal shield formed in the dielectric material between the optical modulator and the silicon substrate, the metal shield blocking an electromagnetic field of a driving signal of the optical modulator from extending into the silicon substrate” [Chen, ¶¶ [0008] - [0010], [0015] - [0017]; claim 1].
Collectively, these references teach a transceiver comprising a set of MZMs and a set of electromagnetic confinement components at least partially surrounding the MZMs, positioned to electromagnetically confine a first transmission with respect to a second transmission or a reception, wherein at least one such confinement component is connected to ground.
A person of ordinary skill in the art would have been motivated to employ Tu’s and Chen's known shielding/confinement structures in Evans’s transceiver PIC in order to confine RF energy around the MZM drive structures, reduce coupling into neighboring transmit or receive paths, and improve high-speed RF performance. The combination would have yielded no more than the predictable use of known modulator-shielding structures in a known transceiver PIC environment.
Further, a person of ordinary skill in the art would have been motivated to implement Tu's and Chen's known electromagnetic-confinement structures in Evans's transceiver PIC because Evans places transmitter and receiver functionality in a common photonic package where RF coupling risks are especially significant. Tu teaches that a shielded MZM transmission structure improves bandwidth by suppressing parasitic modes, while Chen teaches that an RF shield at the modulator/substrate interface reduces substrate-coupled crosstalk and receiver penalty. Applying those known shielding techniques in Evans's known transceiver environment would therefore have been the natural and predictable way to improve channel isolation, signal integrity, and receiver sensitivity in a dense high-speed transceiver.
Claim 20
With respect to claim 20, all limitations of claim 18 are taught by Evans, Tu, and Chen, except wherein claim 20 additionally requires that the set of electromagnetic confinement components are disposed above or adjacent to the MZM. However, within analogous art, Tu expressly teaches shield-CPW electrodes adjacent to the silicon MZI modulator transmission structure “With a shield coplanar waveguide (CPW) transmission line electrode design was demonstrated. This shield-CPW electrode suppresses the signal distortion caused by the parasitic slot-line (SL) mode and improves the electrical bandwidth and the electro-optical (EO) bandwidth. With the shield-CPW electrodes and 5.5 mm-long phase shifters, the silicon MZI optical modulator delivered an EO bandwidth of above 24 GHz and a V π = 3.0 V was achieved at λ = 1310nm. When modulated at 28-Gb/s data rate, it achieved an extinction ratio of 5.66 dB under a driving voltage of V pp = 1.3 V, corresponding to a power consumption of 0.8 pJ/bit……. The emerging silicon photonics technology has received intense research and development efforts by the optical communication industry due to its superior advantages such as small die sizes, low cost and high integration capability [1–4]. Silicon modulator is one of the most important components for high quality and large volume of data uploading in the future fiberoptic network. Since the comprehensive study of electro-optical (EO) effect in silicon material in 1987 [5], silicon EO modulator has achieved remarkable progress. Recently with reverse biased p-n junction, the data rate of silicon optical modulator has reached over 50-Gb/s for both of 1310 nm and 1550 nm [6–10]. The aggregated data rate and modulation efficiency may be further increased by utilizing the amplitude-shift keying (ASK) and phase-shift keying (PSK) technologies [11, 12]. Chip-scale integration of silicon modulators with wavelength division multiplexing (WDM) multiplexers as well as III-V lasers were also demonstrated [13,14]. For all practical applications, low power consumption and driving voltage are critical performance requitement. That is why in the past, optical modulator fabricated by LiNbO3 and compound material was usually made to have a long phase shifting length. However, such long phase shifter also introduces high microwave loss and velocity mismatching which limit the EO bandwidth. Typically, travelling-wave electrode is implemented to reduce the driving voltage while maintain high EO bandwidth. Coplanar waveguide (CPW) and slot-line (SL) waveguide are two of the most common travelling-wave electrode designs. Between them, CPW is more popular for the advantages of low dispersion, low radiation and the ease of shunt and series connections. However, SL mode can be triggered by the asymmetric CPW electrodes, which in turn becomes the main obstacle for its implementation in practice [15]. When applying CPW electrodes onto optical modulator, the parasitic SL mode can induce strong microwave reflection which suppresses the bandwidth of the modulator. A simple wire-bonding method has been utilized to eliminate this parasitic SL mode [16], but it is not effective and also this approach is not compatible with CMOS process [17]. An air bridge technique, where a shield metal layer is added on top of CPW, has been demonstrated to be more effective for suppressing of this parasitic SL mode [18]. Based on this, shield-CPW electrode has been utilized on LiNbO3 modulators [19]. Nevertheless, there is no report on applying this shield-CPW electrode on silicon modulators. In this work, we implemented a shield-CPW electrode to suppress the unwanted SL modes in silicon modulator. For illustration, with a 5.5 mm-long phase shifter, the driving voltage V pp is reduced to be less than 1.3 V in a single-end MZI silicon modulator to achieve a 28-Gb/s data rate and above 24 GHz EO-S21 −3 dB bandwidth with a power consumption of 0.8 pJ/bit……...” [Tu, Abstract, p. 2-3, Fig. 1.].
Further, a person of ordinary skill in the art would have been motivated to dispose the electromagnetic confinement components above or adjacent to the MZM because shielding effectiveness depends strongly on proximity to the field source. Tu places the shield/ground structure adjacent to the silicon MZI transmission line, and Chen places the shield between the modulator and the substrate, i.e., immediately adjacent to the modulator in cross-section. A skilled artisan therefore would have located the confinement components as near the MZM as the packaging and routing constraints permitted, including above-adjacent placements, in order to maximize interception of the RF field and minimize parasitic coupling into nearby structures.
Claim 19 is rejected under 35 U.S.C. § 103 as being unpatentable over Evans et al., in view of Tu et al., and further in view of Chen et al. and further in view of Tavlykaev et al. and Nelson et al.
Claim 19
Because claim 19 is written in the alternative using “at least one of,” the rejection is satisfied when the cited art teaches one or more of the listed known confinement-component implementations. Here, the combined references teach multiple such implementations at once PIC-side ground structures, bond-wire bridges, vias or substrate-level grounding connections, and micro-bumps thereby reinforcing, not weakening, the obviousness conclusion. A skilled artisan would have viewed those recited items as interchangeable or complementary conductive features for establishing electromagnetic confinement at different layers of the same PIC package stack.
With respect to claim 19, all limitations of claim 18 are taught by Evans, Tu, and Chen, except wherein claim 19 additionally requires that the electromagnetic confinement components include at least one of a ground pour on a PIC, a ground plane on a substrate, a bonding wire, a micro-bump, a TSV on the PIC, or a via in the substrate. However, within analogous art, Evans teaches ground traces, conductive vias, and transceiver-PIC package interconnections “……FIGS. lA-lD illustrate example arrangements where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having an optical device. FIGS. 2A-2C illustrate a package where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having an optical device. FIGS. 3A-3E illustrate example PIC and interposer lay- 50 outs. FIGS. 4A-4E illustrate example arrangements where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having a traveling wave optical device. FIG. 5 illustrates a package where an interposer provides electrical interconnects between a ASIC chip and a PIC chip having a traveling wave optical device. FIGS. 6A-6C illustrate example PIC and interposer layouts. FIGS. 7A-7B illustrate example PIC and interposer layouts for matching electrical and optical waves. FIG. 8 illustrates example PIC and interposer layouts. FIGS. 9A, 9B, l0A-lOC, llA-llC, 12A-12C, 13A-13D, 14A-14C, and 15A-15C show example packaging arrangements. FIG. 16 illustrates a block diagram of an example multichannel transmitter PIC……...FIGS. 34 and 35 illustrate example PIC packaging arrangements that show advantages of using an interposer or a bridge chip to electrically couple active optical elements on a PIC chip and circuitry on an ASIC chip. Referring to FIG. 34, the arrangement 3400 includes a TX PIC chip 3410 and a MZMD chip 3420. The TX PIC chip 3410 includes multiple MZM arms 3402 that are in the interior of the TX PIC chip 3410. The MZM arms 3402 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3420. As illustrated in FIG. 34, if wire bonds are used to establish the electrical connections between the MZM arms 3402 and the MZMD circuit, the distance between the MZM arms 3402 and the MZMD chip 3420 may be greater than 1 mm, which may increase complexity in wiring and may negatively impact the device performance at high speed. Flip-chip or wafer bonding between the TX PIC chip 3410 and the MZMD chip 3420 significantly decreases the wiring length, and allows more complex arrangements of the optical elements on the PIC chip. Referring to FIG. 35, the arrangement 3500 includes a TX PIC chip 3510 and a MZMD chip 3520. The TX PIC chip 3510 includes multiple MZM arms 3502 that are arranged along the edge of the TX PIC chip 3510. The MZM arms 3502 are electrically coupled to and controlled by the MZMD circuit on the MZMD chip 3520. As illustrated in FIG. 35, if wire bonds are used to establish the electrical…….” [Evans. col. 1, col. 4, col. 14].
Additionally, Tu and Tavlykaev teach PIC-side ground structures and bonding-wire style connections associated with MZM shielding/interconnection “With a shield coplanar waveguide (CPW) transmission line electrode design was demonstrated. This shield-CPW electrode suppresses the signal distortion caused by the parasitic slot-line (SL) mode and improves the electrical bandwidth and the electro-optical (EO) bandwidth. With the shield-CPW electrodes and 5.5 mm-long phase shifters, the silicon MZI optical modulator delivered an EO bandwidth of above 24 GHz and a V π = 3.0 V was achieved at λ = 1310nm. When modulated at 28-Gb/s data rate, it achieved an extinction ratio of 5.66 dB under a driving voltage of V pp = 1.3 V, corresponding to a power consumption of 0.8 pJ/bit” [Tu, Abstract, Fig. 1].
“……. [0006] The electrode structure shown in FIG. 1 is a microwave Coplanar Waveguide (CPW) aligned with respect to the waveguide Structure in Such a way that the interferometer arms 104,105 are positioned in the electrode gaps 107 and run alongside the gap edges (in X-cut devices). A CPW electrode structure includes a hot central (signal) electrode 108 and two ground planes or electrodes 109,110 formed on opposite sides of the central electrode 108. Microwave (modulating) signals are provided to the signal electrode 108 from a microwave Source 111, via a connector and a microwave cable. The widths of the gap 107 and hot electrode 108 are tapered at the input and output. Advantageously, a CPW structure with properly chosen widths of the gap 107 and hot electrode 108 at the modulator input has a microwave field distribution closely matching that of a coaxial cable connecting the modulator to the microwave Source 111.…. [0039] Furthermore, efficient conversion of the RF power from the gap 412 not used for modulation to the other, can be achieved by employing bond wires (air bridges) 411 at the CPW/CPS transitions, as described above. For optimum operation, the gaps 412,415 and hot electrode 405 widths of the CPS and CPW segments should be designed to provide good impedance and mode matching between them. AS an example, the hot electrode widths for the CPW and CPS Segments can be chosen to be continuous acroSS the transition, as shown in FIG. 4. In this case, CPW gap 412 should be made wider than CPS gap 415, since if they were equal, the CPW segments 401, 402 would have a lower impedance than the CPS Segment 403, causing an impedance discontinuity at the transitions and microwave reflection. If the difference between gapS 412 and 415 is significant enough to cause microwave mode mismatch and radiation loSS, chamfered transitions can be employed, as is well known and detailed in microwave techniques. If the CPW/CPS transition is optimized, following these rules, the conversion efficiency is known to exceed 90%.” [Tavlykaev, ¶¶ [0005]-[0007], [0036]-[0039]].
Within analogous art, Nelson teaches micro-bumps/copper pillar bumps in a PIC/EIC transceiver package “…...[0039] Each of the copper pillar bumps 140 may have a diameter of between 25 um (microns) and 100 um and a height of between 25 um and 100 um. Each of the copper pillar bumps 140 may be formed on a pad opening (e.g., an opening in an insulating (e.g., silicon dioxide) layer on the front surface of the photonic integrated circuit 105) having a diameter of between 10 um and 70 um. [0040] Referring to FIG. 2A, the copper pillar bumps 140 in the area of overlap 135 may be on a grid (e.g., a grid with a pitch between 50 um and 150 um) substantially filling the area of overlap 135, which may be rectangular as shown. In some embodiments, the corner bumps may be omitted as shown, for stress relief. The pads 145 (e.g., Ni / Au pads) on the electronic integrated circuit 110 may have a diameter exceeding 100 um (in an embodiment in which the pitch of the grid exceeds 100 um). The pitch of the copper pillar bumps 140 may be chosen based on design channel count and density. For example, reducing bump pitch (and channel pitch accordingly) reduces the width of the PIC 105 and electronic integrated circuit 110. A reduction in chip width increases bandwidth density and reduces overall product form factor within high volume manufacturing limits. For example, in some embodiments the optical engines dis cussed herein are populated on the edge of the printed circuit board 310 which may form the substrate of the switch ASIC package (FIG. 5. This substrate form factor is ultimately determined by the widths of the PIC 105 and the electronic integrated circuit 110, which is dependent on bump pitch. Furthermore, reducing the substrate form factor improves the aforementioned serializer - deserializer performance and reduces cost in high volume. This is discussed in further detail below. Each of the high-speed channels 150 may be connected by a pair of conductive traces on the front surface of the electronic integrated circuit 110 to a respective pair of pads, or "connector bumps” (e.g., Ni / Au pads) in the first portion 115 of the front surface of the electronic integrated circuit 110 as part of a connection (e.g., an XSR or USR connection, or other suitable serial electrical connection) to, e.g., a switch ASIC, as discussed in further detail below. The pads in the first portion 115 of the front surface of the electronic integrated circuit 110 may be similar to, although they may have different dimensions from, the pads on the front surface of the electronic integrated circuit 110 in the area of overlap 135. FIG. 2B shows an example of a candidate pin assignment for the connector bumps. The corner connector bumps may be absent (as shown in FIG. 2A) or present (as shown in FIG. 2B) …...” [Nelson ¶¶ [0038] - [0040]].
Further, a person of ordinary skill in the art would have been motivated to implement the electromagnetic confinement components using one or more of a ground pour, substrate ground plane, bonding wire, micro-bump, TSV, or substrate via because each of those items was already a known conductive feature used in the cited PIC package stack either to establish ground reference, to couple layers, or to form shielding paths. Tu and Tavlykaev supply PIC-side ground structures and bond-wire bridges, Evans supplies ground traces and vias, Nelson supplies micro-bumps, and Chen supplies the concept of a grounded shield relative to the modulator/substrate arrangement. A skilled artisan would have treated those listed features as complementary implementation choices for providing electromagnetic confinement at different layers of the package, which is a routine design optimization rather than an inventive leap.
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
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/MOHAMMED ABDELRAHEEM/Examiner, Art Unit 2635
/DAVID C PAYNE/Supervisory Patent Examiner, Art Unit 2635